2007-07-03 04:45:50 +02:00
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/* natsemi.c - gPXE driver for the NatSemi DP8381x series. */
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/*
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2007-06-19 00:30:33 +02:00
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2007-07-03 04:45:50 +02:00
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natsemi.c: An Etherboot driver for the NatSemi DP8381x series.
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Copyright (C) 2001 Entity Cyber, Inc.
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This development of this Etherboot driver was funded by
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Sicom Systems: http://www.sicompos.com/
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Author: Marty Connor (mdc@thinguin.org)
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Adapted from a Linux driver which was written by Donald Becker
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This software may be used and distributed according to the terms
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of the GNU Public License (GPL), incorporated herein by reference.
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Original Copyright Notice:
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Written/copyright 1999-2001 by Donald Becker.
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This software may be used and distributed according to the terms of
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the GNU General Public License (GPL), incorporated herein by reference.
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Drivers based on or derived from this code fall under the GPL and must
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retain the authorship, copyright and license notice. This file is not
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a complete program and may only be used when the entire operating
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system is licensed under the GPL. License for under other terms may be
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available. Contact the original author for details.
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The original author may be reached as becker@scyld.com, or at
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Scyld Computing Corporation
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410 Severn Ave., Suite 210
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Annapolis MD 21403
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Support information and updates available at
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http://www.scyld.com/network/netsemi.html
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References:
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http://www.scyld.com/expert/100mbps.html
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http://www.scyld.com/expert/NWay.html
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Datasheet is available from:
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http://www.national.com/pf/DP/DP83815.html
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*/
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/* Revision History */
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2005-03-08 19:53:11 +01:00
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2007-07-03 04:45:50 +02:00
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/*
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2007-07-08 17:03:30 +02:00
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02 JUL 2007 Udayan Kumar 1.2 ported the driver from etherboot to gPXE API.
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Fully rewritten,adapting the old driver.
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2007-07-08 02:42:53 +02:00
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Added a circular buffer for transmit and receive.
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transmit routine will not wait for transmission to finish.
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poll routine deals with it.
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2007-07-03 04:45:50 +02:00
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2007-07-08 02:42:53 +02:00
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13 Dec 2003 timlegge 1.1 Enabled Multicast Support
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29 May 2001 mdc 1.0
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Initial Release. Tested with Netgear FA311 and FA312 boards
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2005-03-08 19:53:11 +01:00
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*/
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2007-07-03 04:45:50 +02:00
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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#include <stdint.h>
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2007-07-05 14:38:37 +02:00
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#include <pic8259.h>
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2007-06-19 00:30:33 +02:00
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#include <stdlib.h>
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#include <stdio.h>
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#include <io.h>
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#include <errno.h>
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#include <timer.h>
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#include <byteswap.h>
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2007-07-05 14:54:12 +02:00
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#include <gpxe/pci.h>
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2007-06-19 00:30:33 +02:00
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#include <gpxe/if_ether.h>
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2007-07-05 14:54:12 +02:00
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#include <gpxe/ethernet.h>
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2007-06-19 00:30:33 +02:00
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#include <gpxe/iobuf.h>
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#include <gpxe/netdevice.h>
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#include <gpxe/spi_bit.h>
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#include <gpxe/threewire.h>
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#include <gpxe/nvo.h>
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2007-07-10 21:08:58 +02:00
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#include <mii.h>
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2007-06-19 00:30:33 +02:00
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#define TX_RING_SIZE 4
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#define NUM_RX_DESC 4
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2007-07-03 04:45:50 +02:00
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#define RX_BUF_SIZE 1536
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#define OWN 0x80000000
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#define DSIZE 0x00000FFF
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#define CRC_SIZE 4
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2007-06-19 00:30:33 +02:00
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struct natsemi_tx {
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uint32_t link;
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uint32_t cmdsts;
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uint32_t bufptr;
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};
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2007-07-07 17:40:58 +02:00
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2007-06-19 00:30:33 +02:00
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struct natsemi_rx {
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uint32_t link;
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uint32_t cmdsts;
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uint32_t bufptr;
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};
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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struct natsemi_nic {
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unsigned short ioaddr;
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2007-06-21 01:07:04 +02:00
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unsigned short tx_cur;
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unsigned short tx_dirty;
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unsigned short rx_cur;
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2007-06-19 00:30:33 +02:00
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struct natsemi_tx tx[TX_RING_SIZE];
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struct natsemi_rx rx[NUM_RX_DESC];
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2007-07-09 00:41:12 +02:00
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2007-06-21 01:07:04 +02:00
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/* need to add iobuf as we cannot free iobuf->data in close without this
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* alternatively substracting sizeof(head) and sizeof(list_head) can also
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2007-07-07 22:07:30 +02:00
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* give the same.
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*/
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2007-06-21 01:07:04 +02:00
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struct io_buffer *iobuf[NUM_RX_DESC];
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2007-07-09 00:41:12 +02:00
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2007-07-07 22:07:30 +02:00
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/* netdev_tx_complete needs pointer to the iobuf of the data so as to free
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* it from the memory.
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*/
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2007-07-02 00:05:58 +02:00
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struct io_buffer *tx_iobuf[TX_RING_SIZE];
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2007-06-19 00:30:33 +02:00
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struct spi_bit_basher spibit;
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struct spi_device eeprom;
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struct nvo_block nvo;
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2005-03-08 19:53:11 +01:00
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};
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2007-07-10 21:08:58 +02:00
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/*
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* Support for fibre connections on Am79C874:
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* This phy needs a special setup when connected to a fibre cable.
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* http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
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*/
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#define PHYID_AM79C874 0x0022561b
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enum {
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MII_MCTRL = 0x15, /* mode control register */
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MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
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MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
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};
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/* values we might find in the silicon revision register */
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#define SRR_DP83815_C 0x0302
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#define SRR_DP83815_D 0x0403
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#define SRR_DP83816_A4 0x0504
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#define SRR_DP83816_A5 0x0505
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2007-06-19 00:30:33 +02:00
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/* NATSEMI: Offsets to the device registers.
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2007-07-07 22:07:30 +02:00
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* Unlike software-only systems, device drivers interact with complex hardware.
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* It's not useful to define symbolic names for every register bit in the
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* device.
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*/
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2005-03-08 19:53:11 +01:00
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enum register_offsets {
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ChipCmd = 0x00,
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ChipConfig = 0x04,
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EECtrl = 0x08,
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PCIBusCfg = 0x0C,
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IntrStatus = 0x10,
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IntrMask = 0x14,
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IntrEnable = 0x18,
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TxRingPtr = 0x20,
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TxConfig = 0x24,
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RxRingPtr = 0x30,
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RxConfig = 0x34,
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ClkRun = 0x3C,
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WOLCmd = 0x40,
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PauseCmd = 0x44,
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RxFilterAddr = 0x48,
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RxFilterData = 0x4C,
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BootRomAddr = 0x50,
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BootRomData = 0x54,
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SiliconRev = 0x58,
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StatsCtrl = 0x5C,
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StatsData = 0x60,
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RxPktErrs = 0x60,
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RxMissed = 0x68,
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RxCRCErrs = 0x64,
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PCIPM = 0x44,
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PhyStatus = 0xC0,
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MIntrCtrl = 0xC4,
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MIntrStatus = 0xC8,
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2007-07-09 00:41:12 +02:00
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2007-07-08 02:42:53 +02:00
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/* These are from the spec, around page 78... on a separate table.
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*/
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2005-03-08 19:53:11 +01:00
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PGSEL = 0xCC,
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PMDCSR = 0xE4,
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TSTDAT = 0xFC,
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DSPCFG = 0xF4,
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2007-06-19 00:30:33 +02:00
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SDCFG = 0x8C,
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BasicControl = 0x80,
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BasicStatus = 0x84
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2005-03-08 19:53:11 +01:00
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};
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2007-07-10 19:29:30 +02:00
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/* the values for the 'magic' registers above (PGSEL=1) */
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#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
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#define TSTDAT_VAL 0x0
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#define DSPCFG_VAL 0x5040
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#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
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#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
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#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
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#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
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2007-07-08 02:42:53 +02:00
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/* Bit in ChipCmd.
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*/
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2005-03-08 19:53:11 +01:00
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enum ChipCmdBits {
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ChipReset = 0x100,
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RxReset = 0x20,
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TxReset = 0x10,
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RxOff = 0x08,
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RxOn = 0x04,
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TxOff = 0x02,
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TxOn = 0x01
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2007-06-21 01:46:22 +02:00
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};
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2007-06-19 00:30:33 +02:00
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2007-07-10 19:29:30 +02:00
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enum ChipConfig_bits {
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CfgPhyDis = 0x200,
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CfgPhyRst = 0x400,
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CfgExtPhy = 0x1000,
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CfgAnegEnable = 0x2000,
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CfgAneg100 = 0x4000,
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CfgAnegFull = 0x8000,
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CfgAnegDone = 0x8000000,
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CfgFullDuplex = 0x20000000,
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CfgSpeed100 = 0x40000000,
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CfgLink = 0x80000000,
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};
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2007-07-08 02:42:53 +02:00
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/* Bits in the RxMode register.
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*/
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2005-03-08 19:53:11 +01:00
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0xC0000000,
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AcceptMulticast = 0x00200000,
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AcceptAllMulticast = 0x20000000,
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AcceptAllPhys = 0x10000000,
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AcceptMyPhys = 0x08000000,
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RxFilterEnable = 0x80000000
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};
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2007-07-08 02:42:53 +02:00
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/* Bits in network_desc.status
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*/
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2005-03-08 19:53:11 +01:00
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enum desc_status_bits {
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DescOwn = 0x80000000,
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DescMore = 0x40000000,
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DescIntr = 0x20000000,
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DescNoCRC = 0x10000000,
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DescPktOK = 0x08000000,
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RxTooLong = 0x00400000
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};
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2007-07-08 02:42:53 +02:00
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/*Bits in Interrupt Mask register
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*/
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2007-07-04 01:29:31 +02:00
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enum Intr_mask_register_bits {
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RxOk = 0x001,
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RxErr = 0x004,
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TxOk = 0x040,
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TxErr = 0x100
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};
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2005-03-08 19:53:11 +01:00
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2007-07-08 02:42:53 +02:00
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/* EEPROM access , values are devices specific
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*/
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2007-06-19 00:30:33 +02:00
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#define EE_CS 0x08 /* EEPROM chip select */
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#define EE_SK 0x04 /* EEPROM shift clock */
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2007-06-26 23:20:34 +02:00
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#define EE_DI 0x01 /* Data in */
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#define EE_DO 0x02 /* Data out */
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2005-03-08 19:53:11 +01:00
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2007-07-08 02:42:53 +02:00
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/* Offsets within EEPROM (these are word offsets)
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*/
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2007-06-19 00:30:33 +02:00
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#define EE_MAC 7
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2007-06-26 23:20:34 +02:00
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#define EE_REG EECtrl
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2007-06-19 00:30:33 +02:00
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static uint32_t SavedClkRun;
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2005-03-08 19:53:11 +01:00
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2007-06-26 23:20:34 +02:00
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static const uint8_t nat_ee_bits[] = {
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2007-06-19 00:30:33 +02:00
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[SPI_BIT_SCLK] = EE_SK,
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[SPI_BIT_MOSI] = EE_DI,
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[SPI_BIT_MISO] = EE_DO,
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2007-06-26 23:20:34 +02:00
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[SPI_BIT_SS(0)] = EE_CS,
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2007-07-07 17:40:58 +02:00
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};
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2005-03-08 19:53:11 +01:00
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2007-06-26 23:20:34 +02:00
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static int nat_spi_read_bit ( struct bit_basher *basher,
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2007-06-19 00:30:33 +02:00
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unsigned int bit_id ) {
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2007-06-26 23:20:34 +02:00
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struct natsemi_nic *nat = container_of ( basher, struct natsemi_nic,
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2007-06-19 00:30:33 +02:00
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spibit.basher );
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2007-06-26 23:20:34 +02:00
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uint8_t mask = nat_ee_bits[bit_id];
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2007-06-19 00:30:33 +02:00
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uint8_t eereg;
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2005-03-08 19:53:11 +01:00
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2007-07-09 00:41:12 +02:00
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eereg = inb ( nat->ioaddr + EE_REG );
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2007-06-19 00:30:33 +02:00
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return ( eereg & mask );
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2007-07-07 17:40:58 +02:00
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}
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2005-03-08 19:53:11 +01:00
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2007-06-26 23:20:34 +02:00
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static void nat_spi_write_bit ( struct bit_basher *basher,
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2007-06-19 00:30:33 +02:00
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unsigned int bit_id, unsigned long data ) {
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2007-06-26 23:20:34 +02:00
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struct natsemi_nic *nat = container_of ( basher, struct natsemi_nic,
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2007-06-19 00:30:33 +02:00
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spibit.basher );
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2007-06-26 23:20:34 +02:00
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uint8_t mask = nat_ee_bits[bit_id];
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2007-06-19 00:30:33 +02:00
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uint8_t eereg;
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2007-06-26 23:20:34 +02:00
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eereg = inb ( nat->ioaddr + EE_REG );
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2007-06-19 00:30:33 +02:00
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eereg &= ~mask;
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eereg |= ( data & mask );
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2007-07-09 00:41:12 +02:00
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outb ( eereg, nat->ioaddr + EE_REG );
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2007-07-07 17:40:58 +02:00
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}
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2005-03-08 19:53:11 +01:00
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2007-06-26 23:20:34 +02:00
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static struct bit_basher_operations nat_basher_ops = {
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.read = nat_spi_read_bit,
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.write = nat_spi_write_bit,
|
2007-06-19 00:30:33 +02:00
|
|
|
};
|
2007-07-07 22:07:30 +02:00
|
|
|
|
|
|
|
/* It looks that this portion of EEPROM can be used for
|
|
|
|
* non-volatile stored options. Data sheet does not talk about this region.
|
|
|
|
* Currently it is not working. But with some efforts it can.
|
2007-07-07 17:40:58 +02:00
|
|
|
*/
|
2007-06-26 23:20:34 +02:00
|
|
|
static struct nvo_fragment nat_nvo_fragments[] = {
|
2007-07-07 22:07:30 +02:00
|
|
|
{ 0x0c, 0x68 },
|
2007-06-19 00:30:33 +02:00
|
|
|
{ 0, 0 }
|
|
|
|
};
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
/*
|
2007-06-19 00:30:33 +02:00
|
|
|
* Set up for EEPROM access
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v NAT NATSEMI NIC
|
2007-07-07 17:40:58 +02:00
|
|
|
*/
|
2007-06-26 23:20:34 +02:00
|
|
|
void nat_init_eeprom ( struct natsemi_nic *nat ) {
|
2007-06-19 00:30:33 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Initialise three-wire bus
|
|
|
|
*/
|
2007-06-26 23:20:34 +02:00
|
|
|
nat->spibit.basher.op = &nat_basher_ops;
|
|
|
|
nat->spibit.bus.mode = SPI_MODE_THREEWIRE;
|
2007-07-01 23:11:22 +02:00
|
|
|
nat->spibit.endianness = SPI_BIT_LITTLE_ENDIAN;
|
2007-06-26 23:20:34 +02:00
|
|
|
init_spi_bit_basher ( &nat->spibit );
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/*natsemi DP 83815 only supports at93c46
|
|
|
|
*/
|
2007-06-26 23:20:34 +02:00
|
|
|
init_at93c46 ( &nat->eeprom, 16 );
|
|
|
|
nat->eeprom.bus = &nat->spibit.bus;
|
2007-06-19 00:30:33 +02:00
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
nat->nvo.nvs = &nat->eeprom.nvs;
|
|
|
|
nat->nvo.fragments = nat_nvo_fragments;
|
2007-07-07 17:40:58 +02:00
|
|
|
}
|
2007-06-26 23:20:34 +02:00
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
/*
|
2007-06-19 00:30:33 +02:00
|
|
|
* Reset NIC
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-21 01:07:04 +02:00
|
|
|
* @v NATSEMI NIC
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* Issues a hardware reset and waits for the reset to complete.
|
2007-07-07 17:40:58 +02:00
|
|
|
*/
|
2007-06-21 01:46:22 +02:00
|
|
|
static void nat_reset ( struct natsemi_nic *nat ) {
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-21 01:07:04 +02:00
|
|
|
int i;
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Reset chip
|
|
|
|
*/
|
2007-06-21 01:46:22 +02:00
|
|
|
outl ( ChipReset, nat->ioaddr + ChipCmd );
|
2007-06-19 00:30:33 +02:00
|
|
|
mdelay ( 10 );
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->tx_dirty = 0;
|
|
|
|
nat->tx_cur = 0;
|
|
|
|
for ( i = 0 ; i < TX_RING_SIZE ; i++ ) {
|
|
|
|
nat->tx[i].link = 0;
|
|
|
|
nat->tx[i].cmdsts = 0;
|
|
|
|
nat->tx[i].bufptr = 0;
|
2007-06-21 01:07:04 +02:00
|
|
|
}
|
|
|
|
nat->rx_cur = 0;
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( virt_to_bus( &nat->tx[0] ),nat->ioaddr + TxRingPtr );
|
|
|
|
outl ( virt_to_bus( &nat->rx[0] ),nat->ioaddr + RxRingPtr );
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( TxOff|RxOff, nat->ioaddr + ChipCmd );
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Restore PME enable bit
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( SavedClkRun, nat->ioaddr + ClkRun );
|
2007-07-07 17:40:58 +02:00
|
|
|
}
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-07-10 21:08:58 +02:00
|
|
|
|
|
|
|
static int mdio_read(struct net_device *netdev, int reg) {
|
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
|
|
|
|
/* The 83815 series has two ports:
|
|
|
|
* - an internal transceiver
|
|
|
|
* - an external mii bus
|
|
|
|
*/
|
|
|
|
return inw(nat->ioaddr+BasicControl+(reg<<2));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mdio_write(struct net_device *netdev, int reg, u16 data) {
|
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
|
|
|
|
/* The 83815 series has an internal transceiver; handle separately */
|
|
|
|
writew(data, nat->ioaddr+BasicControl+(reg<<2));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void init_phy_fixup(struct net_device *netdev) {
|
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
int i;
|
|
|
|
u32 cfg;
|
|
|
|
u16 tmp;
|
|
|
|
uint16_t advertising;
|
|
|
|
int mii;
|
|
|
|
|
|
|
|
/* restore stuff lost when power was out */
|
|
|
|
tmp = mdio_read(netdev, MII_BMCR);
|
|
|
|
advertising= mdio_read(netdev, MII_ADVERTISE);
|
|
|
|
// if (np->autoneg == AUTONEG_ENABLE) {
|
|
|
|
/* renegotiate if something changed */
|
|
|
|
if ((tmp & BMCR_ANENABLE) == 0
|
|
|
|
|| advertising != mdio_read(netdev, MII_ADVERTISE))
|
|
|
|
{
|
|
|
|
/* turn on autonegotiation and force negotiation */
|
|
|
|
tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
|
|
|
|
mdio_write(netdev, MII_ADVERTISE, advertising);
|
|
|
|
}
|
|
|
|
// } else {
|
|
|
|
/* turn off auto negotiation, set speed and duplexity */
|
|
|
|
// tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
|
|
|
|
// if (np->speed == SPEED_100)
|
|
|
|
/// tmp |= BMCR_SPEED100;
|
|
|
|
// if (np->duplex == DUPLEX_FULL)
|
|
|
|
// tmp |= BMCR_FULLDPLX;
|
|
|
|
/*
|
|
|
|
* Note: there is no good way to inform the link partner
|
|
|
|
* that our capabilities changed. The user has to unplug
|
|
|
|
* and replug the network cable after some changes, e.g.
|
|
|
|
* after switching from 10HD, autoneg off to 100 HD,
|
|
|
|
* autoneg off.
|
|
|
|
*/
|
|
|
|
// }
|
|
|
|
mdio_write(netdev, MII_BMCR, tmp);
|
|
|
|
inl(nat->ioaddr + ChipConfig);
|
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
/* find out what phy this is */
|
|
|
|
mii = (mdio_read(netdev, MII_PHYSID1) << 16)
|
|
|
|
+ mdio_read(netdev, MII_PHYSID2);
|
|
|
|
|
|
|
|
/* handle external phys here */
|
|
|
|
switch (mii) {
|
|
|
|
case PHYID_AM79C874:
|
|
|
|
/* phy specific configuration for fibre/tp operation */
|
|
|
|
tmp = mdio_read(netdev, MII_MCTRL);
|
|
|
|
tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
|
|
|
|
//if (dev->if_port == PORT_FIBRE)
|
|
|
|
// tmp |= MII_FX_SEL;
|
|
|
|
//else
|
|
|
|
tmp |= MII_EN_SCRM;
|
|
|
|
mdio_write(netdev, MII_MCTRL, tmp);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
cfg = inl(nat->ioaddr + ChipConfig);
|
|
|
|
if (cfg & CfgExtPhy)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* On page 78 of the spec, they recommend some settings for "optimum
|
|
|
|
performance" to be done in sequence. These settings optimize some
|
|
|
|
of the 100Mbit autodetection circuitry. They say we only want to
|
|
|
|
do this for rev C of the chip, but engineers at NSC (Bradley
|
|
|
|
Kennedy) recommends always setting them. If you don't, you get
|
|
|
|
errors on some autonegotiations that make the device unusable.
|
|
|
|
|
|
|
|
It seems that the DSP needs a few usec to reinitialize after
|
|
|
|
the start of the phy. Just retry writing these values until they
|
|
|
|
stick.
|
|
|
|
*/
|
|
|
|
uint32_t srr = inl(nat->ioaddr + SiliconRev);
|
|
|
|
int NATSEMI_HW_TIMEOUT = 400;
|
|
|
|
for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
|
|
|
|
|
|
|
|
int dspcfg,dspcfg_1;
|
|
|
|
outw(1, nat->ioaddr + PGSEL);
|
|
|
|
outw(PMDCSR_VAL, nat->ioaddr + PMDCSR);
|
|
|
|
outw(TSTDAT_VAL, nat->ioaddr + TSTDAT);
|
|
|
|
dspcfg = (srr <= SRR_DP83815_C)?
|
|
|
|
DSPCFG_VAL : (DSPCFG_COEF | readw(nat->ioaddr + DSPCFG));
|
|
|
|
outw(dspcfg, nat->ioaddr + DSPCFG);
|
|
|
|
outw(SDCFG_VAL, nat->ioaddr + SDCFG);
|
|
|
|
outw(0, nat->ioaddr + PGSEL);
|
|
|
|
inl(nat->ioaddr + ChipConfig);
|
|
|
|
udelay(10);
|
|
|
|
|
|
|
|
outw(1, nat->ioaddr + PGSEL);
|
|
|
|
dspcfg_1 = readw(nat->ioaddr + DSPCFG);
|
|
|
|
outw(0, nat->ioaddr + PGSEL);
|
|
|
|
if (dspcfg == dspcfg_1)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i==NATSEMI_HW_TIMEOUT) {
|
|
|
|
DBG ( "Natsemi: DSPCFG mismatch after retrying for"
|
|
|
|
" %d usec.\n", i*10);
|
|
|
|
} else {
|
|
|
|
DBG ( "NATSEMI: DSPCFG accepted after %d usec.\n",
|
|
|
|
i*10);
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Enable PHY Specific event based interrupts. Link state change
|
|
|
|
* and Auto-Negotiation Completion are among the affected.
|
|
|
|
* Read the intr status to clear it (needed for wake events).
|
|
|
|
*/
|
|
|
|
inw(nat->ioaddr + MIntrStatus);
|
|
|
|
//MICRIntEn = 0x2
|
|
|
|
outw(0x2, nat->ioaddr + MIntrCtrl);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Patch up for fixing CRC errors.
|
|
|
|
* adapted from linux natsemi driver
|
|
|
|
*
|
|
|
|
*/
|
2007-07-10 19:29:30 +02:00
|
|
|
static void do_cable_magic ( struct net_device *netdev ) {
|
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
uint16_t data;
|
|
|
|
/*
|
|
|
|
* 100 MBit links with short cables can trip an issue with the chip.
|
|
|
|
* The problem manifests as lots of CRC errors and/or flickering
|
|
|
|
* activity LED while idle. This process is based on instructions
|
|
|
|
* from engineers at National.
|
|
|
|
*/
|
|
|
|
if (inl(nat->ioaddr + ChipConfig) & CfgSpeed100) {
|
|
|
|
|
|
|
|
outw(1, nat->ioaddr + PGSEL);
|
|
|
|
/*
|
|
|
|
* coefficient visibility should already be enabled via
|
|
|
|
* DSPCFG | 0x1000
|
|
|
|
*/
|
|
|
|
data = inw(nat->ioaddr + TSTDAT) & 0xff;
|
|
|
|
/*
|
|
|
|
* the value must be negative, and within certain values
|
|
|
|
* (these values all come from National)
|
|
|
|
*/
|
|
|
|
if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
|
|
|
|
|
|
|
|
/* the bug has been triggered - fix the coefficient */
|
|
|
|
outw(TSTDAT_FIXED, nat->ioaddr + TSTDAT);
|
|
|
|
/* lock the value */
|
|
|
|
data = inw(nat->ioaddr + DSPCFG);
|
|
|
|
//np->dspcfg = data | DSPCFG_LOCK;
|
|
|
|
outw(data | DSPCFG_LOCK , nat->ioaddr + DSPCFG);
|
|
|
|
}
|
|
|
|
outw(0, nat->ioaddr + PGSEL);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
/*
|
2007-06-19 00:30:33 +02:00
|
|
|
* Open NIC
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v netdev Net device
|
|
|
|
* @ret rc Return status code
|
2007-07-07 17:40:58 +02:00
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
static int nat_open ( struct net_device *netdev ) {
|
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
int i;
|
2007-06-21 01:46:22 +02:00
|
|
|
uint32_t tx_config,rx_config;
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/* Disable PME:
|
2007-07-07 22:07:30 +02:00
|
|
|
* The PME bit is initialized from the EEPROM contents.
|
|
|
|
* PCI cards probably have PME disabled, but motherboard
|
|
|
|
* implementations may have PME set to enable WakeOnLan.
|
|
|
|
* With PME set the chip will scan incoming packets but
|
|
|
|
* nothing will be written to memory.
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
SavedClkRun = inl ( nat->ioaddr + ClkRun );
|
|
|
|
outl ( SavedClkRun & ~0x100, nat->ioaddr + ClkRun );
|
2007-07-05 14:54:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Setting up Mac address in the NIC
|
|
|
|
*/
|
2007-07-07 22:07:30 +02:00
|
|
|
for ( i = 0 ; i < ETH_ALEN ; i+=2 ) {
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( i,nat->ioaddr + RxFilterAddr );
|
|
|
|
outw ( netdev->ll_addr[i] + ( netdev->ll_addr[i + 1] << 8 ),
|
|
|
|
nat->ioaddr + RxFilterData );
|
2007-06-26 23:20:34 +02:00
|
|
|
}
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/*Set up the Tx Ring
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->tx_cur = 0;
|
|
|
|
nat->tx_dirty = 0;
|
|
|
|
for ( i = 0 ; i < TX_RING_SIZE ; i++ ) {
|
|
|
|
nat->tx[i].link = virt_to_bus ( ( i + 1 < TX_RING_SIZE ) ? &nat->tx[i + 1] : &nat->tx[0] );
|
2007-06-21 01:07:04 +02:00
|
|
|
nat->tx[i].cmdsts = 0;
|
|
|
|
nat->tx[i].bufptr = 0;
|
|
|
|
}
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Set up RX ring
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->rx_cur = 0;
|
|
|
|
for ( i = 0 ; i < NUM_RX_DESC ; i++ ) {
|
2007-06-21 01:07:04 +02:00
|
|
|
nat->iobuf[i] = alloc_iob ( RX_BUF_SIZE );
|
2007-07-09 00:41:12 +02:00
|
|
|
if ( !nat->iobuf[i] )
|
2007-07-08 17:03:30 +02:00
|
|
|
goto memory_alloc_err;
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->rx[i].link = virt_to_bus ( ( i + 1 < NUM_RX_DESC ) ? &nat->rx[i + 1] : &nat->rx[0] );
|
2007-07-08 19:37:42 +02:00
|
|
|
nat->rx[i].cmdsts = RX_BUF_SIZE;
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->rx[i].bufptr = virt_to_bus ( nat->iobuf[i]->data );
|
2007-06-19 00:30:33 +02:00
|
|
|
}
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* load Receive Descriptor Register
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( virt_to_bus ( &nat->rx[0] ), nat->ioaddr + RxRingPtr );
|
|
|
|
DBG ( "Natsemi Rx descriptor loaded with: %X\n",
|
|
|
|
(unsigned int) inl ( nat->ioaddr + RxRingPtr ) );
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* setup Tx ring
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( virt_to_bus ( &nat->tx[0] ),nat->ioaddr + TxRingPtr );
|
|
|
|
DBG ( "Natsemi Tx descriptor loaded with: %X\n",
|
|
|
|
(unsigned int)inl ( nat->ioaddr + TxRingPtr ) );
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Enables RX
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( RxFilterEnable|AcceptBroadcast|AcceptAllMulticast|AcceptMyPhys,
|
|
|
|
nat->ioaddr + RxFilterAddr );
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
/* Initialize other registers.
|
|
|
|
* Configure the PCI bus bursts and FIFO thresholds.
|
|
|
|
* Configure for standard, in-spec Ethernet.
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
if ( inl ( nat->ioaddr + ChipConfig ) & 0x20000000 ) { /* Full duplex */
|
2007-07-10 19:29:30 +02:00
|
|
|
tx_config = 0xD0801002 | 0xC0000000;
|
|
|
|
DBG ( "Full duplex\n" );
|
|
|
|
rx_config = 0x10000020 | 0x10000000;
|
2007-06-19 00:30:33 +02:00
|
|
|
} else {
|
2007-07-10 19:29:30 +02:00
|
|
|
tx_config = 0x10801002 & ~0xC0000000;
|
|
|
|
DBG ( "Half duplex\n" );
|
|
|
|
rx_config = 0x0020 & ~0x10000000;
|
2007-06-19 00:30:33 +02:00
|
|
|
}
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( tx_config, nat->ioaddr + TxConfig );
|
|
|
|
outl ( rx_config, nat->ioaddr + RxConfig );
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/*start the receiver
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( RxOn, nat->ioaddr + ChipCmd );
|
2007-07-10 19:29:30 +02:00
|
|
|
|
|
|
|
/* lines 1586 linux-natsemi.c uses cable magic
|
|
|
|
* testing this feature is required or not
|
|
|
|
*/
|
|
|
|
do_cable_magic ( netdev );
|
2007-07-10 21:08:58 +02:00
|
|
|
init_phy_fixup ( netdev );
|
2007-07-10 19:29:30 +02:00
|
|
|
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-07-08 19:37:42 +02:00
|
|
|
/* mask the interrupts. note interrupt is not enabled here
|
2007-07-08 02:42:53 +02:00
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
return 0;
|
2007-07-08 17:03:30 +02:00
|
|
|
|
|
|
|
memory_alloc_err:
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 17:03:30 +02:00
|
|
|
/* this block frees the previously allocated buffers
|
|
|
|
* if memory for all the buffers is not available
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
i = 0;
|
|
|
|
while ( nat->rx[i].cmdsts == RX_BUF_SIZE ) {
|
|
|
|
free_iob ( nat->iobuf[i] );
|
2007-07-08 17:03:30 +02:00
|
|
|
i++;
|
|
|
|
}
|
|
|
|
return -ENOMEM;
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Close NIC
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v netdev Net device
|
2005-03-08 19:53:11 +01:00
|
|
|
*/
|
2007-06-21 01:07:04 +02:00
|
|
|
static void nat_close ( struct net_device *netdev ) {
|
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
2007-06-21 01:46:22 +02:00
|
|
|
int i;
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Reset the hardware to disable everything in one go
|
|
|
|
*/
|
2007-06-21 01:07:04 +02:00
|
|
|
nat_reset ( nat );
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Free RX ring
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
for ( i = 0; i < NUM_RX_DESC ; i++ ) {
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-09 00:41:12 +02:00
|
|
|
free_iob ( nat->iobuf[i] );
|
2007-06-21 01:07:04 +02:00
|
|
|
}
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Transmit packet
|
2005-03-08 19:53:11 +01:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v netdev Network device
|
|
|
|
* @v iobuf I/O buffer
|
|
|
|
* @ret rc Return status code
|
2005-03-08 19:53:11 +01:00
|
|
|
*/
|
2007-06-21 01:46:22 +02:00
|
|
|
static int nat_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
|
2007-06-19 00:30:33 +02:00
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* check for space in TX ring
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
if ( nat->tx[nat->tx_cur].cmdsts != 0 ) {
|
|
|
|
DBG ( "TX overflow\n" );
|
2007-06-19 00:30:33 +02:00
|
|
|
return -ENOBUFS;
|
|
|
|
}
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* to be used in netdev_tx_complete
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->tx_iobuf[nat->tx_cur] = iobuf;
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-08 17:03:30 +02:00
|
|
|
/* Pad and align packet has not been used because its not required here
|
2007-07-08 02:42:53 +02:00
|
|
|
* iob_pad ( iobuf, ETH_ZLEN ); can be used to achieve it
|
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Add to TX ring
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
DBG ( "TX id %d at %lx + %x\n", nat->tx_cur,
|
2007-07-01 01:30:41 +02:00
|
|
|
virt_to_bus ( &iobuf->data ), iob_len ( iobuf ) );
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->tx[nat->tx_cur].bufptr = virt_to_bus ( iobuf->data );
|
|
|
|
nat->tx[nat->tx_cur].cmdsts = iob_len ( iobuf ) | OWN;
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* increment the circular buffer pointer to the next buffer location
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->tx_cur = ( nat->tx_cur + 1 ) % TX_RING_SIZE;
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/*start the transmitter
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( TxOn, nat->ioaddr + ChipCmd );
|
2007-06-19 00:30:33 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Poll for received packets
|
|
|
|
*
|
|
|
|
* @v netdev Network device
|
|
|
|
* @v rx_quota Maximum number of packets to receive
|
|
|
|
*/
|
2007-07-08 21:12:38 +02:00
|
|
|
static void nat_poll ( struct net_device *netdev) {
|
2007-06-21 01:07:04 +02:00
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
2007-07-01 01:30:41 +02:00
|
|
|
unsigned int status;
|
2007-06-19 00:30:33 +02:00
|
|
|
unsigned int rx_status;
|
2007-07-04 04:20:47 +02:00
|
|
|
unsigned int intr_status;
|
2007-06-19 00:30:33 +02:00
|
|
|
unsigned int rx_len;
|
|
|
|
struct io_buffer *rx_iob;
|
|
|
|
int i;
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* read the interrupt register
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
intr_status = inl ( nat->ioaddr + IntrStatus );
|
|
|
|
if ( !intr_status )
|
|
|
|
goto end;
|
2007-07-04 04:20:47 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* check the status of packets given to card for transmission
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
DBG ( "Intr status %X\n",intr_status );
|
2007-07-04 04:20:47 +02:00
|
|
|
|
2007-07-09 00:41:12 +02:00
|
|
|
i = nat->tx_dirty;
|
|
|
|
while ( i!= nat->tx_cur ) {
|
|
|
|
status = nat->tx[nat->tx_dirty].cmdsts;
|
|
|
|
DBG ( "value of tx_dirty = %d tx_cur=%d status=%X\n",
|
|
|
|
nat->tx_dirty,nat->tx_cur,status );
|
2007-07-01 01:30:41 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* check if current packet has been transmitted or not
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
if ( status & OWN )
|
2007-06-21 01:07:04 +02:00
|
|
|
break;
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Check if any errors in transmission
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
if (! ( status & DescPktOK ) ) {
|
|
|
|
DBG ( "Error in sending Packet status:%X\n",
|
|
|
|
(unsigned int) status );
|
|
|
|
netdev_tx_complete_err ( netdev,nat->tx_iobuf[nat->tx_dirty],-EINVAL );
|
2007-07-07 22:07:30 +02:00
|
|
|
} else {
|
2007-07-09 00:41:12 +02:00
|
|
|
DBG ( "Success in transmitting Packet\n" );
|
|
|
|
netdev_tx_complete ( netdev,nat->tx_iobuf[nat->tx_dirty] );
|
2007-06-19 00:30:33 +02:00
|
|
|
}
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* setting cmdsts zero, indicating that it can be reused
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->tx[nat->tx_dirty].cmdsts = 0;
|
|
|
|
nat->tx_dirty = ( nat->tx_dirty + 1 ) % TX_RING_SIZE;
|
|
|
|
i = ( i + 1 ) % TX_RING_SIZE;
|
2007-06-19 00:30:33 +02:00
|
|
|
}
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Handle received packets
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
rx_status = (unsigned int) nat->rx[nat->rx_cur].cmdsts;
|
|
|
|
while ( ( rx_status & OWN ) ) {
|
|
|
|
rx_len = ( rx_status & DSIZE ) - CRC_SIZE;
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/*check for the corrupt packet
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
if ( ( rx_status & ( DescMore|DescPktOK|RxTooLong ) ) != DescPktOK) {
|
|
|
|
DBG ( "natsemi_poll: Corrupted packet received, "
|
2007-06-26 03:24:34 +02:00
|
|
|
"buffer status = %X ^ %X \n",rx_status,
|
2007-07-09 00:41:12 +02:00
|
|
|
(unsigned int) nat->rx[nat->rx_cur].cmdsts );
|
|
|
|
netdev_rx_err ( netdev,NULL,-EINVAL );
|
2007-07-07 22:07:30 +02:00
|
|
|
} else {
|
2007-07-09 00:41:12 +02:00
|
|
|
rx_iob = alloc_iob ( rx_len );
|
|
|
|
|
|
|
|
if ( !rx_iob )
|
2007-07-08 02:42:53 +02:00
|
|
|
/* leave packet for next call to poll
|
|
|
|
*/
|
2007-07-04 04:20:47 +02:00
|
|
|
goto end;
|
2007-07-09 00:41:12 +02:00
|
|
|
memcpy ( iob_put ( rx_iob,rx_len ),
|
|
|
|
nat->iobuf[nat->rx_cur]->data,rx_len );
|
|
|
|
DBG ( "received packet\n" );
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* add to the receive queue.
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
netdev_rx ( netdev,rx_iob );
|
2007-06-19 00:30:33 +02:00
|
|
|
}
|
2007-06-21 01:07:04 +02:00
|
|
|
nat->rx[nat->rx_cur].cmdsts = RX_BUF_SIZE;
|
2007-07-09 00:41:12 +02:00
|
|
|
nat->rx_cur = ( nat->rx_cur + 1 ) % NUM_RX_DESC;
|
|
|
|
rx_status = nat->rx[nat->rx_cur].cmdsts;
|
2007-06-19 00:30:33 +02:00
|
|
|
}
|
2007-07-04 04:20:47 +02:00
|
|
|
end:
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* re-enable the potentially idle receive state machine
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( RxOn, nat->ioaddr + ChipCmd );
|
2007-06-21 01:07:04 +02:00
|
|
|
}
|
|
|
|
|
2007-07-08 19:37:42 +02:00
|
|
|
/**
|
|
|
|
* Enable/disable interrupts
|
|
|
|
*
|
|
|
|
* @v netdev Network device
|
|
|
|
* @v enable Interrupts should be enabled
|
|
|
|
*/
|
|
|
|
static void nat_irq ( struct net_device *netdev, int enable ) {
|
2007-07-09 00:41:12 +02:00
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
2007-07-08 19:37:42 +02:00
|
|
|
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( ( enable ? ( RxOk|RxErr|TxOk|TxErr ) :0 ),
|
2007-07-08 19:37:42 +02:00
|
|
|
nat->ioaddr + IntrMask);
|
2007-07-09 00:41:12 +02:00
|
|
|
outl ( ( enable ? 1:0 ),nat->ioaddr + IntrEnable );
|
2007-07-08 19:37:42 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/** natsemi net device operations */
|
2007-07-07 22:07:30 +02:00
|
|
|
static struct net_device_operations nat_operations = {
|
|
|
|
.open = nat_open,
|
|
|
|
.close = nat_close,
|
|
|
|
.transmit = nat_transmit,
|
|
|
|
.poll = nat_poll,
|
2007-07-08 19:37:42 +02:00
|
|
|
.irq = nat_irq,
|
2007-07-07 22:07:30 +02:00
|
|
|
};
|
2007-06-21 01:07:04 +02:00
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
/*
|
2007-06-19 00:30:33 +02:00
|
|
|
* Probe PCI device
|
|
|
|
*
|
|
|
|
* @v pci PCI device
|
|
|
|
* @v id PCI ID
|
|
|
|
* @ret rc Return status code
|
|
|
|
*/
|
|
|
|
static int nat_probe ( struct pci_device *pci,
|
|
|
|
const struct pci_device_id *id __unused ) {
|
|
|
|
struct net_device *netdev;
|
|
|
|
struct natsemi_nic *nat = NULL;
|
|
|
|
int rc;
|
2007-07-07 22:07:30 +02:00
|
|
|
int i;
|
|
|
|
uint8_t ll_addr_encoded[MAX_LL_ADDR_LEN];
|
2007-07-09 00:41:12 +02:00
|
|
|
uint8_t last = 0;
|
|
|
|
uint8_t last1 = 0;
|
2007-07-08 21:12:38 +02:00
|
|
|
uint8_t prev_bytes[2];
|
2007-06-19 00:30:33 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Allocate net device
|
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
netdev = alloc_etherdev ( sizeof ( *nat ) );
|
2007-07-07 22:07:30 +02:00
|
|
|
if ( ! netdev )
|
|
|
|
return -ENOMEM;
|
2007-07-09 00:41:12 +02:00
|
|
|
netdev_init ( netdev,&nat_operations );
|
2007-06-19 00:30:33 +02:00
|
|
|
nat = netdev->priv;
|
|
|
|
pci_set_drvdata ( pci, netdev );
|
|
|
|
netdev->dev = &pci->dev;
|
|
|
|
memset ( nat, 0, sizeof ( *nat ) );
|
|
|
|
nat->ioaddr = pci->ioaddr;
|
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Fix up PCI device
|
|
|
|
*/
|
2007-07-07 22:07:30 +02:00
|
|
|
adjust_pci_device ( pci );
|
2007-07-05 14:38:37 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Reset the NIC, set up EEPROM access and read MAC address
|
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
nat_reset ( nat );
|
2007-06-26 23:20:34 +02:00
|
|
|
nat_init_eeprom ( nat );
|
2007-07-09 00:41:12 +02:00
|
|
|
nvs_read ( &nat->eeprom.nvs, EE_MAC-1, prev_bytes, 1 );
|
2007-07-07 22:07:30 +02:00
|
|
|
nvs_read ( &nat->eeprom.nvs, EE_MAC, ll_addr_encoded, ETH_ALEN );
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
/* decoding the MAC address read from NVS
|
|
|
|
* and save it in netdev->ll_addr
|
|
|
|
*/
|
2007-07-09 00:41:12 +02:00
|
|
|
last = prev_bytes[1] >> 7;
|
|
|
|
for ( i = 0 ; i < ETH_ALEN ; i++ ) {
|
|
|
|
last1 = ll_addr_encoded[i] >> 7;
|
|
|
|
netdev->ll_addr[i] = ll_addr_encoded[i] << 1 | last;
|
|
|
|
last = last1;
|
2007-07-07 22:07:30 +02:00
|
|
|
}
|
2007-07-08 02:42:53 +02:00
|
|
|
|
|
|
|
/* Register network device
|
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
if ( ( rc = register_netdev ( netdev ) ) != 0 )
|
2007-07-07 22:07:30 +02:00
|
|
|
goto err_register_netdev;
|
2007-06-19 00:30:33 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2007-07-07 22:07:30 +02:00
|
|
|
err_register_netdev:
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Disable NIC
|
|
|
|
*/
|
2007-07-07 22:07:30 +02:00
|
|
|
nat_reset ( nat );
|
2007-07-09 00:41:12 +02:00
|
|
|
|
2007-07-08 02:42:53 +02:00
|
|
|
/* Free net device
|
|
|
|
*/
|
2007-07-01 04:23:19 +02:00
|
|
|
netdev_put ( netdev );
|
2007-06-19 00:30:33 +02:00
|
|
|
return rc;
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Remove PCI device
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v pci PCI device
|
2005-03-08 19:53:11 +01:00
|
|
|
*/
|
2007-06-21 01:07:04 +02:00
|
|
|
static void nat_remove ( struct pci_device *pci ) {
|
2007-06-19 00:30:33 +02:00
|
|
|
struct net_device *netdev = pci_get_drvdata ( pci );
|
2007-06-21 01:07:04 +02:00
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
2007-07-03 04:45:50 +02:00
|
|
|
|
|
|
|
if ( nat->nvo.nvs )
|
|
|
|
nvo_unregister ( &nat->nvo );
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
unregister_netdev ( netdev );
|
2007-06-21 01:07:04 +02:00
|
|
|
nat_reset ( nat );
|
2007-07-01 04:23:19 +02:00
|
|
|
netdev_put ( netdev );
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-21 01:07:04 +02:00
|
|
|
static struct pci_device_id natsemi_nics[] = {
|
|
|
|
PCI_ROM(0x100b, 0x0020, "dp83815", "DP83815"),
|
2005-04-13 03:01:33 +02:00
|
|
|
};
|
|
|
|
|
2007-06-21 01:07:04 +02:00
|
|
|
struct pci_driver natsemi_driver __pci_driver = {
|
|
|
|
.ids = natsemi_nics,
|
|
|
|
.id_count = ( sizeof ( natsemi_nics ) / sizeof ( natsemi_nics[0] ) ),
|
|
|
|
.probe = nat_probe,
|
|
|
|
.remove = nat_remove,
|
2005-03-08 19:53:11 +01:00
|
|
|
};
|