2007-06-19 00:30:33 +02:00
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/* natsemi.c - gPXE driver for the NatSemi DP8381x series.
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2005-03-08 19:53:11 +01:00
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*/
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2007-06-19 00:30:33 +02:00
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <io.h>
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#include <errno.h>
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#include <timer.h>
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#include <byteswap.h>
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2007-07-05 14:54:12 +02:00
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#include <gpxe/pci.h>
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2007-06-19 00:30:33 +02:00
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#include <gpxe/if_ether.h>
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2007-07-05 14:54:12 +02:00
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#include <gpxe/ethernet.h>
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2007-06-19 00:30:33 +02:00
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#include <gpxe/iobuf.h>
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#include <gpxe/netdevice.h>
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#include <gpxe/spi_bit.h>
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#include <gpxe/threewire.h>
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#include <gpxe/nvo.h>
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#define TX_RING_SIZE 4
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#define NUM_RX_DESC 4
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struct natsemi_tx {
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uint32_t link;
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uint32_t cmdsts;
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uint32_t bufptr;
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};
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2007-07-07 17:40:58 +02:00
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2007-06-19 00:30:33 +02:00
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struct natsemi_rx {
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uint32_t link;
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uint32_t cmdsts;
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uint32_t bufptr;
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};
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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struct natsemi_nic {
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unsigned short ioaddr;
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unsigned short tx_next;
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struct natsemi_tx tx[TX_RING_SIZE];
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struct natsemi_rx rx[NUM_RX_DESC];
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struct spi_bit_basher spibit;
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struct spi_device eeprom;
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struct nvo_block nvo;
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2005-03-08 19:53:11 +01:00
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};
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2007-06-19 00:30:33 +02:00
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/* Tuning Parameters */
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#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
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#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
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#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
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#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
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#define TX_IPG 3 /* This is the only valid value */
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//#define RX_BUF_LEN_IDX 0 /* */
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#define RX_BUF_LEN 8192 /*buffer size should be multiple of 32 */
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#define RX_BUF_PAD 4
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#define RX_BUF_SIZE 1536
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/* NATSEMI: Offsets to the device registers.
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2005-03-08 19:53:11 +01:00
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Unlike software-only systems, device drivers interact with complex hardware.
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It's not useful to define symbolic names for every register bit in the
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device.
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*/
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enum register_offsets {
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ChipCmd = 0x00,
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ChipConfig = 0x04,
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EECtrl = 0x08,
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PCIBusCfg = 0x0C,
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IntrStatus = 0x10,
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IntrMask = 0x14,
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IntrEnable = 0x18,
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TxRingPtr = 0x20,
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TxConfig = 0x24,
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RxRingPtr = 0x30,
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RxConfig = 0x34,
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ClkRun = 0x3C,
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WOLCmd = 0x40,
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PauseCmd = 0x44,
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RxFilterAddr = 0x48,
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RxFilterData = 0x4C,
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BootRomAddr = 0x50,
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BootRomData = 0x54,
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SiliconRev = 0x58,
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StatsCtrl = 0x5C,
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StatsData = 0x60,
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RxPktErrs = 0x60,
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RxMissed = 0x68,
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RxCRCErrs = 0x64,
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PCIPM = 0x44,
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PhyStatus = 0xC0,
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MIntrCtrl = 0xC4,
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MIntrStatus = 0xC8,
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/* These are from the spec, around page 78... on a separate table. */
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PGSEL = 0xCC,
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PMDCSR = 0xE4,
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TSTDAT = 0xFC,
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DSPCFG = 0xF4,
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2007-06-19 00:30:33 +02:00
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SDCFG = 0x8C,
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BasicControl = 0x80,
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BasicStatus = 0x84
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2005-03-08 19:53:11 +01:00
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};
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2007-06-19 00:30:33 +02:00
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2005-03-08 19:53:11 +01:00
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/* Bit in ChipCmd. */
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enum ChipCmdBits {
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ChipReset = 0x100,
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RxReset = 0x20,
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TxReset = 0x10,
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RxOff = 0x08,
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RxOn = 0x04,
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TxOff = 0x02,
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TxOn = 0x01
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2007-06-19 00:30:33 +02:00
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}
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2005-03-08 19:53:11 +01:00
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/* Bits in the RxMode register. */
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0xC0000000,
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AcceptMulticast = 0x00200000,
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AcceptAllMulticast = 0x20000000,
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AcceptAllPhys = 0x10000000,
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AcceptMyPhys = 0x08000000,
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RxFilterEnable = 0x80000000
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};
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/* Bits in network_desc.status */
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enum desc_status_bits {
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DescOwn = 0x80000000,
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DescMore = 0x40000000,
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DescIntr = 0x20000000,
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DescNoCRC = 0x10000000,
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DescPktOK = 0x08000000,
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RxTooLong = 0x00400000
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};
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2007-06-19 00:30:33 +02:00
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/* EEPROM access */
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#define EE_M1 0x80 /* Mode select bit 1 */
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#define EE_M0 0x40 /* Mode select bit 0 */
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#define EE_CS 0x08 /* EEPROM chip select */
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#define EE_SK 0x04 /* EEPROM shift clock */
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#define EE_DI 0x02 /* Data in */
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#define EE_DO 0x01 /* Data out */
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/* Offsets within EEPROM (these are word offsets) */
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#define EE_MAC 7
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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static uint32_t SavedClkRun;
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2005-03-08 19:53:11 +01:00
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2005-04-13 01:24:39 +02:00
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2007-06-19 00:30:33 +02:00
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static const uint8_t rtl_ee_bits[] = {
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[SPI_BIT_SCLK] = EE_SK,
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[SPI_BIT_MOSI] = EE_DI,
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[SPI_BIT_MISO] = EE_DO,
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[SPI_BIT_SS(0)] = ( EE_CS | EE_M1 ),
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2007-07-07 17:40:58 +02:00
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};
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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static int rtl_spi_read_bit ( struct bit_basher *basher,
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unsigned int bit_id ) {
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struct rtl8139_nic *rtl = container_of ( basher, struct rtl8139_nic,
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spibit.basher );
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uint8_t mask = rtl_ee_bits[bit_id];
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uint8_t eereg;
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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eereg = inb ( rtl->ioaddr + Cfg9346 );
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return ( eereg & mask );
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2007-07-07 17:40:58 +02:00
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}
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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static void rtl_spi_write_bit ( struct bit_basher *basher,
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unsigned int bit_id, unsigned long data ) {
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struct rtl8139_nic *rtl = container_of ( basher, struct rtl8139_nic,
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spibit.basher );
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uint8_t mask = rtl_ee_bits[bit_id];
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uint8_t eereg;
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eereg = inb ( rtl->ioaddr + Cfg9346 );
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eereg &= ~mask;
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eereg |= ( data & mask );
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outb ( eereg, rtl->ioaddr + Cfg9346 );
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2007-07-07 17:40:58 +02:00
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}
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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static struct bit_basher_operations rtl_basher_ops = {
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.read = rtl_spi_read_bit,
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.write = rtl_spi_write_bit,
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};
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/** Portion of EEPROM available for non-volatile stored options
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2007-07-07 17:40:58 +02:00
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*
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2007-06-19 00:30:33 +02:00
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* We use offset 0x40 (i.e. address 0x20), length 0x40. This block is
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* marked as VPD in the rtl8139 datasheets, so we use it only if we
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* detect that the card is not supporting VPD.
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2007-07-07 17:40:58 +02:00
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*/
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2007-06-19 00:30:33 +02:00
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static struct nvo_fragment rtl_nvo_fragments[] = {
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{ 0x20, 0x40 },
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{ 0, 0 }
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};
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/**
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* Set up for EEPROM access
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2007-07-07 17:40:58 +02:00
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*
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2007-06-19 00:30:33 +02:00
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* @v NAT NATSEMI NIC
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2007-07-07 17:40:58 +02:00
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*/
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2007-06-19 00:30:33 +02:00
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void nat_init_eeprom ( struct natsemi_nic *nat ) {
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int ee9356;
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int vpd;
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/* Initialise three-wire bus */
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nat->spibit.basher.op = &rtl_basher_ops;
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rtl->spibit.bus.mode = SPI_MODE_THREEWIRE;
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init_spi_bit_basher ( &rtl->spibit );
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/* Detect EEPROM type and initialise three-wire device */
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ee9356 = ( inw ( rtl->ioaddr + RxConfig ) & Eeprom9356 );
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if ( ee9356 ) {
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DBG ( "EEPROM is an AT93C56\n" );
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init_at93c56 ( &rtl->eeprom, 16 );
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} else {
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DBG ( "EEPROM is an AT93C46\n" );
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init_at93c46 ( &rtl->eeprom, 16 );
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}
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rtl->eeprom.bus = &rtl->spibit.bus;
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/* Initialise space for non-volatile options, if available */
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vpd = ( inw ( rtl->ioaddr + Config1 ) & VPDEnable );
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if ( vpd ) {
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DBG ( "EEPROM in use for VPD; cannot use for options\n" );
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} else {
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rtl->nvo.nvs = &rtl->eeprom.nvs;
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rtl->nvo.fragments = rtl_nvo_fragments;
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}
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2007-07-07 17:40:58 +02:00
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}
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/**
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* Reset NIC
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2007-07-07 17:40:58 +02:00
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*
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2007-06-19 00:30:33 +02:00
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* @v rtl NATSEMI NIC
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2007-07-07 17:40:58 +02:00
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*
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2007-06-19 00:30:33 +02:00
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* Issues a hardware reset and waits for the reset to complete.
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2007-07-07 17:40:58 +02:00
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*/
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2007-06-19 00:30:33 +02:00
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static void nat_reset ( struct nat_nic *nat ) {
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/* Reset chip */
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outb ( ChipReset, nat->ioaddr + ChipCmd );
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mdelay ( 10 );
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memset ( &nat->tx, 0, sizeof ( nat->tx ) );
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nat->rx.offset = 0;
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/* Restore PME enable bit */
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outl(SavedClkRun, nat->ioaddr + ClkRun);
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2007-07-07 17:40:58 +02:00
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}
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/**
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* Open NIC
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2007-07-07 17:40:58 +02:00
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*
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2007-06-19 00:30:33 +02:00
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* @v netdev Net device
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* @ret rc Return status code
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2007-07-07 17:40:58 +02:00
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*/
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2007-06-19 00:30:33 +02:00
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static int nat_open ( struct net_device *netdev ) {
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struct natsemi_nic *nat = netdev->priv;
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struct io_buffer *iobuf;
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int i;
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2007-07-07 17:40:58 +02:00
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2007-06-19 00:30:33 +02:00
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/* Disable PME:
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* The PME bit is initialized from the EEPROM contents.
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* PCI cards probably have PME disabled, but motherboard
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* implementations may have PME set to enable WakeOnLan.
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* With PME set the chip will scan incoming packets but
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* nothing will be written to memory. */
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SavedClkRun = inl(nat->ioaddr + ClkRun);
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outl(SavedClkRun & ~0x100, nat->ioaddr + ClkRun);
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2007-07-05 14:54:12 +02:00
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2007-06-19 00:30:33 +02:00
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2005-03-08 19:53:11 +01:00
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2007-06-19 00:30:33 +02:00
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/* Program the MAC address TODO enable this comment */
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/*
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for ( i = 0 ; i < ETH_ALEN ; i++ )
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outb ( netdev->ll_addr[i], rtl->ioaddr + MAC0 + i );
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*/
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/* Set up RX ring */
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2007-07-07 17:40:58 +02:00
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2007-06-19 00:30:33 +02:00
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for (i=0;i<NUM_RX_DESC;i++)
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{
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2007-07-07 17:40:58 +02:00
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2007-06-19 00:30:33 +02:00
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iobuf = alloc_iob ( RX_BUF_SIZE );
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if (!iobuf)
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return -ENOMEM;
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nat->rx[i].link = virt_to_bus((i+1 < NUM_RX_DESC) ? &nat->rx[i+1] : &nat->rx[0]);
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nat->rx[i].cmdsts = (u32) RX_BUF_SIZE;
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nat->rx[i].bufptr = virt_to_bus(iobuf->data);
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}
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2007-07-07 17:40:58 +02:00
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2007-06-19 00:30:33 +02:00
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/* load Receive Descriptor Register */
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outl(virt_to_bus(&nat->rx[0]), ioaddr + RxRingPtr);
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DBG("Natsemi Rx descriptor loaded with: %X\n",inl(nat->ioaddr+RingPtr));
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2007-07-07 17:40:58 +02:00
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2007-06-19 00:30:33 +02:00
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/* setup Tx ring */
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outl(virt_to_bus(&nat->tx[0]),nat->ioaddr+TxRingPtr);
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DBG("Natsemi Tx descriptor loaded with: %X\n",inl(nat->ioaddr+TxRingPtr));
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2007-07-07 17:40:58 +02:00
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|
|
2007-06-19 00:30:33 +02:00
|
|
|
/* Enables RX */
|
|
|
|
outl(RxFilterEnable|AcceptBroadcast|AcceptAllMulticast|AcceptMyPhys, nat->ioaddr+RxFilterAddr);
|
2007-07-07 17:40:58 +02:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/* Initialize other registers. */
|
|
|
|
/* Configure the PCI bus bursts and FIFO thresholds. */
|
|
|
|
/* Configure for standard, in-spec Ethernet. */
|
|
|
|
if (inl(nat->ioaddr + ChipConfig) & 0x20000000) { /* Full duplex */
|
|
|
|
tx_config = 0xD0801002;
|
|
|
|
rx_config = 0x10000020;
|
|
|
|
} else {
|
|
|
|
tx_config = 0x10801002;
|
|
|
|
rx_config = 0x0020;
|
|
|
|
}
|
|
|
|
outl(tx_config, nat->ioaddr + TxConfig);
|
|
|
|
outl(rx_config, nat->ioaddr + RxConfig);
|
2007-07-07 17:40:58 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/*start the receiver and transmitter */
|
|
|
|
outl(RxOn|TxOn, nat->ioaddr + ChipCmd);
|
2007-07-07 17:40:58 +02:00
|
|
|
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
return 0;
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Close NIC
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v netdev Net device
|
2005-03-08 19:53:11 +01:00
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
static void rtl_close ( struct net_device *netdev ) {
|
|
|
|
struct rtl8139_nic *rtl = netdev->priv;
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/* Reset the hardware to disable everything in one go */
|
|
|
|
rtl_reset ( rtl );
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/* Free RX ring */
|
|
|
|
free ( rtl->rx.ring );
|
|
|
|
rtl->rx.ring = NULL;
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Transmit packet
|
2005-03-08 19:53:11 +01:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v netdev Network device
|
|
|
|
* @v iobuf I/O buffer
|
|
|
|
* @ret rc Return status code
|
2005-03-08 19:53:11 +01:00
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
static int natsemi_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
|
|
|
|
struct natsemi_nic *nat = netdev->priv;
|
|
|
|
|
|
|
|
/* Check for space in TX ring */
|
|
|
|
if ( nat->tx.iobuf[nat->tx.next] != NULL ) {
|
|
|
|
printf ( "TX overflow\n" );
|
|
|
|
return -ENOBUFS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Pad and align packet */
|
|
|
|
iob_pad ( iobuf, ETH_ZLEN );
|
|
|
|
|
|
|
|
/* Add to TX ring */
|
|
|
|
DBG ( "TX id %d at %lx+%x\n", rtl->tx.next,
|
|
|
|
virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
|
|
|
|
rtl->tx.iobuf[rtl->tx.next] = iobuf;
|
|
|
|
outl ( virt_to_bus ( iobuf->data ),
|
|
|
|
rtl->ioaddr + TxAddr0 + 4 * rtl->tx.next );
|
|
|
|
outl ( ( ( ( TX_FIFO_THRESH & 0x7e0 ) << 11 ) | iob_len ( iobuf ) ),
|
|
|
|
rtl->ioaddr + TxStatus0 + 4 * rtl->tx.next );
|
|
|
|
rtl->tx.next = ( rtl->tx.next + 1 ) % TX_RING_SIZE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Poll for received packets
|
|
|
|
*
|
|
|
|
* @v netdev Network device
|
|
|
|
* @v rx_quota Maximum number of packets to receive
|
|
|
|
*/
|
|
|
|
static void rtl_poll ( struct net_device *netdev, unsigned int rx_quota ) {
|
|
|
|
struct rtl8139_nic *rtl = netdev->priv;
|
|
|
|
unsigned int status;
|
|
|
|
unsigned int tsad;
|
|
|
|
unsigned int rx_status;
|
|
|
|
unsigned int rx_len;
|
|
|
|
struct io_buffer *rx_iob;
|
|
|
|
int wrapped_len;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Acknowledge interrupts */
|
|
|
|
status = inw ( rtl->ioaddr + IntrStatus );
|
|
|
|
if ( ! status )
|
|
|
|
return;
|
|
|
|
outw ( status, rtl->ioaddr + IntrStatus );
|
|
|
|
|
|
|
|
/* Handle TX completions */
|
|
|
|
tsad = inw ( rtl->ioaddr + TxSummary );
|
|
|
|
for ( i = 0 ; i < TX_RING_SIZE ; i++ ) {
|
|
|
|
if ( ( rtl->tx.iobuf[i] != NULL ) && ( tsad & ( 1 << i ) ) ) {
|
|
|
|
DBG ( "TX id %d complete\n", i );
|
|
|
|
netdev_tx_complete ( netdev, rtl->tx.iobuf[i] );
|
|
|
|
rtl->tx.iobuf[i] = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle received packets */
|
|
|
|
while ( rx_quota && ! ( inw ( rtl->ioaddr + ChipCmd ) & RxBufEmpty ) ){
|
|
|
|
rx_status = * ( ( uint16_t * )
|
|
|
|
( rtl->rx.ring + rtl->rx.offset ) );
|
|
|
|
rx_len = * ( ( uint16_t * )
|
|
|
|
( rtl->rx.ring + rtl->rx.offset + 2 ) );
|
|
|
|
if ( rx_status & RxOK ) {
|
|
|
|
DBG ( "RX packet at offset %x+%x\n", rtl->rx.offset,
|
|
|
|
rx_len );
|
|
|
|
|
|
|
|
rx_iob = alloc_iob ( rx_len );
|
|
|
|
if ( ! rx_iob ) {
|
|
|
|
/* Leave packet for next call to poll() */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
wrapped_len = ( ( rtl->rx.offset + 4 + rx_len )
|
|
|
|
- RX_BUF_LEN );
|
|
|
|
if ( wrapped_len < 0 )
|
|
|
|
wrapped_len = 0;
|
|
|
|
|
|
|
|
memcpy ( iob_put ( rx_iob, rx_len - wrapped_len ),
|
|
|
|
rtl->rx.ring + rtl->rx.offset + 4,
|
|
|
|
rx_len - wrapped_len );
|
|
|
|
memcpy ( iob_put ( rx_iob, wrapped_len ),
|
|
|
|
rtl->rx.ring, wrapped_len );
|
|
|
|
|
|
|
|
netdev_rx ( netdev, rx_iob );
|
|
|
|
rx_quota--;
|
|
|
|
} else {
|
|
|
|
DBG ( "RX bad packet (status %#04x len %d)\n",
|
|
|
|
rx_status, rx_len );
|
|
|
|
}
|
|
|
|
rtl->rx.offset = ( ( ( rtl->rx.offset + 4 + rx_len + 3 ) & ~3 )
|
|
|
|
% RX_BUF_LEN );
|
|
|
|
outw ( rtl->rx.offset - 16, rtl->ioaddr + RxBufPtr );
|
|
|
|
}
|
|
|
|
}
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
#if 0
|
|
|
|
static void rtl_irq(struct nic *nic, irq_action_t action)
|
|
|
|
{
|
|
|
|
unsigned int mask;
|
|
|
|
/* Bit of a guess as to which interrupts we should allow */
|
|
|
|
unsigned int interested = ROK | RER | RXOVW | FOVW | SERR;
|
|
|
|
|
|
|
|
switch ( action ) {
|
|
|
|
case DISABLE :
|
|
|
|
case ENABLE :
|
|
|
|
mask = inw(rtl->ioaddr + IntrMask);
|
|
|
|
mask = mask & ~interested;
|
|
|
|
if ( action == ENABLE ) mask = mask | interested;
|
|
|
|
outw(mask, rtl->ioaddr + IntrMask);
|
|
|
|
break;
|
|
|
|
case FORCE :
|
|
|
|
/* Apparently writing a 1 to this read-only bit of a
|
|
|
|
* read-only and otherwise unrelated register will
|
|
|
|
* force an interrupt. If you ever want to see how
|
|
|
|
* not to write a datasheet, read the one for the
|
|
|
|
* RTL8139...
|
|
|
|
*/
|
|
|
|
outb(EROK, rtl->ioaddr + RxEarlyStatus);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Probe PCI device
|
|
|
|
*
|
|
|
|
* @v pci PCI device
|
|
|
|
* @v id PCI ID
|
|
|
|
* @ret rc Return status code
|
|
|
|
*/
|
|
|
|
static int nat_probe ( struct pci_device *pci,
|
|
|
|
const struct pci_device_id *id __unused ) {
|
|
|
|
struct net_device *netdev;
|
|
|
|
struct natsemi_nic *nat = NULL;
|
|
|
|
int registered_netdev = 0;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* Fix up PCI device */
|
|
|
|
adjust_pci_device ( pci );
|
|
|
|
|
|
|
|
/* Allocate net device */
|
|
|
|
netdev = alloc_etherdev ( sizeof ( *nat ) );
|
|
|
|
if ( ! netdev ) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
nat = netdev->priv;
|
|
|
|
pci_set_drvdata ( pci, netdev );
|
|
|
|
netdev->dev = &pci->dev;
|
|
|
|
memset ( nat, 0, sizeof ( *nat ) );
|
|
|
|
nat->ioaddr = pci->ioaddr;
|
|
|
|
|
|
|
|
/* Reset the NIC, set up EEPROM access and read MAC address */
|
|
|
|
nat_reset ( nat );
|
|
|
|
/* commenitng two line below. Have to be included in final natsemi.c TODO*/
|
|
|
|
/*
|
|
|
|
nat_init_eeprom ( rtl );
|
|
|
|
nvs_read ( &nat->eeprom.nvs, EE_MAC, netdev->ll_addr, ETH_ALEN );
|
|
|
|
|
|
|
|
*/
|
2005-03-08 19:53:11 +01:00
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/* Point to NIC specific routines */
|
|
|
|
netdev->open = nat_open;
|
|
|
|
netdev->close = nat_close;
|
|
|
|
netdev->transmit = nat_transmit;
|
|
|
|
netdev->poll = nat_poll;
|
|
|
|
|
|
|
|
/* Register network device */
|
|
|
|
if ( ( rc = register_netdev ( netdev ) ) != 0 )
|
|
|
|
goto err;
|
|
|
|
registered_netdev = 1;
|
|
|
|
|
|
|
|
/* Register non-volatile storagei
|
|
|
|
* uncomment lines below in final version*/
|
|
|
|
/*
|
|
|
|
if ( rtl->nvo.nvs ) {
|
|
|
|
if ( ( rc = nvo_register ( &rtl->nvo ) ) != 0 )
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
*/
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
|
|
|
/* Disable NIC */
|
|
|
|
if ( nat )
|
|
|
|
nat_reset ( rtl );
|
|
|
|
if ( registered_netdev )
|
|
|
|
unregister_netdev ( netdev );
|
|
|
|
/* Free net device */
|
|
|
|
free_netdev ( netdev );
|
|
|
|
return rc;
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
/**
|
|
|
|
* Remove PCI device
|
2007-07-07 17:40:58 +02:00
|
|
|
*
|
2007-06-19 00:30:33 +02:00
|
|
|
* @v pci PCI device
|
2005-03-08 19:53:11 +01:00
|
|
|
*/
|
2007-06-19 00:30:33 +02:00
|
|
|
static void rtl_remove ( struct pci_device *pci ) {
|
|
|
|
struct net_device *netdev = pci_get_drvdata ( pci );
|
|
|
|
struct rtl8139_nic *rtl = netdev->priv;
|
|
|
|
|
|
|
|
if ( rtl->nvo.nvs )
|
|
|
|
nvo_unregister ( &rtl->nvo );
|
|
|
|
unregister_netdev ( netdev );
|
|
|
|
rtl_reset ( rtl );
|
|
|
|
free_netdev ( netdev );
|
2005-03-08 19:53:11 +01:00
|
|
|
}
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
static struct pci_device_id rtl8139_nics[] = {
|
|
|
|
PCI_ROM(0x10ec, 0x8129, "rtl8129", "Realtek 8129"),
|
|
|
|
PCI_ROM(0x10ec, 0x8139, "rtl8139", "Realtek 8139"),
|
|
|
|
PCI_ROM(0x10ec, 0x8138, "rtl8139b", "Realtek 8139B"),
|
|
|
|
PCI_ROM(0x1186, 0x1300, "dfe538", "DFE530TX+/DFE538TX"),
|
|
|
|
PCI_ROM(0x1113, 0x1211, "smc1211-1", "SMC EZ10/100"),
|
|
|
|
PCI_ROM(0x1112, 0x1211, "smc1211", "SMC EZ10/100"),
|
|
|
|
PCI_ROM(0x1500, 0x1360, "delta8139", "Delta Electronics 8139"),
|
|
|
|
PCI_ROM(0x4033, 0x1360, "addtron8139", "Addtron Technology 8139"),
|
|
|
|
PCI_ROM(0x1186, 0x1340, "dfe690txd", "D-Link DFE690TXD"),
|
|
|
|
PCI_ROM(0x13d1, 0xab06, "fe2000vx", "AboCom FE2000VX"),
|
|
|
|
PCI_ROM(0x1259, 0xa117, "allied8139", "Allied Telesyn 8139"),
|
|
|
|
PCI_ROM(0x14ea, 0xab06, "fnw3603tx", "Planex FNW-3603-TX"),
|
|
|
|
PCI_ROM(0x14ea, 0xab07, "fnw3800tx", "Planex FNW-3800-TX"),
|
|
|
|
PCI_ROM(0xffff, 0x8139, "clone-rtl8139", "Cloned 8139"),
|
2005-04-13 03:01:33 +02:00
|
|
|
};
|
|
|
|
|
2007-06-19 00:30:33 +02:00
|
|
|
struct pci_driver rtl8139_driver __pci_driver = {
|
|
|
|
.ids = rtl8139_nics,
|
|
|
|
.id_count = ( sizeof ( rtl8139_nics ) / sizeof ( rtl8139_nics[0] ) ),
|
|
|
|
.probe = rtl_probe,
|
|
|
|
.remove = rtl_remove,
|
2005-03-08 19:53:11 +01:00
|
|
|
};
|