342 lines
9.8 KiB
C
342 lines
9.8 KiB
C
#ifndef _IPXE_PCI_H
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#define _IPXE_PCI_H
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/** @file
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*
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* PCI bus
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/device.h>
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#include <ipxe/tables.h>
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#include <ipxe/pci_io.h>
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/** PCI vendor ID */
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#define PCI_VENDOR_ID 0x00
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/** PCI device ID */
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#define PCI_DEVICE_ID 0x02
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/** PCI command */
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#define PCI_COMMAND 0x04
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#define PCI_COMMAND_IO 0x0001 /**< I/O space */
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#define PCI_COMMAND_MEM 0x0002 /**< Memory space */
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#define PCI_COMMAND_MASTER 0x0004 /**< Bus master */
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#define PCI_COMMAND_INVALIDATE 0x0010 /**< Mem. write & invalidate */
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#define PCI_COMMAND_PARITY 0x0040 /**< Parity error response */
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#define PCI_COMMAND_SERR 0x0100 /**< SERR# enable */
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#define PCI_COMMAND_INTX_DISABLE 0x0400 /**< Interrupt disable */
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/** PCI status */
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#define PCI_STATUS 0x06
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#define PCI_STATUS_CAP_LIST 0x0010 /**< Capabilities list */
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#define PCI_STATUS_PARITY 0x0100 /**< Master data parity error */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /**< Received target abort */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /**< Received master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /**< Signalled system error */
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#define PCI_STATUS_DETECTED_PARITY 0x8000 /**< Detected parity error */
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/** PCI revision */
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#define PCI_REVISION 0x08
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/** PCI cache line size */
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#define PCI_CACHE_LINE_SIZE 0x0c
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/** PCI latency timer */
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#define PCI_LATENCY_TIMER 0x0d
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/** PCI header type */
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#define PCI_HEADER_TYPE 0x0e
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#define PCI_HEADER_TYPE_NORMAL 0x00 /**< Normal header */
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#define PCI_HEADER_TYPE_BRIDGE 0x01 /**< PCI-to-PCI bridge header */
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#define PCI_HEADER_TYPE_CARDBUS 0x02 /**< CardBus header */
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#define PCI_HEADER_TYPE_MASK 0x7f /**< Header type mask */
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#define PCI_HEADER_TYPE_MULTI 0x80 /**< Multi-function device */
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/** PCI base address registers */
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#define PCI_BASE_ADDRESS(n) ( 0x10 + ( 4 * (n) ) )
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#define PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 )
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#define PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 )
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#define PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 )
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#define PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 )
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#define PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 )
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#define PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 )
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#define PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL /**< I/O BAR */
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#define PCI_BASE_ADDRESS_IO_MASK 0x00000003UL /**< I/O BAR mask */
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#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL /**< 64-bit memory */
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#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL /**< Memory type mask */
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#define PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL /**< Memory BAR mask */
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/** PCI subsystem vendor ID */
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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/** PCI subsystem ID */
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#define PCI_SUBSYSTEM_ID 0x2e
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/** PCI expansion ROM base address */
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#define PCI_ROM_ADDRESS 0x30
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/** PCI capabilities pointer */
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#define PCI_CAPABILITY_LIST 0x34
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/** CardBus capabilities pointer */
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#define PCI_CB_CAPABILITY_LIST 0x14
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/** PCI interrupt line */
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#define PCI_INTERRUPT_LINE 0x3c
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/** Capability ID */
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#define PCI_CAP_ID 0x00
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#define PCI_CAP_ID_PM 0x01 /**< Power management */
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#define PCI_CAP_ID_VPD 0x03 /**< Vital product data */
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#define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */
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#define PCI_CAP_ID_EXP 0x10 /**< PCI Express */
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#define PCI_CAP_ID_EA 0x14 /**< Enhanced Allocation */
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/** Next capability */
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#define PCI_CAP_NEXT 0x01
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/** Power management control and status */
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#define PCI_PM_CTRL 0x04
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#define PCI_PM_CTRL_STATE_MASK 0x0003 /**< Current power state */
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#define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */
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#define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */
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/** PCI Express */
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#define PCI_EXP_DEVCTL 0x08
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#define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */
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/** Uncorrectable error status */
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#define PCI_ERR_UNCOR_STATUS 0x04
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/** Network controller */
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#define PCI_CLASS_NETWORK 0x02
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/** Serial bus controller */
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#define PCI_CLASS_SERIAL 0x0c
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#define PCI_CLASS_SERIAL_USB 0x03 /**< USB controller */
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#define PCI_CLASS_SERIAL_USB_UHCI 0x00 /**< UHCI USB controller */
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#define PCI_CLASS_SERIAL_USB_OHCI 0x10 /**< OHCI USB controller */
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#define PCI_CLASS_SERIAL_USB_EHCI 0x20 /**< ECHI USB controller */
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#define PCI_CLASS_SERIAL_USB_XHCI 0x30 /**< xHCI USB controller */
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/** Construct PCI class
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*
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* @v base Base class (or PCI_ANY_ID)
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* @v sub Subclass (or PCI_ANY_ID)
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* @v progif Programming interface (or PCI_ANY_ID)
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*/
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#define PCI_CLASS( base, sub, progif ) \
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( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \
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( ( (progif) & 0xff) << 0 ) )
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/** PCI Express function level reset delay (in ms) */
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#define PCI_EXP_FLR_DELAY_MS 100
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/** A PCI device ID list entry */
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struct pci_device_id {
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/** Name */
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const char *name;
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/** PCI vendor ID */
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uint16_t vendor;
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/** PCI device ID */
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uint16_t device;
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/** Arbitrary driver data */
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unsigned long driver_data;
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};
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/** Match-anything ID */
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#define PCI_ANY_ID 0xffff
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/** A PCI class ID */
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struct pci_class_id {
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/** Class */
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uint32_t class;
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/** Class mask */
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uint32_t mask;
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};
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/** Construct PCI class ID
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*
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* @v base Base class (or PCI_ANY_ID)
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* @v sub Subclass (or PCI_ANY_ID)
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* @v progif Programming interface (or PCI_ANY_ID)
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*/
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#define PCI_CLASS_ID( base, sub, progif ) { \
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.class = PCI_CLASS ( base, sub, progif ), \
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.mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) | \
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( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) | \
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( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
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}
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/** A PCI device */
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struct pci_device {
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/** Generic device */
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struct device dev;
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/** Memory base
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*
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* This is the physical address of the first valid memory BAR.
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*/
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unsigned long membase;
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/**
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* I/O address
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*
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* This is the physical address of the first valid I/O BAR.
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*/
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unsigned long ioaddr;
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/** Vendor ID */
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uint16_t vendor;
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/** Device ID */
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uint16_t device;
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/** Device class */
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uint32_t class;
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/** Interrupt number */
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uint8_t irq;
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/** Segment, bus, device, and function (bus:dev.fn) number */
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uint32_t busdevfn;
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/** Driver for this device */
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struct pci_driver *driver;
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/** Driver-private data
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*
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* Use pci_set_drvdata() and pci_get_drvdata() to access this
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* field.
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*/
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void *priv;
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/** Driver device ID */
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struct pci_device_id *id;
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};
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/** A PCI driver */
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struct pci_driver {
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/** PCI ID table */
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struct pci_device_id *ids;
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/** Number of entries in PCI ID table */
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unsigned int id_count;
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/** PCI class ID */
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struct pci_class_id class;
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/**
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* Probe device
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*
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* @v pci PCI device
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* @ret rc Return status code
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*/
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int ( * probe ) ( struct pci_device *pci );
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/**
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* Remove device
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*
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* @v pci PCI device
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*/
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void ( * remove ) ( struct pci_device *pci );
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};
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/** PCI driver table */
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#define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
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/** Declare a PCI driver */
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#define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
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/** Declare a fallback PCI driver */
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#define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
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#define PCI_SEG( busdevfn ) ( ( (busdevfn) >> 16 ) & 0xffff )
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#define PCI_BUS( busdevfn ) ( ( (busdevfn) >> 8 ) & 0xff )
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#define PCI_SLOT( busdevfn ) ( ( (busdevfn) >> 3 ) & 0x1f )
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#define PCI_FUNC( busdevfn ) ( ( (busdevfn) >> 0 ) & 0x07 )
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#define PCI_BUSDEVFN( segment, bus, slot, func ) \
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( ( (segment) << 16 ) | ( (bus) << 8 ) | \
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( (slot) << 3 ) | ( (func) << 0 ) )
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#define PCI_FIRST_FUNC( busdevfn ) ( (busdevfn) & ~0x07 )
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#define PCI_LAST_FUNC( busdevfn ) ( (busdevfn) | 0x07 )
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#define PCI_BASE_CLASS( class ) ( (class) >> 16 )
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#define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff )
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#define PCI_PROG_INTF( class ) ( (class) & 0xff )
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/*
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* PCI_ROM is used to build up entries in a struct pci_id array. It
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* is also parsed by parserom.pl to generate Makefile rules and files
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* for rom-o-matic.
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*
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* PCI_ID can be used to generate entries without creating a
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* corresponding ROM in the build process.
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*/
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#define PCI_ID( _vendor, _device, _name, _description, _data ) { \
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.vendor = _vendor, \
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.device = _device, \
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.name = _name, \
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.driver_data = _data \
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}
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#define PCI_ROM( _vendor, _device, _name, _description, _data ) \
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PCI_ID( _vendor, _device, _name, _description, _data )
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/** PCI device debug message format */
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#define PCI_FMT "%04x:%02x:%02x.%x"
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/** PCI device debug message arguments */
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#define PCI_ARGS( pci ) \
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PCI_SEG ( (pci)->busdevfn ), PCI_BUS ( (pci)->busdevfn ), \
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PCI_SLOT ( (pci)->busdevfn ), PCI_FUNC ( (pci)->busdevfn )
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extern void adjust_pci_device ( struct pci_device *pci );
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extern unsigned long pci_bar_start ( struct pci_device *pci,
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unsigned int reg );
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extern int pci_read_config ( struct pci_device *pci );
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extern int pci_find_next ( struct pci_device *pci, unsigned int busdevfn );
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extern int pci_find_driver ( struct pci_device *pci );
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extern int pci_probe ( struct pci_device *pci );
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extern void pci_remove ( struct pci_device *pci );
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extern int pci_find_capability ( struct pci_device *pci, int capability );
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extern int pci_find_next_capability ( struct pci_device *pci,
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int pos, int capability );
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extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
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/**
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* Initialise PCI device
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*
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* @v pci PCI device
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* @v busdevfn PCI bus:dev.fn address
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*/
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static inline void pci_init ( struct pci_device *pci, unsigned int busdevfn ) {
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pci->busdevfn = busdevfn;
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}
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/**
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* Set PCI driver
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*
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* @v pci PCI device
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* @v driver PCI driver
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* @v id PCI device ID
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*/
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static inline void pci_set_driver ( struct pci_device *pci,
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struct pci_driver *driver,
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struct pci_device_id *id ) {
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pci->driver = driver;
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pci->id = id;
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pci->dev.driver_name = id->name;
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}
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/**
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* Set PCI driver-private data
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*
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* @v pci PCI device
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* @v priv Private data
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*/
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static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
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pci->priv = priv;
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}
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/**
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* Get PCI driver-private data
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*
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* @v pci PCI device
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* @ret priv Private data
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*/
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static inline void * pci_get_drvdata ( struct pci_device *pci ) {
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return pci->priv;
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}
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#endif /* _IPXE_PCI_H */
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