262 lines
6.1 KiB
C
262 lines
6.1 KiB
C
#ifndef _EXANIC_H
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#define _EXANIC_H
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/** @file
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*
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* Exablaze ExaNIC driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/pci.h>
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#include <ipxe/ethernet.h>
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#include <ipxe/uaccess.h>
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#include <ipxe/retry.h>
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#include <ipxe/i2c.h>
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#include <ipxe/bitbash.h>
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/** Maximum number of ports */
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#define EXANIC_MAX_PORTS 8
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/** Register BAR */
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#define EXANIC_REGS_BAR PCI_BASE_ADDRESS_0
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/** Transmit region BAR */
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#define EXANIC_TX_BAR PCI_BASE_ADDRESS_2
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/** Alignment for DMA regions */
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#define EXANIC_ALIGN 0x1000
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/** Flag for 32-bit DMA addresses */
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#define EXANIC_DMA_32_BIT 0x00000001UL
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/** Register set length */
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#define EXANIC_REGS_LEN 0x2000
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/** Transmit feedback region length */
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#define EXANIC_TXF_LEN 0x1000
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/** Transmit feedback slot
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*
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* This is a policy decision.
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*/
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#define EXANIC_TXF_SLOT( index ) ( 0x40 * (index) )
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/** Receive region length */
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#define EXANIC_RX_LEN 0x200000
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/** Transmit feedback base address register */
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#define EXANIC_TXF_BASE 0x0014
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/** Capabilities register */
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#define EXANIC_CAPS 0x0038
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#define EXANIC_CAPS_100M 0x01000000UL /**< 100Mbps supported */
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#define EXANIC_CAPS_1G 0x02000000UL /**< 1Gbps supported */
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#define EXANIC_CAPS_10G 0x04000000UL /**< 10Gbps supported */
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#define EXANIC_CAPS_40G 0x08000000UL /**< 40Gbps supported */
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#define EXANIC_CAPS_100G 0x10000000UL /**< 100Gbps supported */
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#define EXANIC_CAPS_SPEED_MASK 0x1f000000UL /**< Supported speeds mask */
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/** I2C GPIO register */
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#define EXANIC_I2C 0x012c
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/** Power control register */
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#define EXANIC_POWER 0x0138
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#define EXANIC_POWER_ON 0x000000f0UL /**< Power on PHYs */
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/** Port register offset */
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#define EXANIC_PORT_REGS( index ) ( 0x0200 + ( 0x40 * (index) ) )
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/** Port enable register */
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#define EXANIC_PORT_ENABLE 0x0000
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#define EXANIC_PORT_ENABLE_ENABLED 0x00000001UL /**< Port is enabled */
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/** Port speed register */
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#define EXANIC_PORT_SPEED 0x0004
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/** Port status register */
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#define EXANIC_PORT_STATUS 0x0008
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#define EXANIC_PORT_STATUS_LINK 0x00000008UL /**< Link is up */
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#define EXANIC_PORT_STATUS_ABSENT 0x80000000UL /**< Port is not present */
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/** Port MAC address (second half) register */
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#define EXANIC_PORT_MAC 0x000c
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/** Port flags register */
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#define EXANIC_PORT_FLAGS 0x0010
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#define EXANIC_PORT_FLAGS_PROMISC 0x00000001UL /**< Promiscuous mode */
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/** Port receive chunk base address register */
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#define EXANIC_PORT_RX_BASE 0x0014
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/** Port transmit command register */
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#define EXANIC_PORT_TX_COMMAND 0x0020
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/** Port transmit region offset register */
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#define EXANIC_PORT_TX_OFFSET 0x0024
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/** Port transmit region length register */
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#define EXANIC_PORT_TX_LEN 0x0028
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/** Port MAC address (first half) register */
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#define EXANIC_PORT_OUI 0x0030
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/** Port interrupt configuration register */
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#define EXANIC_PORT_IRQ 0x0034
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/** An ExaNIC transmit chunk descriptor */
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struct exanic_tx_descriptor {
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/** Feedback ID */
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uint16_t txf_id;
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/** Feedback slot */
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uint16_t txf_slot;
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/** Payload length (including padding */
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uint16_t len;
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/** Payload type */
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uint8_t type;
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/** Flags */
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uint8_t flags;
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} __attribute__ (( packed ));
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/** An ExaNIC transmit chunk */
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struct exanic_tx_chunk {
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/** Descriptor */
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struct exanic_tx_descriptor desc;
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/** Padding */
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uint8_t pad[2];
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/** Payload data */
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uint8_t data[2038];
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} __attribute__ (( packed ));
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/** Raw Ethernet frame type */
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#define EXANIC_TYPE_RAW 0x01
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/** An ExaNIC receive chunk descriptor */
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struct exanic_rx_descriptor {
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/** Timestamp */
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uint32_t timestamp;
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/** Status (valid only on final chunk) */
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uint8_t status;
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/** Length (zero except on the final chunk) */
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uint8_t len;
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/** Filter number */
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uint8_t filter;
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/** Generation */
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uint8_t generation;
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} __attribute__ (( packed ));
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/** An ExaNIC receive chunk */
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struct exanic_rx_chunk {
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/** Payload data */
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uint8_t data[120];
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/** Descriptor */
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struct exanic_rx_descriptor desc;
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} __attribute__ (( packed ));
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/** Receive status error mask */
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#define EXANIC_STATUS_ERROR_MASK 0x0f
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/** An ExaNIC I2C bus configuration */
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struct exanic_i2c_config {
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/** GPIO bit for pulling SCL low */
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uint8_t setscl;
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/** GPIO bit for pulling SDA low */
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uint8_t setsda;
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/** GPIO bit for reading SDA */
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uint8_t getsda;
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};
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/** EEPROM address */
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#define EXANIC_EEPROM_ADDRESS 0x50
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/** An ExaNIC port */
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struct exanic_port {
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/** Network device */
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struct net_device *netdev;
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/** Port registers */
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void *regs;
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/** Transmit region offset */
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size_t tx_offset;
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/** Transmit region */
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void *tx;
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/** Number of transmit descriptors */
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uint16_t tx_count;
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/** Transmit producer counter */
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uint16_t tx_prod;
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/** Transmit consumer counter */
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uint16_t tx_cons;
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/** Transmit feedback slot */
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uint16_t txf_slot;
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/** Transmit feedback region */
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uint16_t *txf;
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/** Receive region */
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userptr_t rx;
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/** Receive consumer counter */
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unsigned int rx_cons;
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/** Receive I/O buffer (if any) */
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struct io_buffer *rx_iobuf;
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/** Receive status */
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int rx_rc;
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/** Port status */
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uint32_t status;
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/** Default link speed (as raw register value) */
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uint32_t default_speed;
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/** Speed capability bitmask */
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uint32_t speeds;
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/** Current attempted link speed (as a capability bit index) */
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unsigned int speed;
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/** Port status check timer */
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struct retry_timer timer;
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};
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/** An ExaNIC */
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struct exanic {
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/** Registers */
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void *regs;
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/** Transmit region */
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void *tx;
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/** Transmit feedback region */
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void *txf;
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/** I2C bus configuration */
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struct exanic_i2c_config i2cfg;
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/** I2C bit-bashing interface */
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struct i2c_bit_basher basher;
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/** I2C serial EEPROM */
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struct i2c_device eeprom;
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/** Capabilities */
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uint32_t caps;
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/** Base MAC address */
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uint8_t mac[ETH_ALEN];
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/** Ports */
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struct exanic_port *port[EXANIC_MAX_PORTS];
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};
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/** Maximum used length of transmit region
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*
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* This is a policy decision to avoid overflowing the 16-bit transmit
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* producer and consumer counters.
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*/
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#define EXANIC_MAX_TX_LEN ( 256 * sizeof ( struct exanic_tx_chunk ) )
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/** Maximum length of received packet
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*
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* This is a policy decision.
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*/
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#define EXANIC_MAX_RX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
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/** Interval between link state checks
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*
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* This is a policy decision.
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*/
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#define EXANIC_LINK_INTERVAL ( 1 * TICKS_PER_SEC )
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#endif /* _EXANIC_H */
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