![Michael Brown](/assets/img/avatar_default.png)
ISA 3c509 is currently non-functional, although the EISA (3c509-eisa) and MCA (3c529) variants should build OK. None of this code is yet tested.
952 lines
26 KiB
C
952 lines
26 KiB
C
#ifdef ALLMULTI
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#error multicast support is not yet implemented
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#endif
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/*------------------------------------------------------------------------
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* smc9000.c
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* This is a Etherboot driver for SMC's 9000 series of Ethernet cards.
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*
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* Copyright (C) 1998 Daniel Engström <daniel.engstrom@riksnett.no>
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* Based on the Linux SMC9000 driver, smc9194.c by Eric Stahlman
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* Copyright (C) 1996 by Erik Stahlman <eric@vt.edu>
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*
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* This software may be used and distributed according to the terms
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* of the GNU Public License, incorporated herein by reference.
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*
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* "Features" of the SMC chip:
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* 4608 byte packet memory. ( for the 91C92/4. Others have more )
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* EEPROM for configuration
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* AUI/TP selection
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*
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* Authors
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* Erik Stahlman <erik@vt.edu>
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* Daniel Engström <daniel.engstrom@riksnett.no>
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*
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* History
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* 98-09-25 Daniel Engström Etherboot driver crated from Eric's
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* Linux driver.
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*
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*---------------------------------------------------------------------------*/
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#define LINUX_OUT_MACROS 1
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#define SMC9000_DEBUG 0
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#if SMC9000_DEBUG > 1
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#define PRINTK2 printf
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#else
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#define PRINTK2(args...)
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#endif
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#include <gpxe/ethernet.h>
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#include "etherboot.h"
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#include "nic.h"
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#include <gpxe/isa.h>
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#include "timer.h"
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#include "smc9000.h"
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# define _outb outb
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# define _outw outw
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static const char smc9000_version[] = "Version 0.99 98-09-30";
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static const char *interfaces[ 2 ] = { "TP", "AUI" };
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static const char *chip_ids[ 15 ] = {
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NULL, NULL, NULL,
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/* 3 */ "SMC91C90/91C92",
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/* 4 */ "SMC91C94",
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/* 5 */ "SMC91C95",
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NULL,
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/* 7 */ "SMC91C100",
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/* 8 */ "SMC91C100FD",
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/* 9 */ "SMC91C11xFD",
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NULL, NULL,
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NULL, NULL, NULL
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};
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static const char smc91c96_id[] = "SMC91C96";
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/*------------------------------------------------------------
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. Reads a register from the MII Management serial interface
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.-------------------------------------------------------------*/
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static word smc_read_phy_register(int ioaddr, byte phyaddr, byte phyreg)
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{
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int oldBank;
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unsigned int i;
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byte mask;
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word mii_reg;
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byte bits[64];
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int clk_idx = 0;
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int input_idx;
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word phydata;
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// 32 consecutive ones on MDO to establish sync
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for (i = 0; i < 32; ++i)
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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// Start code <01>
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bits[clk_idx++] = MII_MDOE;
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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// Read command <10>
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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bits[clk_idx++] = MII_MDOE;
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// Output the PHY address, msb first
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mask = (byte)0x10;
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for (i = 0; i < 5; ++i)
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{
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if (phyaddr & mask)
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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else
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bits[clk_idx++] = MII_MDOE;
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// Shift to next lowest bit
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mask >>= 1;
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}
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// Output the phy register number, msb first
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mask = (byte)0x10;
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for (i = 0; i < 5; ++i)
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{
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if (phyreg & mask)
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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else
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bits[clk_idx++] = MII_MDOE;
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// Shift to next lowest bit
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mask >>= 1;
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}
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// Tristate and turnaround (2 bit times)
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bits[clk_idx++] = 0;
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//bits[clk_idx++] = 0;
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// Input starts at this bit time
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input_idx = clk_idx;
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// Will input 16 bits
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for (i = 0; i < 16; ++i)
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bits[clk_idx++] = 0;
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// Final clock bit
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bits[clk_idx++] = 0;
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// Save the current bank
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oldBank = inw( ioaddr+BANK_SELECT );
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// Select bank 3
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SMC_SELECT_BANK(ioaddr, 3);
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// Get the current MII register value
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mii_reg = inw( ioaddr+MII_REG );
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// Turn off all MII Interface bits
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mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
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// Clock all 64 cycles
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for (i = 0; i < sizeof(bits); ++i)
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{
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// Clock Low - output data
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outw( mii_reg | bits[i], ioaddr+MII_REG );
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udelay(50);
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// Clock Hi - input data
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outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
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udelay(50);
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bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
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}
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// Return to idle state
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// Set clock to low, data to low, and output tristated
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outw( mii_reg, ioaddr+MII_REG );
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udelay(50);
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// Restore original bank select
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SMC_SELECT_BANK(ioaddr, oldBank);
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// Recover input data
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phydata = 0;
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for (i = 0; i < 16; ++i)
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{
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phydata <<= 1;
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if (bits[input_idx++] & MII_MDI)
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phydata |= 0x0001;
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}
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#if (SMC_DEBUG > 2 )
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printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
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phyaddr, phyreg, phydata);
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#endif
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return(phydata);
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}
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/*------------------------------------------------------------
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. Writes a register to the MII Management serial interface
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.-------------------------------------------------------------*/
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static void smc_write_phy_register(int ioaddr,
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byte phyaddr, byte phyreg, word phydata)
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{
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int oldBank;
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unsigned int i;
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word mask;
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word mii_reg;
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byte bits[65];
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int clk_idx = 0;
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// 32 consecutive ones on MDO to establish sync
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for (i = 0; i < 32; ++i)
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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// Start code <01>
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bits[clk_idx++] = MII_MDOE;
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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// Write command <01>
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bits[clk_idx++] = MII_MDOE;
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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// Output the PHY address, msb first
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mask = (byte)0x10;
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for (i = 0; i < 5; ++i)
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{
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if (phyaddr & mask)
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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else
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bits[clk_idx++] = MII_MDOE;
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// Shift to next lowest bit
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mask >>= 1;
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}
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// Output the phy register number, msb first
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mask = (byte)0x10;
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for (i = 0; i < 5; ++i)
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{
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if (phyreg & mask)
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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else
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bits[clk_idx++] = MII_MDOE;
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// Shift to next lowest bit
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mask >>= 1;
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}
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// Tristate and turnaround (2 bit times)
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bits[clk_idx++] = 0;
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bits[clk_idx++] = 0;
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// Write out 16 bits of data, msb first
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mask = 0x8000;
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for (i = 0; i < 16; ++i)
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{
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if (phydata & mask)
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bits[clk_idx++] = MII_MDOE | MII_MDO;
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else
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bits[clk_idx++] = MII_MDOE;
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// Shift to next lowest bit
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mask >>= 1;
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}
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// Final clock bit (tristate)
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bits[clk_idx++] = 0;
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// Save the current bank
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oldBank = inw( ioaddr+BANK_SELECT );
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// Select bank 3
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SMC_SELECT_BANK(ioaddr, 3);
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// Get the current MII register value
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mii_reg = inw( ioaddr+MII_REG );
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// Turn off all MII Interface bits
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mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
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// Clock all cycles
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for (i = 0; i < sizeof(bits); ++i)
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{
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// Clock Low - output data
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outw( mii_reg | bits[i], ioaddr+MII_REG );
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udelay(50);
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// Clock Hi - input data
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outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
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udelay(50);
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bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
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}
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// Return to idle state
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// Set clock to low, data to low, and output tristated
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outw( mii_reg, ioaddr+MII_REG );
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udelay(50);
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// Restore original bank select
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SMC_SELECT_BANK(ioaddr, oldBank);
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#if (SMC_DEBUG > 2 )
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printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
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phyaddr, phyreg, phydata);
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#endif
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}
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/*------------------------------------------------------------
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. Finds and reports the PHY address
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.-------------------------------------------------------------*/
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static int smc_detect_phy(int ioaddr, byte *pphyaddr)
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{
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word phy_id1;
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word phy_id2;
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int phyaddr;
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int found = 0;
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// Scan all 32 PHY addresses if necessary
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for (phyaddr = 0; phyaddr < 32; ++phyaddr)
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{
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// Read the PHY identifiers
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phy_id1 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG);
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phy_id2 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG);
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// Make sure it is a valid identifier
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if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) &&
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(phy_id1 > 0x0000) && (phy_id1 < 0xffff))
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{
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if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000))
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{
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// Save the PHY's address
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*pphyaddr = phyaddr;
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found = 1;
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break;
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}
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}
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}
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if (!found)
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{
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printf("No PHY found\n");
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return(0);
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}
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// Set the PHY type
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if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) )
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{
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printf("PHY=LAN83C183 (LAN91C111 Internal)\n");
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}
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if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) )
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{
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printf("PHY=LAN83C180\n");
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}
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return(1);
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}
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/*------------------------------------------------------------
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. Configures the specified PHY using Autonegotiation. Calls
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. smc_phy_fixed() if the user has requested a certain config.
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.-------------------------------------------------------------*/
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static void smc_phy_configure(int ioaddr)
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{
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int timeout;
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byte phyaddr;
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word my_phy_caps; // My PHY capabilities
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word my_ad_caps; // My Advertised capabilities
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word status;
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int failed = 0;
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int rpc_cur_mode = RPC_DEFAULT;
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int lastPhy18;
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// Find the address and type of our phy
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if (!smc_detect_phy(ioaddr, &phyaddr))
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{
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return;
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}
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// Reset the PHY, setting all other bits to zero
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smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST);
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// Wait for the reset to complete, or time out
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timeout = 6; // Wait up to 3 seconds
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while (timeout--)
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{
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if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG)
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& PHY_CNTL_RST))
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{
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// reset complete
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break;
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}
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mdelay(500); // wait 500 millisecs
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}
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if (timeout < 1)
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{
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PRINTK2("PHY reset timed out\n");
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return;
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}
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// Read PHY Register 18, Status Output
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lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
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// Enable PHY Interrupts (for register 18)
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// Interrupts listed here are disabled
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smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG,
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PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
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PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
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PHY_INT_SPDDET | PHY_INT_DPLXDET);
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/* Configure the Receive/Phy Control register */
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SMC_SELECT_BANK(ioaddr, 0);
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outw( rpc_cur_mode, ioaddr + RPC_REG );
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// Copy our capabilities from PHY_STAT_REG to PHY_AD_REG
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my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
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my_ad_caps = PHY_AD_CSMA; // I am CSMA capable
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if (my_phy_caps & PHY_STAT_CAP_T4)
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my_ad_caps |= PHY_AD_T4;
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if (my_phy_caps & PHY_STAT_CAP_TXF)
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my_ad_caps |= PHY_AD_TX_FDX;
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if (my_phy_caps & PHY_STAT_CAP_TXH)
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my_ad_caps |= PHY_AD_TX_HDX;
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if (my_phy_caps & PHY_STAT_CAP_TF)
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my_ad_caps |= PHY_AD_10_FDX;
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if (my_phy_caps & PHY_STAT_CAP_TH)
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my_ad_caps |= PHY_AD_10_HDX;
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// Update our Auto-Neg Advertisement Register
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smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps);
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PRINTK2("phy caps=%x\n", my_phy_caps);
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PRINTK2("phy advertised caps=%x\n", my_ad_caps);
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// Restart auto-negotiation process in order to advertise my caps
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smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
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PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
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// Wait for the auto-negotiation to complete. This may take from
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// 2 to 3 seconds.
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// Wait for the reset to complete, or time out
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timeout = 20; // Wait up to 10 seconds
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while (timeout--)
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{
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status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
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if (status & PHY_STAT_ANEG_ACK)
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{
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// auto-negotiate complete
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break;
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}
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mdelay(500); // wait 500 millisecs
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// Restart auto-negotiation if remote fault
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if (status & PHY_STAT_REM_FLT)
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{
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PRINTK2("PHY remote fault detected\n");
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// Restart auto-negotiation
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PRINTK2("PHY restarting auto-negotiation\n");
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smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
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PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
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PHY_CNTL_SPEED | PHY_CNTL_DPLX);
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}
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}
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if (timeout < 1)
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{
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PRINTK2("PHY auto-negotiate timed out\n");
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failed = 1;
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}
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// Fail if we detected an auto-negotiate remote fault
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if (status & PHY_STAT_REM_FLT)
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{
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PRINTK2("PHY remote fault detected\n");
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failed = 1;
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}
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// Set our sysctl parameters to match auto-negotiation results
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if ( lastPhy18 & PHY_INT_SPDDET )
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{
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PRINTK2("PHY 100BaseT\n");
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rpc_cur_mode |= RPC_SPEED;
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}
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else
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{
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PRINTK2("PHY 10BaseT\n");
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rpc_cur_mode &= ~RPC_SPEED;
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}
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if ( lastPhy18 & PHY_INT_DPLXDET )
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{
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PRINTK2("PHY Full Duplex\n");
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rpc_cur_mode |= RPC_DPLX;
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}
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else
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{
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PRINTK2("PHY Half Duplex\n");
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rpc_cur_mode &= ~RPC_DPLX;
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}
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// Re-Configure the Receive/Phy Control register
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outw( rpc_cur_mode, ioaddr + RPC_REG );
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}
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/*
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* Function: smc_reset( int ioaddr )
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* Purpose:
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* This sets the SMC91xx chip to its normal state, hopefully from whatever
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* mess that any other DOS driver has put it in.
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*
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* Maybe I should reset more registers to defaults in here? SOFTRESET should
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* do that for me.
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*
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* Method:
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* 1. send a SOFT RESET
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* 2. wait for it to finish
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* 3. reset the memory management unit
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* 4. clear all interrupts
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*
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*/
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static void smc_reset(int ioaddr)
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{
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/* This resets the registers mostly to defaults, but doesn't
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* affect EEPROM. That seems unnecessary */
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SMC_SELECT_BANK(ioaddr, 0);
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_outw( RCR_SOFTRESET, ioaddr + RCR );
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/* this should pause enough for the chip to be happy */
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SMC_DELAY(ioaddr);
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|
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/* Set the transmit and receive configuration registers to
|
|
* default values */
|
|
_outw(RCR_CLEAR, ioaddr + RCR);
|
|
_outw(TCR_CLEAR, ioaddr + TCR);
|
|
|
|
/* Reset the MMU */
|
|
SMC_SELECT_BANK(ioaddr, 2);
|
|
_outw( MC_RESET, ioaddr + MMU_CMD );
|
|
|
|
/* Note: It doesn't seem that waiting for the MMU busy is needed here,
|
|
* but this is a place where future chipsets _COULD_ break. Be wary
|
|
* of issuing another MMU command right after this */
|
|
_outb(0, ioaddr + INT_MASK);
|
|
}
|
|
|
|
|
|
/*----------------------------------------------------------------------
|
|
* Function: smc9000_probe_addr( int ioaddr )
|
|
*
|
|
* Purpose:
|
|
* Tests to see if a given ioaddr points to an SMC9xxx chip.
|
|
* Returns a 1 on success
|
|
*
|
|
* Algorithm:
|
|
* (1) see if the high byte of BANK_SELECT is 0x33
|
|
* (2) compare the ioaddr with the base register's address
|
|
* (3) see if I recognize the chip ID in the appropriate register
|
|
*
|
|
* ---------------------------------------------------------------------
|
|
*/
|
|
static int smc9000_probe_addr( isa_probe_addr_t ioaddr )
|
|
{
|
|
word bank;
|
|
word revision_register;
|
|
word base_address_register;
|
|
|
|
/* First, see if the high byte is 0x33 */
|
|
bank = inw(ioaddr + BANK_SELECT);
|
|
if ((bank & 0xFF00) != 0x3300) {
|
|
return 0;
|
|
}
|
|
/* The above MIGHT indicate a device, but I need to write to further
|
|
* test this. */
|
|
_outw(0x0, ioaddr + BANK_SELECT);
|
|
bank = inw(ioaddr + BANK_SELECT);
|
|
if ((bank & 0xFF00) != 0x3300) {
|
|
return 0;
|
|
}
|
|
|
|
/* well, we've already written once, so hopefully another time won't
|
|
* hurt. This time, I need to switch the bank register to bank 1,
|
|
* so I can access the base address register */
|
|
SMC_SELECT_BANK(ioaddr, 1);
|
|
base_address_register = inw(ioaddr + BASE);
|
|
|
|
if (ioaddr != (base_address_register >> 3 & 0x3E0)) {
|
|
DBG("SMC9000: IOADDR %hX doesn't match configuration (%hX)."
|
|
"Probably not a SMC chip\n",
|
|
ioaddr, base_address_register >> 3 & 0x3E0);
|
|
/* well, the base address register didn't match. Must not have
|
|
* been a SMC chip after all. */
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* check if the revision register is something that I recognize.
|
|
* These might need to be added to later, as future revisions
|
|
* could be added. */
|
|
SMC_SELECT_BANK(ioaddr, 3);
|
|
revision_register = inw(ioaddr + REVISION);
|
|
if (!chip_ids[(revision_register >> 4) & 0xF]) {
|
|
/* I don't recognize this chip, so... */
|
|
DBG( "SMC9000: IO %hX: Unrecognized revision register:"
|
|
" %hX, Contact author.\n", ioaddr, revision_register );
|
|
return 0;
|
|
}
|
|
|
|
/* at this point I'll assume that the chip is an SMC9xxx.
|
|
* It might be prudent to check a listing of MAC addresses
|
|
* against the hardware address, or do some other tests. */
|
|
return 1;
|
|
}
|
|
|
|
|
|
/**************************************************************************
|
|
* ETH_TRANSMIT - Transmit a frame
|
|
***************************************************************************/
|
|
static void smc9000_transmit(
|
|
struct nic *nic,
|
|
const char *d, /* Destination */
|
|
unsigned int t, /* Type */
|
|
unsigned int s, /* size */
|
|
const char *p) /* Packet */
|
|
{
|
|
word length; /* real, length incl. header */
|
|
word numPages;
|
|
unsigned long time_out;
|
|
byte packet_no;
|
|
word status;
|
|
int i;
|
|
|
|
/* We dont pad here since we can have the hardware doing it for us */
|
|
length = (s + ETH_HLEN + 1)&~1;
|
|
|
|
/* convert to MMU pages */
|
|
numPages = length / 256;
|
|
|
|
if (numPages > 7 ) {
|
|
DBG("SMC9000: Far too big packet error. \n");
|
|
return;
|
|
}
|
|
|
|
/* dont try more than, say 30 times */
|
|
for (i=0;i<30;i++) {
|
|
/* now, try to allocate the memory */
|
|
SMC_SELECT_BANK(nic->ioaddr, 2);
|
|
_outw(MC_ALLOC | numPages, nic->ioaddr + MMU_CMD);
|
|
|
|
status = 0;
|
|
/* wait for the memory allocation to finnish */
|
|
for (time_out = currticks() + 5*TICKS_PER_SEC; currticks() < time_out; ) {
|
|
status = inb(nic->ioaddr + INTERRUPT);
|
|
if ( status & IM_ALLOC_INT ) {
|
|
/* acknowledge the interrupt */
|
|
_outb(IM_ALLOC_INT, nic->ioaddr + INTERRUPT);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if ((status & IM_ALLOC_INT) != 0 ) {
|
|
/* We've got the memory */
|
|
break;
|
|
} else {
|
|
printf("SMC9000: Memory allocation timed out, resetting MMU.\n");
|
|
_outw(MC_RESET, nic->ioaddr + MMU_CMD);
|
|
}
|
|
}
|
|
|
|
/* If I get here, I _know_ there is a packet slot waiting for me */
|
|
packet_no = inb(nic->ioaddr + PNR_ARR + 1);
|
|
if (packet_no & 0x80) {
|
|
/* or isn't there? BAD CHIP! */
|
|
printf("SMC9000: Memory allocation failed. \n");
|
|
return;
|
|
}
|
|
|
|
/* we have a packet address, so tell the card to use it */
|
|
_outb(packet_no, nic->ioaddr + PNR_ARR);
|
|
|
|
/* point to the beginning of the packet */
|
|
_outw(PTR_AUTOINC, nic->ioaddr + POINTER);
|
|
|
|
#if SMC9000_DEBUG > 2
|
|
printf("Trying to xmit packet of length %hX\n", length );
|
|
#endif
|
|
|
|
/* send the packet length ( +6 for status, length and ctl byte )
|
|
* and the status word ( set to zeros ) */
|
|
_outw(0, nic->ioaddr + DATA_1 );
|
|
|
|
/* send the packet length ( +6 for status words, length, and ctl) */
|
|
_outb((length+6) & 0xFF, nic->ioaddr + DATA_1);
|
|
_outb((length+6) >> 8 , nic->ioaddr + DATA_1);
|
|
|
|
/* Write the contents of the packet */
|
|
|
|
/* The ethernet header first... */
|
|
outsw(nic->ioaddr + DATA_1, d, ETH_ALEN >> 1);
|
|
outsw(nic->ioaddr + DATA_1, nic->node_addr, ETH_ALEN >> 1);
|
|
_outw(htons(t), nic->ioaddr + DATA_1);
|
|
|
|
/* ... the data ... */
|
|
outsw(nic->ioaddr + DATA_1 , p, s >> 1);
|
|
|
|
/* ... and the last byte, if there is one. */
|
|
if ((s & 1) == 0) {
|
|
_outw(0, nic->ioaddr + DATA_1);
|
|
} else {
|
|
_outb(p[s-1], nic->ioaddr + DATA_1);
|
|
_outb(0x20, nic->ioaddr + DATA_1);
|
|
}
|
|
|
|
/* and let the chipset deal with it */
|
|
_outw(MC_ENQUEUE , nic->ioaddr + MMU_CMD);
|
|
|
|
status = 0; time_out = currticks() + 5*TICKS_PER_SEC;
|
|
do {
|
|
status = inb(nic->ioaddr + INTERRUPT);
|
|
|
|
if ((status & IM_TX_INT ) != 0) {
|
|
word tx_status;
|
|
|
|
/* ack interrupt */
|
|
_outb(IM_TX_INT, nic->ioaddr + INTERRUPT);
|
|
|
|
packet_no = inw(nic->ioaddr + FIFO_PORTS);
|
|
packet_no &= 0x7F;
|
|
|
|
/* select this as the packet to read from */
|
|
_outb( packet_no, nic->ioaddr + PNR_ARR );
|
|
|
|
/* read the first word from this packet */
|
|
_outw( PTR_AUTOINC | PTR_READ, nic->ioaddr + POINTER );
|
|
|
|
tx_status = inw( nic->ioaddr + DATA_1 );
|
|
|
|
if (0 == (tx_status & TS_SUCCESS)) {
|
|
DBG("SMC9000: TX FAIL STATUS: %hX \n", tx_status);
|
|
/* re-enable transmit */
|
|
SMC_SELECT_BANK(nic->ioaddr, 0);
|
|
_outw(inw(nic->ioaddr + TCR ) | TCR_ENABLE, nic->ioaddr + TCR );
|
|
}
|
|
|
|
/* kill the packet */
|
|
SMC_SELECT_BANK(nic->ioaddr, 2);
|
|
_outw(MC_FREEPKT, nic->ioaddr + MMU_CMD);
|
|
|
|
return;
|
|
}
|
|
}while(currticks() < time_out);
|
|
|
|
printf("SMC9000: TX timed out, resetting board\n");
|
|
smc_reset(nic->ioaddr);
|
|
return;
|
|
}
|
|
|
|
/**************************************************************************
|
|
* ETH_POLL - Wait for a frame
|
|
***************************************************************************/
|
|
static int smc9000_poll(struct nic *nic, int retrieve)
|
|
{
|
|
SMC_SELECT_BANK(nic->ioaddr, 2);
|
|
if (inw(nic->ioaddr + FIFO_PORTS) & FP_RXEMPTY)
|
|
return 0;
|
|
|
|
if ( ! retrieve ) return 1;
|
|
|
|
/* start reading from the start of the packet */
|
|
_outw(PTR_READ | PTR_RCV | PTR_AUTOINC, nic->ioaddr + POINTER);
|
|
|
|
/* First read the status and check that we're ok */
|
|
if (!(inw(nic->ioaddr + DATA_1) & RS_ERRORS)) {
|
|
/* Next: read the packet length and mask off the top bits */
|
|
nic->packetlen = (inw(nic->ioaddr + DATA_1) & 0x07ff);
|
|
|
|
/* the packet length includes the 3 extra words */
|
|
nic->packetlen -= 6;
|
|
#if SMC9000_DEBUG > 2
|
|
printf(" Reading %d words (and %d byte(s))\n",
|
|
(nic->packetlen >> 1), nic->packetlen & 1);
|
|
#endif
|
|
/* read the packet (and the last "extra" word) */
|
|
insw(nic->ioaddr + DATA_1, nic->packet, (nic->packetlen+2) >> 1);
|
|
/* is there an odd last byte ? */
|
|
if (nic->packet[nic->packetlen+1] & 0x20)
|
|
nic->packetlen++;
|
|
|
|
/* error or good, tell the card to get rid of this packet */
|
|
_outw(MC_RELEASE, nic->ioaddr + MMU_CMD);
|
|
return 1;
|
|
}
|
|
|
|
printf("SMC9000: RX error\n");
|
|
/* error or good, tell the card to get rid of this packet */
|
|
_outw(MC_RELEASE, nic->ioaddr + MMU_CMD);
|
|
return 0;
|
|
}
|
|
|
|
static void smc9000_disable ( struct nic *nic, struct isa_device *isa __unused ) {
|
|
|
|
smc_reset(nic->ioaddr);
|
|
|
|
/* no more interrupts for me */
|
|
SMC_SELECT_BANK(nic->ioaddr, 2);
|
|
_outb( 0, nic->ioaddr + INT_MASK);
|
|
|
|
/* and tell the card to stay away from that nasty outside world */
|
|
SMC_SELECT_BANK(nic->ioaddr, 0);
|
|
_outb( RCR_CLEAR, nic->ioaddr + RCR );
|
|
_outb( TCR_CLEAR, nic->ioaddr + TCR );
|
|
}
|
|
|
|
static void smc9000_irq(struct nic *nic __unused, irq_action_t action __unused)
|
|
{
|
|
switch ( action ) {
|
|
case DISABLE :
|
|
break;
|
|
case ENABLE :
|
|
break;
|
|
case FORCE :
|
|
break;
|
|
}
|
|
}
|
|
|
|
static struct nic_operations smc9000_operations = {
|
|
.connect = dummy_connect,
|
|
.poll = smc9000_poll,
|
|
.transmit = smc9000_transmit,
|
|
.irq = smc9000_irq,
|
|
|
|
};
|
|
|
|
/**************************************************************************
|
|
* ETH_PROBE - Look for an adapter
|
|
***************************************************************************/
|
|
|
|
static int smc9000_probe ( struct nic *nic, struct isa_device *isa ) {
|
|
|
|
unsigned short revision;
|
|
int memory;
|
|
int media;
|
|
const char * version_string;
|
|
const char * if_string;
|
|
int i;
|
|
|
|
nic->irqno = 0;
|
|
isa_fill_nic ( nic, isa );
|
|
nic->ioaddr = isa->ioaddr;
|
|
|
|
/*
|
|
* Get the MAC address ( bank 1, regs 4 - 9 )
|
|
*/
|
|
SMC_SELECT_BANK(nic->ioaddr, 1);
|
|
for ( i = 0; i < 6; i += 2 ) {
|
|
word address;
|
|
|
|
address = inw(nic->ioaddr + ADDR0 + i);
|
|
nic->node_addr[i+1] = address >> 8;
|
|
nic->node_addr[i] = address & 0xFF;
|
|
}
|
|
|
|
/* get the memory information */
|
|
SMC_SELECT_BANK(nic->ioaddr, 0);
|
|
memory = ( inw(nic->ioaddr + MCR) >> 9 ) & 0x7; /* multiplier */
|
|
memory *= 256 * (inw(nic->ioaddr + MIR) & 0xFF);
|
|
|
|
/*
|
|
* Now, I want to find out more about the chip. This is sort of
|
|
* redundant, but it's cleaner to have it in both, rather than having
|
|
* one VERY long probe procedure.
|
|
*/
|
|
SMC_SELECT_BANK(nic->ioaddr, 3);
|
|
revision = inw(nic->ioaddr + REVISION);
|
|
version_string = chip_ids[(revision >> 4) & 0xF];
|
|
|
|
if (((revision & 0xF0) >> 4 == CHIP_9196) &&
|
|
((revision & 0x0F) >= REV_9196)) {
|
|
/* This is a 91c96. 'c96 has the same chip id as 'c94 (4) but
|
|
* a revision starting at 6 */
|
|
version_string = smc91c96_id;
|
|
}
|
|
|
|
if ( !version_string ) {
|
|
/* I shouldn't get here because this call was done before.... */
|
|
return 0;
|
|
}
|
|
|
|
/* is it using AUI or 10BaseT ? */
|
|
SMC_SELECT_BANK(nic->ioaddr, 1);
|
|
if (inw(nic->ioaddr + CONFIG) & CFG_AUI_SELECT)
|
|
media = 2;
|
|
else
|
|
media = 1;
|
|
|
|
if_string = interfaces[media - 1];
|
|
|
|
/* now, reset the chip, and put it into a known state */
|
|
smc_reset(nic->ioaddr);
|
|
|
|
printf("SMC9000 %s\n", smc9000_version);
|
|
DBG("Copyright (C) 1998 Daniel Engstr\x94m\n");
|
|
DBG("Copyright (C) 1996 Eric Stahlman\n");
|
|
|
|
printf("%s rev:%d I/O port:%hX Interface:%s RAM:%d bytes \n",
|
|
version_string, revision & 0xF,
|
|
nic->ioaddr, if_string, memory );
|
|
|
|
DBG ( "Ethernet MAC address: %s\n", eth_ntoa ( nic->node_addr ) );
|
|
|
|
SMC_SELECT_BANK(nic->ioaddr, 0);
|
|
|
|
/* see the header file for options in TCR/RCR NORMAL*/
|
|
_outw(TCR_NORMAL, nic->ioaddr + TCR);
|
|
_outw(RCR_NORMAL, nic->ioaddr + RCR);
|
|
|
|
/* Select which interface to use */
|
|
SMC_SELECT_BANK(nic->ioaddr, 1);
|
|
if ( media == 1 ) {
|
|
_outw( inw( nic->ioaddr + CONFIG ) & ~CFG_AUI_SELECT,
|
|
nic->ioaddr + CONFIG );
|
|
}
|
|
else if ( media == 2 ) {
|
|
_outw( inw( nic->ioaddr + CONFIG ) | CFG_AUI_SELECT,
|
|
nic->ioaddr + CONFIG );
|
|
}
|
|
|
|
smc_phy_configure(nic->ioaddr);
|
|
|
|
nic->nic_op = &smc9000_operations;
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* The SMC9000 can be at any of the following port addresses. To
|
|
* change for a slightly different card, you can add it to the array.
|
|
*
|
|
*/
|
|
static isa_probe_addr_t smc9000_probe_addrs[] = {
|
|
0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0,
|
|
0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0,
|
|
};
|
|
|
|
ISA_DRIVER ( smc9000_driver, smc9000_probe_addrs, smc9000_probe_addr,
|
|
GENERIC_ISAPNP_VENDOR, 0x8228 );
|
|
|
|
DRIVER ( "SMC9000", nic_driver, isa_driver, smc9000_driver,
|
|
smc9000_probe, smc9000_disable );
|
|
|
|
ISA_ROM ( "smc9000", "SMC9000" );
|
|
|
|
/*
|
|
* Local variables:
|
|
* c-basic-offset: 3
|
|
* End:
|
|
*/
|