547 lines
12 KiB
C
547 lines
12 KiB
C
#ifndef __mt25218_h__
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#define __mt25218_h__
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#include "MT25218_PRM.h"
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#include "ib_mad.h"
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#define TAVOR_DEVICE_ID 0x5a44
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#define TAVOR_BRIDGE_DEVICE_ID 0x5a46
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#define ARTAVOR_DEVICE_ID 0x6278
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#define MEMFREE_RESET_OFFSET 0xF0010
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#define INVALID_WQE_LKEY 0x00000100
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/*
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* memfree specific command
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*
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*/
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#define MEMFREE_CMD_QUERY_ADAPTER 0x006
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#define MEMFREE_CMD_WRITE_MGM 0x026
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#define MEMFREE_CMD_MOD_STAT_CFG 0x034
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#define MEMFREE_CMD_QUERY_FW 0x004
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#define MEMFREE_CMD_ENABLE_LAM 0xff8
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#define MEMFREE_CMD_MAP_FA 0xfff
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#define MEMFREE_CMD_UNMAP_FA 0xffe
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#define MEMFREE_CMD_RUN_FW 0xff6
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#define MEMFREE_CMD_SET_ICM_SIZE 0xffd
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#define MEMFREE_CMD_MAP_ICM_AUX 0xffc
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#define MEMFREE_CMD_MAP_ICM 0xffa
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#define MEMFREE_CMD_QUERY_DEV_LIM 0x003
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/*
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* Tavor specific event types
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* Only event types that are specific to Tavor
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* and are used by the driver are listed here
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*/
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#define TAVOR_IF_EV_TYPE_OVERRUN 0x0F
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/*
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* EQ doorbel commands
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*/
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#define EQ_DBELL_CMD_INC_CONS_IDX 1 /* increment Consumer_indx by one */
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#define EQ_DBELL_CMD_ARM_EQ 2 /* Request notifcation for next event (Arm EQ) */
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#define EQ_DBELL_CMD_DISARM_CQ 3 /* Disarm CQ (CQ number is specified in EQ_param) */
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#define EQ_DBELL_CMD_SET_CONS_IDX 4 /* set Consumer_indx to value of EQ_param */
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#define EQ_DBELL_CMD_ALWAYS_ARM 5 /* move EQ to Always Armed state */
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/*
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* CQ doorbel commands
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*/
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#define CQ_DBELL_CMD_INC_CONS_IDX 1
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#define CQ_DBELL_CMD_REQ_NOTIF_SOL_UNSOL 2
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#define CQ_DBELL_CMD_REQ_NOTIF_SOL 3
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#define CQ_DBELL_CMD_SET_CONS_IDX 4
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#define CQ_DBELL_CMD_REQ_NOTIF_MULT 5
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#define INPRM_BUF_SZ 4096
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#define INPRM_BUF_ALIGN 4096
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#define OUTPRM_BUF_SZ 4096
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#define OUTPRM_BUF_ALIGN 4096
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/*
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* sizes of parameter blocks used in certain
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* commands.
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* TODO: replace them with sizeof
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* operators of the appropriate structs
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*/
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#define SW2HW_MPT_IBUF_SZ MT_STRUCT_SIZE(arbelprm_mpt_st)
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#define SW2HW_EQ_IBUF_SZ MT_STRUCT_SIZE(arbelprm_eqc_st)
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#define INIT_IB_IBUF_SZ MT_STRUCT_SIZE(arbelprm_init_ib_st)
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#define SW2HW_CQ_IBUF_SZ MT_STRUCT_SIZE(arbelprm_completion_queue_context_st)
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#define QPCTX_IBUF_SZ MT_STRUCT_SIZE(arbelprm_queue_pair_ee_context_entry_st)
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#define EQN 0
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#define UAR_IDX 1
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#define QPC_OFFSET 0
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#define CQC_OFFSET (QPC_OFFSET + 0x100000)
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#define EQPC_OFFSET (CQC_OFFSET + 0x100000)
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#define EQC_OFFSET (EQPC_OFFSET + 0x100000)
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#define MC_BASE_OFFSET (EQC_OFFSET + 0x100000)
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#define MPT_BASE_OFFSET (MC_BASE_OFFSET + 0x100000)
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#define MTT_BASE_OFFSET (MPT_BASE_OFFSET + 0x100000)
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#define LOG2_QPS 7
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#define LOG2_CQS 8
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#define LOG2_EQS 6
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#define LOG2_MC_ENTRY 6 /* 8 QPs per group */
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#define LOG2_MC_GROUPS 3 /* 8 groups */
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#define LOG2_MPT_ENTRIES 5
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#define LOG2_EQ_SZ 5
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#define LOG2_CQ_SZ 5
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#define NUM_PORTS 2
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#define EQE_OWNER_OFFSET 31
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#define EQE_OWNER_VAL_HW 0x80
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#define CQE_OWNER_OFFSET 31
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#define CQE_OWNER_VAL_HW 0x80
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#define POST_RCV_OFFSET 0x18
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#define POST_SND_OFFSET 0x10
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#define CQ_DBELL_OFFSET 0x20
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#define EQ_DBELL_OFFSET 0x28
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#define CQE_ERROR_OPCODE 0xfe
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#define OWNER_HW 1
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#define OWNER_SW 0
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#define MAX_GATHER 1 /* max gather entries used in send */
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#define MAX_SCATTER 2
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#define LOG2_MADS_SND_CQ_SZ LOG2_CQ_SZ
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#define LOG2_MADS_RCV_CQ_SZ LOG2_CQ_SZ
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#define LOG2_IPOIB_SND_CQ_SZ LOG2_CQ_SZ
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#define LOG2_IPOIB_RCV_CQ_SZ LOG2_CQ_SZ
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#define NUM_MADS_SND_CQES (1<<LOG2_MADS_SND_CQ_SZ)
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#define NUM_MADS_RCV_CQES (1<<LOG2_MADS_RCV_CQ_SZ)
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#define NUM_IPOIB_SND_CQES (1<<LOG2_IPOIB_SND_CQ_SZ)
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#define NUM_IPOIB_RCV_CQES (1<<LOG2_IPOIB_RCV_CQ_SZ)
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/* work queues must be 2^n size with n=0.. */
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#define NUM_MADS_RCV_WQES (1<<1)
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#define NUM_IPOIB_RCV_WQES (1<<1)
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#if NUM_MADS_RCV_WQES > NUM_IPOIB_RCV_WQES
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#define MAX_RCV_WQES NUM_MADS_RCV_WQES
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#else
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#define MAX_RCV_WQES NUM_IPOIB_RCV_WQES
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#endif
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#define NUM_MADS_SND_WQES (1<<1)
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#define NUM_IPOIB_SND_WQES (1<<1)
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#if NUM_MADS_SND_WQES > NUM_IPOIB_SND_WQES
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#define MAX_SND_WQES NUM_MADS_SND_WQES
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#else
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#define MAX_SND_WQES NUM_IPOIB_SND_WQES
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#endif
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/* uar context indexes */
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enum {
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MADS_RCV_CQ_ARM_DB_IDX,
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MADS_SND_CQ_ARM_DB_IDX,
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IPOIB_RCV_CQ_ARM_DB_IDX,
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IPOIB_SND_CQ_ARM_DB_IDX,
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MADS_SND_QP_DB_IDX,
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IPOIB_SND_QP_DB_IDX,
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GROUP_SEP_IDX,
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START_UNMAPPED_DB_IDX,
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/* --------------------------
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unmapped doorbell records
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-------------------------- */
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END_UNMAPPED_DB_IDX = 505,
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MADS_RCV_QP_DB_IDX = 506,
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IPOIB_RCV_QP_DB_IDX = 507,
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MADS_RCV_CQ_CI_DB_IDX = 508,
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MADS_SND_CQ_CI_DB_IDX = 509,
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IPOIB_RCV_CQ_CI_DB_IDX = 510,
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IPOIB_SND_CQ_CI_DB_IDX = 511
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};
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/* uar resources types */
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enum {
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UAR_RES_INVALID = 0x0, /* Invalid (not allocated) DoorBell record */
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UAR_RES_CQ_SET_CI = 0x1, /* CQ SET_CI DoorBell record */
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UAR_RES_CQ_ARM = 0x2, /* CQ ARM DoorBell record */
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UAR_RES_SQ_DBELL = 0x3, /* Send Queue DoorBell record */
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UAR_RES_RQ_DBELL = 0x4, /* Receive Queue DoorBell record */
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UAR_RES_SRQ_DBELL = 0x5, /* Shared Receive Queue DoorBell record */
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UAR_RES_GROUP_SEP = 0x7 /* Group Separator record */
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};
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enum {
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TS_RC,
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TS_UC,
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TS_RD,
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TS_UD,
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TS_MLX
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};
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enum {
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PM_STATE_ARMED = 0,
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PM_STATE_REARM = 1,
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PM_STATE_MIGRATED = 3
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};
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enum {
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DOORBEL_RES_SQ = 3,
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DOORBEL_RES_RQ = 4,
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DOORBEL_RES_SRQ = 5
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};
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struct ib_buffers_st {
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__u8 send_mad_buf[NUM_MADS_SND_WQES][MAD_BUF_SZ];
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__u8 rcv_mad_buf[NUM_MADS_RCV_WQES][MAD_BUF_SZ + GRH_SIZE];
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__u8 ipoib_rcv_buf[NUM_IPOIB_RCV_WQES][IPOIB_RCV_BUF_SZ + GRH_SIZE];
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__u8 ipoib_rcv_grh_buf[NUM_IPOIB_RCV_WQES][IPOIB_RCV_BUF_SZ];
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__u8 send_ipoib_buf[NUM_IPOIB_SND_WQES][IPOIB_SND_BUF_SZ];
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};
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struct pcidev {
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unsigned long bar[6];
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__u32 dev_config_space[64];
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struct pci_device *dev;
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__u8 bus;
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__u8 devfn;
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};
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struct dev_pci_struct {
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struct pcidev dev;
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struct pcidev br;
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void *cr_space;
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void *uar;
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};
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struct eq_st {
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__u8 eqn;
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__u32 cons_counter;
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__u32 eq_size;
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void *ci_base_base_addr;
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struct eqe_t *eq_buf;
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};
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struct eqe_t {
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__u8 raw[MT_STRUCT_SIZE(arbelprm_event_queue_entry_st)];
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} __attribute__ ((packed));
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enum qp_state_e {
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QP_STATE_RST = 0,
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QP_STATE_INIT = 1,
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QP_STATE_RTR = 2,
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QP_STATE_RTS = 3,
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QP_STATE_SQEr = 4,
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QP_STATE_SQD = 5,
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QP_STATE_ERR = 6,
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QP_STATE_SQDING = 7,
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QP_STATE_SUSPEND = 9
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};
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struct memory_pointer_st {
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__u32 byte_count;
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__u32 lkey;
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__u32 local_addr_h;
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__u32 local_addr_l;
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} __attribute__ ((packed));
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/* receive wqe descriptor */
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struct recv_wqe_st {
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/* part referenced by hardware */
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__u8 control[MT_STRUCT_SIZE(arbelprm_wqe_segment_ctrl_recv_st)];
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struct memory_pointer_st mpointer[MAX_SCATTER];
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} __attribute__ ((packed));
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struct recv_wqe_cont_st {
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struct recv_wqe_st wqe;
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struct udqp_st *qp; /* qp this wqe is used with */
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} __attribute__ ((packed));
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#define RECV_WQE_U_ALIGN 64
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union recv_wqe_u {
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__u8 align[RECV_WQE_U_ALIGN]; /* this ensures proper alignment */
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struct recv_wqe_st wqe;
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struct recv_wqe_cont_st wqe_cont;
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} __attribute__ ((packed));
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struct send_doorbell_st {
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__u8 raw[MT_STRUCT_SIZE(arbelprm_send_doorbell_st)];
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} __attribute__ ((packed));
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struct next_control_seg_st {
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__u8 next[MT_STRUCT_SIZE(arbelprm_wqe_segment_next_st)];
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__u8 control[MT_STRUCT_SIZE(arbelprm_wqe_segment_ctrl_send_st)];
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} __attribute__ ((packed));
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struct ud_seg_st {
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__u8 av[MT_STRUCT_SIZE(arbelprm_wqe_segment_ud_st)];
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} __attribute__ ((packed));
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struct ud_send_wqe_st {
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struct next_control_seg_st next; /* 16 bytes */
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struct ud_seg_st udseg; /* 48 bytes */
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struct memory_pointer_st mpointer[MAX_GATHER]; /* 16 * MAX_GATHER bytes */
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} __attribute__ ((packed));
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struct ude_send_wqe_cont_st {
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struct ud_send_wqe_st wqe;
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struct udqp_st *qp; /* qp this wqe is used with */
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} __attribute__ ((packed));
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#define UD_SEND_WQE_U_ALIGN 128
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union ud_send_wqe_u {
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__u8 align[UD_SEND_WQE_U_ALIGN];
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struct ude_send_wqe_cont_st wqe_cont;
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} __attribute__ ((packed));
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struct address_vector_st {
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__u8 raw[MT_STRUCT_SIZE(arbelprm_ud_address_vector_st)];
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} __attribute__ ((packed));
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struct ud_av_st {
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struct address_vector_st av;
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__u32 dest_qp; /* destination qpn */
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__u32 qkey;
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__u8 next_free;
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} __attribute__ ((packed));
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union ud_av_u {
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struct ud_av_st ud_av;
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} __attribute__ ((packed));
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struct udav_st {
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union ud_av_u av_array[NUM_AVS];
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__u8 udav_next_free;
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};
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union cqe_st {
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__u8 good_cqe[MT_STRUCT_SIZE(arbelprm_completion_queue_entry_st)];
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__u8 error_cqe[MT_STRUCT_SIZE(arbelprm_completion_with_error_st)];
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} __attribute__ ((packed));
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struct qp_ee_ctx_t {
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__u8 raw[MT_STRUCT_SIZE(arbelprm_queue_pair_ee_context_entry_st)];
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} __attribute__ ((packed));
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struct qp_ee_state_tarnisition_st {
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__u32 opt_param_mask;
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__u32 r1;
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struct qp_ee_ctx_t ctx;
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__u32 r2[62];
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} __attribute__ ((packed));
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struct cq_dbell_st {
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__u8 raw[MT_STRUCT_SIZE(arbelprm_cq_cmd_doorbell_st)];
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} __attribute__ ((packed));
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struct mad_ifc_inprm_st {
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union mad_u mad;
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} __attribute__ ((packed));
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struct wqe_buf_st {
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struct ud_send_wqe_st *sndq;
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struct recv_wqe_st *rcvq;
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};
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struct mad_buffer_st {
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void *buf; /* pointer to a 256 byte buffer */
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__u8 owner; /* sw or hw ownership BUF_OWNER_SW or BUF_OWNER_HW */
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};
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struct rcv_buf_st {
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void *buf;
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__u8 busy;
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};
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struct ib_eqe_st {
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__u8 event_type;
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__u32 cqn;
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};
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struct cq_st {
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__u32 cqn;
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union cqe_st *cq_buf;
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__u32 cons_counter; /* consuner counter */
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__u8 num_cqes;
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__u32 arm_db_ctx_idx;
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void *arm_db_ctx_pointer;
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__u32 ci_db_ctx_idx;
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void *ci_db_ctx_pointer;
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};
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struct udqp_st {
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/* cq used by this QP */
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struct cq_st snd_cq;
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struct cq_st rcv_cq;
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/* QP related data */
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__u32 qpn; /* QP number */
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__u32 qkey;
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__u8 recv_wqe_cur_free;
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__u8 recv_wqe_alloc_idx;
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__u8 max_recv_wqes;
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void *rcv_bufs[MAX_RCV_WQES];
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union recv_wqe_u *rcv_wq; /* receive work queue */
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struct recv_wqe_st *last_posted_rcv_wqe;
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__u8 snd_wqe_cur_free;
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__u8 snd_wqe_alloc_idx;
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__u8 max_snd_wqes;
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void *snd_bufs[MAX_SND_WQES];
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__u16 send_buf_sz;
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__u16 rcv_buf_sz;
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union ud_send_wqe_u *snd_wq; /* send work queue */
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struct ud_send_wqe_st *last_posted_snd_wqe;
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/* pointers to uar context entries */
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void *send_uar_context;
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__u16 post_send_counter;
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void *rcv_uar_context;
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__u16 post_rcv_counter;
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__u32 snd_db_record_index;
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__u32 rcv_db_record_index;
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};
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struct device_ib_data_st {
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__u32 mkey;
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__u32 pd;
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__u8 port;
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__u32 qkey;
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struct eq_st eq;
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struct udav_st udav;
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struct udqp_st mads_qp;
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struct udqp_st ipoib_qp;
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void *clr_int_addr;
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__u32 clr_int_data;
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__u32 uar_idx;
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void *uar_context_base;
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void *error_buf_addr;
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__u32 error_buf_size;
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};
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struct query_fw_st {
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__u16 fw_rev_major;
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__u16 fw_rev_minor;
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__u16 fw_rev_subminor;
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__u32 error_buf_start_h;
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__u32 error_buf_start_l;
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__u32 error_buf_size;
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__u32 fw_pages;
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struct addr_64_st eq_ci_table;
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struct addr_64_st clear_int_addr;
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};
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struct query_adapter_st {
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__u8 intapin;
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};
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struct vpm_entry_st {
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__u32 va_h;
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__u32 va_l;
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__u32 pa_h;
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__u32 pa_l;
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__u8 log2_size;
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};
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#define MAX_VPM_PER_CALL 1
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struct map_icm_st {
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__u32 num_vpm;
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struct vpm_entry_st vpm_arr[MAX_VPM_PER_CALL];
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};
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struct init_hca_st {
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__u32 qpc_base_addr_h;
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__u32 qpc_base_addr_l;
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__u8 log_num_of_qp;
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__u32 eec_base_addr_h;
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__u32 eec_base_addr_l;
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__u8 log_num_of_ee;
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__u32 srqc_base_addr_h;
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__u32 srqc_base_addr_l;
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__u8 log_num_of_srq;
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__u32 cqc_base_addr_h;
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__u32 cqc_base_addr_l;
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__u8 log_num_of_cq;
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__u32 eqpc_base_addr_h;
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__u32 eqpc_base_addr_l;
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__u32 eeec_base_addr_h;
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__u32 eeec_base_addr_l;
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__u32 eqc_base_addr_h;
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__u32 eqc_base_addr_l;
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__u8 log_num_of_eq;
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__u32 rdb_base_addr_h;
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__u32 rdb_base_addr_l;
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__u32 mc_base_addr_h;
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__u32 mc_base_addr_l;
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__u16 log_mc_table_entry_sz;
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__u32 mc_table_hash_sz;
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__u8 log_mc_table_sz;
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__u32 mpt_base_addr_h;
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__u32 mpt_base_addr_l;
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__u8 log_mpt_sz;
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__u32 mtt_base_addr_h;
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__u32 mtt_base_addr_l;
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__u8 log_max_uars;
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};
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struct dev_lim_st {
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__u8 log2_rsvd_qps;
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__u16 qpc_entry_sz;
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__u8 log2_rsvd_srqs;
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__u16 srq_entry_sz;
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__u8 log2_rsvd_ees;
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__u16 eec_entry_sz;
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__u8 log2_rsvd_cqs;
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__u16 cqc_entry_sz;
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__u8 log2_rsvd_mtts;
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__u16 mtt_entry_sz;
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|
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__u8 log2_rsvd_mrws;
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__u16 mpt_entry_sz;
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__u8 log2_rsvd_rdbs;
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__u16 eqc_entry_sz;
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__u32 max_icm_size_l;
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|
__u32 max_icm_size_h;
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|
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__u8 uar_sz;
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__u8 num_rsvd_uars;
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|
};
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static int create_udqp(struct udqp_st *qp);
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static int destroy_udqp(struct udqp_st *qp);
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static void *get_send_wqe_buf(void *wqe, __u8 index);
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static void *get_rcv_wqe_buf(void *wqe, __u8 index);
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static struct recv_wqe_st *alloc_rcv_wqe(struct udqp_st *qp);
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static int free_wqe(void *wqe);
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static int poll_cq(void *cqh, union cqe_st *cqe_p, __u8 * num_cqes);
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static int poll_eq(struct ib_eqe_st *ib_eqe_p, __u8 * num_eqes);
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static int post_rcv_buf(struct udqp_st *qp, struct recv_wqe_st *rcv_wqe);
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static __u32 dev_get_qpn(void *qph);
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#endif /* __mt25218_h__ */
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