ad4f58d410
Replace the old via-rhine driver with a new version using the iPXE API. Includes fixes by Thomas Miletich for: - MMIO access - Link detection - RX completion in RX overflow case - Reset and EEPROM reloading - CRC stripping - Missing cpu_to_le32() calls - Missing memory barriers Signed-off-by: Adrian Jamróz <adrian.jamroz@gmail.com> Modified-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Robin Smidsrød <robin@smidsrod.no> Modified-by: Michael Brown <mcb30@ipxe.org> Tested-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
251 lines
7.4 KiB
C
251 lines
7.4 KiB
C
#ifndef _RHINE_H
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#define _RHINE_H
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/** @file
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*
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* VIA Rhine network driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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/** Rhine BAR size */
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#define RHINE_BAR_SIZE 256
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/** Default timeout */
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#define RHINE_TIMEOUT_US 10000
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/** Rhine descriptor format */
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struct rhine_descriptor {
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uint32_t des0;
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uint32_t des1;
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uint32_t buffer;
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uint32_t next;
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} __attribute__ (( packed ));
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#define RHINE_DES0_OWN (1 << 31) /*< Owned descriptor */
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#define RHINE_DES1_IC (1 << 23) /*< Generate interrupt */
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#define RHINE_TDES1_EDP (1 << 22) /*< End of packet */
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#define RHINE_TDES1_STP (1 << 21) /*< Start of packet */
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#define RHINE_TDES1_TCPCK (1 << 20) /*< HW TCP checksum */
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#define RHINE_TDES1_UDPCK (1 << 19) /*< HW UDP checksum */
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#define RHINE_TDES1_IPCK (1 << 18) /*< HW IP checksum */
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#define RHINE_TDES1_TAG (1 << 17) /*< Tagged frame */
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#define RHINE_TDES1_CRC (1 << 16) /*< No CRC */
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#define RHINE_DES1_CHAIN (1 << 15) /*< Chained descriptor */
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#define RHINE_DES1_SIZE(_x) ((_x) & 0x7ff) /*< Frame size */
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#define RHINE_DES0_GETSIZE(_x) (((_x) >> 16) & 0x7ff)
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#define RHINE_RDES0_RXOK (1 << 15)
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#define RHINE_RDES0_VIDHIT (1 << 14)
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#define RHINE_RDES0_MAR (1 << 13)
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#define RHINE_RDES0_BAR (1 << 12)
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#define RHINE_RDES0_PHY (1 << 11)
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#define RHINE_RDES0_CHN (1 << 10)
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#define RHINE_RDES0_STP (1 << 9)
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#define RHINE_RDES0_EDP (1 << 8)
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#define RHINE_RDES0_BUFF (1 << 7)
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#define RHINE_RDES0_FRAG (1 << 6)
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#define RHINE_RDES0_RUNT (1 << 5)
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#define RHINE_RDES0_LONG (1 << 4)
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#define RHINE_RDES0_FOV (1 << 3)
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#define RHINE_RDES0_FAE (1 << 2)
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#define RHINE_RDES0_CRCE (1 << 1)
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#define RHINE_RDES0_RERR (1 << 0)
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#define RHINE_TDES0_TERR (1 << 15)
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#define RHINE_TDES0_UDF (1 << 11)
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#define RHINE_TDES0_CRS (1 << 10)
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#define RHINE_TDES0_OWC (1 << 9)
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#define RHINE_TDES0_ABT (1 << 8)
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#define RHINE_TDES0_CDH (1 << 7)
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#define RHINE_TDES0_COLS (1 << 4)
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#define RHINE_TDES0_NCR(_x) ((_x) & 0xf)
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#define RHINE_RING_ALIGN 4
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/** Rhine descriptor rings sizes */
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#define RHINE_RXDESC_NUM 4
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#define RHINE_TXDESC_NUM 8
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#define RHINE_RX_MAX_LEN 1536
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/** Rhine MAC address registers */
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#define RHINE_MAC 0x00
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/** Receive control register */
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#define RHINE_RCR 0x06
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#define RHINE_RCR_FIFO_TRSH(_x) (((_x) & 0x7) << 5) /*< RX FIFO threshold */
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#define RHINE_RCR_PHYS_ACCEPT (1 << 4) /*< Accept matching PA */
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#define RHINE_RCR_BCAST_ACCEPT (1 << 3) /*< Accept broadcast */
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#define RHINE_RCR_MCAST_ACCEPT (1 << 2) /*< Accept multicast */
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#define RHINE_RCR_RUNT_ACCEPT (1 << 1) /*< Accept runt frames */
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#define RHINE_RCR_ERR_ACCEPT (1 << 0) /*< Accept erroneous frames */
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/** Transmit control register */
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#define RHINE_TCR 0x07
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#define RHINE_TCR_LOOPBACK(_x) (((_x) & 0x3) << 1) /*< Transmit loop mode */
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#define RHINE_TCR_TAGGING (1 << 0) /*< 802.1P/Q packet tagging */
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/** Command 0 register */
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#define RHINE_CR0 0x08
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#define RHINE_CR0_RXSTART (1 << 6)
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#define RHINE_CR0_TXSTART (1 << 5)
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#define RHINE_CR0_TXEN (1 << 4) /*< Transmit enable */
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#define RHINE_CR0_RXEN (1 << 3) /*< Receive enable */
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#define RHINE_CR0_STOPNIC (1 << 2) /*< Stop NIC */
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#define RHINE_CR0_STARTNIC (1 << 1) /*< Start NIC */
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/** Command 1 register */
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#define RHINE_CR1 0x09
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#define RHINE_CR1_RESET (1 << 7) /*< Software reset */
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#define RHINE_CR1_RXPOLL (1 << 6) /*< Receive poll demand */
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#define RHINE_CR1_TXPOLL (1 << 5) /*< Xmit poll demand */
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#define RHINE_CR1_AUTOPOLL (1 << 3) /*< Disable autopoll */
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#define RHINE_CR1_FDX (1 << 2) /*< Full duplex */
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#define RIHNE_CR1_ACCUNI (1 << 1) /*< Disable accept unicast */
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/** Transmit queue wake register */
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#define RHINE_TXQUEUE_WAKE 0x0a
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/** Interrupt service 0 */
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#define RHINE_ISR0 0x0c
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#define RHINE_ISR0_MIBOVFL (1 << 7)
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#define RHINE_ISR0_PCIERR (1 << 6)
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#define RHINE_ISR0_RXRINGERR (1 << 5)
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#define RHINE_ISR0_TXRINGERR (1 << 4)
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#define RHINE_ISR0_TXERR (1 << 3)
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#define RHINE_ISR0_RXERR (1 << 2)
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#define RHINE_ISR0_TXDONE (1 << 1)
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#define RHINE_ISR0_RXDONE (1 << 0)
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/** Interrupt service 1 */
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#define RHINE_ISR1 0x0d
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#define RHINE_ISR1_GPI (1 << 7)
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#define RHINE_ISR1_PORTSTATE (1 << 6)
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#define RHINE_ISR1_TXABORT (1 << 5)
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#define RHINE_ISR1_RXNOBUF (1 << 4)
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#define RHINE_ISR1_RXFIFOOVFL (1 << 3)
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#define RHINE_ISR1_RXFIFOUNFL (1 << 2)
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#define RHINE_ISR1_TXFIFOUNFL (1 << 1)
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#define RHINE_ISR1_EARLYRX (1 << 0)
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/** Interrupt enable mask register 0 */
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#define RHINE_IMR0 0x0e
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/** Interrupt enable mask register 1 */
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#define RHINE_IMR1 0x0f
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/** RX queue descriptor base address */
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#define RHINE_RXQUEUE_BASE 0x18
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/** TX queue 0 descriptor base address */
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#define RHINE_TXQUEUE_BASE 0x1c
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/** MII configuration */
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#define RHINE_MII_CFG 0x6c
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/** MII status register */
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#define RHINE_MII_SR 0x6d
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#define RHINE_MII_SR_PHYRST (1 << 7) /*< PHY reset */
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#define RHINE_MII_SR_LINKNWAY (1 << 4) /*< Link status after N-Way */
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#define RHINE_MII_SR_PHYERR (1 << 3) /*< PHY device error */
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#define RHINE_MII_SR_DUPLEX (1 << 2) /*< Duplex mode after N-Way */
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#define RHINE_MII_SR_LINKPOLL (1 << 1) /*< Link status after poll */
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#define RHINE_MII_SR_LINKSPD (1 << 0) /*< Link speed after N-Way */
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/** MII bus control 0 register */
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#define RHINE_MII_BCR0 0x6e
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/** MII bus control 1 register */
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#define RHINE_MII_BCR1 0x6f
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/** MII control register */
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#define RHINE_MII_CR 0x70
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#define RHINE_MII_CR_AUTOPOLL (1 << 7) /*< MII auto polling */
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#define RHINE_MII_CR_RDEN (1 << 6) /*< PHY read enable */
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#define RHINE_MII_CR_WREN (1 << 5) /*< PHY write enable */
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#define RHINE_MII_CR_DIRECT (1 << 4) /*< Direct programming mode */
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#define RHINE_MII_CR_MDIOOUT (1 << 3) /*< MDIO output enable */
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/** MII port address */
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#define RHINE_MII_ADDR 0x71
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#define RHINE_MII_ADDR_MSRCEN (1 << 6)
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#define RHINE_MII_ADDR_MDONE (1 << 5)
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/** MII read/write data */
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#define RHINE_MII_RDWR 0x72
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/** EERPOM control/status register */
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#define RHINE_EEPROM_CTRL 0x74
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#define RHINE_EEPROM_CTRL_STATUS (1 << 7) /*< EEPROM status */
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#define RHINE_EEPROM_CTRL_RELOAD (1 << 5) /*< EEPROM reload */
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/** Chip configuration A */
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#define RHINE_CHIPCFG_A 0x78
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/* MMIO enable. Only valid for Rhine I. Reserved on later boards */
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#define RHINE_CHIPCFG_A_MMIO (1 << 5)
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/** Chip configuration B */
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#define RHINE_CHIPCFG_B 0x79
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/** Chip configuation C */
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#define RHINE_CHIPCFG_C 0x7a
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/** Chip configuration D */
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#define RHINE_CHIPCFG_D 0x7b
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/* MMIO enable. Only valid on Rhine II and later. GPIOEN on Rhine I */
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#define RHINE_CHIPCFG_D_MMIO (1 << 7)
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#define RHINE_REVISION_OLD 0x20
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/** A VIA Rhine descriptor ring */
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struct rhine_ring {
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/** Descriptors */
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struct rhine_descriptor *desc;
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/** Producer index */
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unsigned int prod;
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/** Consumer index */
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unsigned int cons;
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/** Number of descriptors */
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unsigned int count;
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/** Register address */
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unsigned int reg;
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};
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/**
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* Initialise descriptor ring
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*
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* @v ring Descriptor ring
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* @v count Number of descriptors (must be a power of 2)
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* @v reg Register address
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*/
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static inline __attribute__ (( always_inline)) void
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rhine_init_ring ( struct rhine_ring *ring, unsigned int count,
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unsigned int reg ) {
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ring->count = count;
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ring->reg = reg;
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}
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/** A VIA Rhine network card */
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struct rhine_nic {
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/** I/O address (some PIO access is always required) */
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unsigned long ioaddr;
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/** Registers */
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void *regs;
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/** Cached value of CR1 (to avoid read-modify-write on fast path) */
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uint8_t cr1;
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/** MII interface */
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struct mii_interface mii;
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/** Transmit descriptor ring */
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struct rhine_ring tx;
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/** Receive descriptor ring */
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struct rhine_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[RHINE_RXDESC_NUM];
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};
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#endif /* _RHINE_H */
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