682 lines
17 KiB
C
682 lines
17 KiB
C
/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
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* Copyright (C) 2004 Advanced Micro Devices
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* Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
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*
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* Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
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* Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
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* Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
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* Derived from the lance driver written 1993,1994,1995 by Donald Becker.
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* Copyright 1993 United States Government as represented by the
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* Director, National Security Agency.[ pcnet32.c ]
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* Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include "etherboot.h"
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#include "nic.h"
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#include "mii.h"
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#include "pci.h"
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#include "timer.h"
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#include "string.h"
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#include "stdint.h"
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#include "amd8111e.h"
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/* driver definitions */
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#define NUM_TX_SLOTS 2
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#define NUM_RX_SLOTS 4
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#define TX_SLOTS_MASK 1
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#define RX_SLOTS_MASK 3
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#define TX_BUF_LEN 1536
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#define RX_BUF_LEN 1536
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#define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
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#define RX_PKT_LEN_MIN 60
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#define RX_PKT_LEN_MAX ETH_FRAME_LEN
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#define TX_TIMEOUT 3000
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#define TX_PROCESS_TIME 10
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#define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
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#define PHY_RW_RETRY 10
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struct amd8111e_tx_desc {
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u16 buf_len;
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u16 tx_flags;
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u16 tag_ctrl_info;
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u16 tag_ctrl_cmd;
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u32 buf_phy_addr;
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u32 reserved;
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};
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struct amd8111e_rx_desc {
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u32 reserved;
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u16 msg_len;
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u16 tag_ctrl_info;
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u16 buf_len;
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u16 rx_flags;
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u32 buf_phy_addr;
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};
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struct eth_frame {
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u8 dst_addr[ETH_ALEN];
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u8 src_addr[ETH_ALEN];
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u16 type;
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u8 data[ETH_FRAME_LEN - ETH_HLEN];
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} __attribute__((packed));
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struct amd8111e_priv {
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struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
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struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
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unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
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unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
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unsigned long tx_idx, rx_idx;
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int tx_consistent;
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char opened;
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char link;
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char speed;
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char duplex;
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int ext_phy_addr;
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u32 ext_phy_id;
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struct pci_device *pdev;
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struct nic *nic;
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void *mmio;
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};
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static struct amd8111e_priv amd8111e;
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/********************************************************
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* locale functions *
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********************************************************/
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static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
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static int amd8111e_start(struct amd8111e_priv *lp);
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static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
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#if 0
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static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
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#endif
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static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
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static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
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static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
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static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
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static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
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static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
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static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
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static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
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static void amd8111e_wait_link(struct amd8111e_priv *lp);
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static void amd8111e_poll_link(struct amd8111e_priv *lp);
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static void amd8111e_restart(struct amd8111e_priv *lp);
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/*
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* This function clears necessary the device registers.
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*/
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static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
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{
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unsigned int reg_val;
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unsigned int logic_filter[2] = {0,};
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void *mmio = lp->mmio;
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/* stop the chip */
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writel(RUN, mmio + CMD0);
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/* Clear RCV_RING_BASE_ADDR */
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writel(0, mmio + RCV_RING_BASE_ADDR0);
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/* Clear XMT_RING_BASE_ADDR */
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writel(0, mmio + XMT_RING_BASE_ADDR0);
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writel(0, mmio + XMT_RING_BASE_ADDR1);
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writel(0, mmio + XMT_RING_BASE_ADDR2);
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writel(0, mmio + XMT_RING_BASE_ADDR3);
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/* Clear CMD0 */
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writel(CMD0_CLEAR, mmio + CMD0);
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/* Clear CMD2 */
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writel(CMD2_CLEAR, mmio + CMD2);
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/* Clear CMD7 */
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writel(CMD7_CLEAR, mmio + CMD7);
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/* Clear DLY_INT_A and DLY_INT_B */
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writel(0x0, mmio + DLY_INT_A);
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writel(0x0, mmio + DLY_INT_B);
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/* Clear FLOW_CONTROL */
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writel(0x0, mmio + FLOW_CONTROL);
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/* Clear INT0 write 1 to clear register */
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reg_val = readl(mmio + INT0);
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writel(reg_val, mmio + INT0);
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/* Clear STVAL */
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writel(0x0, mmio + STVAL);
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/* Clear INTEN0 */
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writel(INTEN0_CLEAR, mmio + INTEN0);
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/* Clear LADRF */
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writel(0x0, mmio + LADRF);
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/* Set SRAM_SIZE & SRAM_BOUNDARY registers */
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writel(0x80010, mmio + SRAM_SIZE);
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/* Clear RCV_RING0_LEN */
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writel(0x0, mmio + RCV_RING_LEN0);
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/* Clear XMT_RING0/1/2/3_LEN */
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writel(0x0, mmio + XMT_RING_LEN0);
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writel(0x0, mmio + XMT_RING_LEN1);
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writel(0x0, mmio + XMT_RING_LEN2);
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writel(0x0, mmio + XMT_RING_LEN3);
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/* Clear XMT_RING_LIMIT */
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writel(0x0, mmio + XMT_RING_LIMIT);
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/* Clear MIB */
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writew(MIB_CLEAR, mmio + MIB_ADDR);
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/* Clear LARF */
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amd8111e_writeq(*(u64*)logic_filter, mmio + LADRF);
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/* SRAM_SIZE register */
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reg_val = readl(mmio + SRAM_SIZE);
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/* Set default value to CTRL1 Register */
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writel(CTRL1_DEFAULT, mmio + CTRL1);
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/* To avoid PCI posting bug */
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readl(mmio + CMD2);
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}
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/*
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* This function initializes the device registers and starts the device.
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*/
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static int amd8111e_start(struct amd8111e_priv *lp)
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{
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struct nic *nic = lp->nic;
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void *mmio = lp->mmio;
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int i, reg_val;
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/* stop the chip */
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writel(RUN, mmio + CMD0);
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/* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
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writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
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/* enable the port manager and set auto negotiation always */
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writel(VAL1 | EN_PMGR, mmio + CMD3 );
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writel(XPHYANE | XPHYRST, mmio + CTRL2);
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/* set control registers */
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reg_val = readl(mmio + CTRL1);
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reg_val &= ~XMTSP_MASK;
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writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
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/* initialize tx and rx ring base addresses */
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amd8111e_init_tx_ring(lp);
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amd8111e_init_rx_ring(lp);
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writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
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writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
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writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
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writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
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/* set default IPG to 96 */
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writew(DEFAULT_IPG, mmio + IPG);
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writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
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/* AutoPAD transmit, Retransmit on Underflow */
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writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
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/* JUMBO disabled */
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writel(JUMBO, mmio + CMD3);
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/* Setting the MAC address to the device */
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for(i = 0; i < ETH_ALEN; i++)
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writeb(nic->node_addr[i], mmio + PADR + i);
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/* set RUN bit to start the chip, interrupt not enabled */
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writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
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/* To avoid PCI posting bug */
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readl(mmio + CMD0);
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return 0;
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}
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/*
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This function will read the PHY registers.
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*/
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static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
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{
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void *mmio = lp->mmio;
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unsigned int reg_val;
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unsigned int retry = PHY_RW_RETRY;
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reg_val = readl(mmio + PHY_ACCESS);
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while (reg_val & PHY_CMD_ACTIVE)
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reg_val = readl(mmio + PHY_ACCESS);
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writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
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mmio + PHY_ACCESS);
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do {
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reg_val = readl(mmio + PHY_ACCESS);
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udelay(30); /* It takes 30 us to read/write data */
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} while (--retry && (reg_val & PHY_CMD_ACTIVE));
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if (reg_val & PHY_RD_ERR) {
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*val = 0;
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return -1;
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}
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*val = reg_val & 0xffff;
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return 0;
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}
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/*
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This function will write into PHY registers.
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*/
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#if 0
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static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
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{
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void *mmio = lp->mmio;
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unsigned int reg_val;
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unsigned int retry = PHY_RW_RETRY;
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reg_val = readl(mmio + PHY_ACCESS);
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while (reg_val & PHY_CMD_ACTIVE)
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reg_val = readl(mmio + PHY_ACCESS);
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writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
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mmio + PHY_ACCESS);
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do {
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reg_val = readl(mmio + PHY_ACCESS);
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udelay(30); /* It takes 30 us to read/write the data */
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} while (--retry && (reg_val & PHY_CMD_ACTIVE));
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if(reg_val & PHY_RD_ERR)
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return -1;
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return 0;
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}
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#endif
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static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
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{
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int i;
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lp->ext_phy_id = 0;
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lp->ext_phy_addr = 1;
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for (i = 0x1e; i >= 0; i--) {
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u32 id1, id2;
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if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
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continue;
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if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
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continue;
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lp->ext_phy_id = (id1 << 16) | id2;
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lp->ext_phy_addr = i;
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break;
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}
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if (lp->ext_phy_id)
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printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
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lp->ext_phy_id, lp->ext_phy_addr);
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else
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printf("Couldn't detect MII PHY, assuming address 0x01\n");
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}
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static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
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{
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void *mmio = lp->mmio;
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unsigned int int0;
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writel(INTREN, mmio + CMD0);
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writel(INTEN0_CLEAR, mmio + INTEN0);
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int0 = readl(mmio + INT0);
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writel(int0, mmio + INT0);
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readl(mmio + INT0);
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}
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static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
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{
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void *mmio = lp->mmio;
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writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
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writel(VAL0 | INTREN, mmio + CMD0);
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readl(mmio + CMD0);
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}
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static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
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{
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void *mmio = lp->mmio;
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writel(VAL0 | UINTCMD, mmio + CMD0);
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readl(mmio + CMD0);
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}
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static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
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{
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struct nic *nic = lp->nic;
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void *mmio = lp->mmio;
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int i;
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/* BIOS should have set mac address to PADR register,
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* so we read PADR to get it.
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*/
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for (i = 0; i < ETH_ALEN; i++)
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nic->node_addr[i] = readb(mmio + PADR + i);
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printf("Ethernet addr: %!\n", nic->node_addr);
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return 0;
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}
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static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
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{
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int i;
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lp->rx_idx = 0;
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/* Initilaizing receive descriptors */
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for (i = 0; i < NUM_RX_SLOTS; i++) {
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lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
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lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
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wmb();
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lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
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}
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return 0;
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}
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static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
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{
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int i;
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lp->tx_idx = 0;
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lp->tx_consistent = 1;
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/* Initializing transmit descriptors */
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for (i = 0; i < NUM_TX_SLOTS; i++) {
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lp->tx_ring[i].tx_flags = 0;
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lp->tx_ring[i].buf_phy_addr = 0;
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lp->tx_ring[i].buf_len = 0;
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}
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return 0;
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}
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static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
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{
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volatile u16 status;
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int retry = TX_RETRY;
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status = le16_to_cpu(lp->tx_ring[index].tx_flags);
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while (--retry && (status & OWN_BIT)) {
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mdelay(TX_PROCESS_TIME);
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status = le16_to_cpu(lp->tx_ring[index].tx_flags);
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}
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if (status & OWN_BIT) {
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printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
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amd8111e_restart(lp);
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return -1;
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}
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return 0;
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}
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static void amd8111e_wait_link(struct amd8111e_priv *lp)
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{
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unsigned int status;
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u32 reg_val;
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do {
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/* read phy to update STAT0 register */
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, ®_val);
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, ®_val);
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, ®_val);
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, ®_val);
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status = readl(lp->mmio + STAT0);
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} while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
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}
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static void amd8111e_poll_link(struct amd8111e_priv *lp)
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{
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unsigned int status, speed;
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u32 reg_val;
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if (!lp->link) {
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/* read phy to update STAT0 register */
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, ®_val);
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, ®_val);
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, ®_val);
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amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, ®_val);
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status = readl(lp->mmio + STAT0);
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if (status & LINK_STATS) {
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|
lp->link = 1;
|
|
speed = (status & SPEED_MASK) >> 7;
|
|
if (speed == PHY_SPEED_100)
|
|
lp->speed = 1;
|
|
else
|
|
lp->speed = 0;
|
|
if (status & FULL_DPLX)
|
|
lp->duplex = 1;
|
|
else
|
|
lp->duplex = 0;
|
|
|
|
printf("Link is up: %s Mbps %s duplex\n",
|
|
lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
|
|
}
|
|
} else {
|
|
status = readl(lp->mmio + STAT0);
|
|
if (!(status & LINK_STATS)) {
|
|
lp->link = 0;
|
|
printf("Link is down\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
static void amd8111e_restart(struct amd8111e_priv *lp)
|
|
{
|
|
printf("\nStarting nic...\n");
|
|
amd8111e_disable_interrupt(lp);
|
|
amd8111e_init_hw_default(lp);
|
|
amd8111e_probe_ext_phy(lp);
|
|
amd8111e_get_mac_address(lp);
|
|
amd8111e_start(lp);
|
|
|
|
printf("Waiting link up...\n");
|
|
lp->link = 0;
|
|
amd8111e_wait_link(lp);
|
|
amd8111e_poll_link(lp);
|
|
}
|
|
|
|
|
|
/********************************************************
|
|
* Interface Functions *
|
|
********************************************************/
|
|
|
|
static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
|
|
unsigned int type, unsigned int size, const char *packet)
|
|
{
|
|
struct amd8111e_priv *lp = nic->priv_data;
|
|
struct eth_frame *frame;
|
|
unsigned int index;
|
|
|
|
/* check packet size */
|
|
if (size > TX_PKT_LEN_MAX) {
|
|
printf("amd8111e_transmit(): too large packet, drop\n");
|
|
return;
|
|
}
|
|
|
|
/* get tx slot */
|
|
index = lp->tx_idx;
|
|
if (amd8111e_wait_tx_ring(lp, index))
|
|
return;
|
|
|
|
/* fill frame */
|
|
frame = (struct eth_frame *)lp->tx_buf[index];
|
|
memset(frame->data, 0, TX_PKT_LEN_MAX);
|
|
memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
|
|
memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
|
|
frame->type = htons(type);
|
|
memcpy(frame->data, packet, size);
|
|
|
|
/* start xmit */
|
|
lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
|
|
lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
|
|
wmb();
|
|
lp->tx_ring[index].tx_flags =
|
|
cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
|
|
writel(VAL1 | TDMD0, lp->mmio + CMD0);
|
|
readl(lp->mmio + CMD0);
|
|
|
|
/* update slot pointer */
|
|
lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
|
|
}
|
|
|
|
static int amd8111e_poll(struct nic *nic, int retrieve)
|
|
{
|
|
/* return true if there's an ethernet packet ready to read */
|
|
/* nic->packet should contain data on return */
|
|
/* nic->packetlen should contain length of data */
|
|
|
|
struct amd8111e_priv *lp = nic->priv_data;
|
|
u16 status, pkt_len;
|
|
unsigned int index, pkt_ok;
|
|
|
|
amd8111e_poll_link(lp);
|
|
|
|
index = lp->rx_idx;
|
|
status = le16_to_cpu(lp->rx_ring[index].rx_flags);
|
|
pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
|
|
|
|
if (status & OWN_BIT)
|
|
return 0;
|
|
|
|
if (status & ERR_BIT)
|
|
pkt_ok = 0;
|
|
else if (!(status & STP_BIT))
|
|
pkt_ok = 0;
|
|
else if (!(status & ENP_BIT))
|
|
pkt_ok = 0;
|
|
else if (pkt_len < RX_PKT_LEN_MIN)
|
|
pkt_ok = 0;
|
|
else if (pkt_len > RX_PKT_LEN_MAX)
|
|
pkt_ok = 0;
|
|
else
|
|
pkt_ok = 1;
|
|
|
|
if (pkt_ok) {
|
|
if (!retrieve)
|
|
return 1;
|
|
nic->packetlen = pkt_len;
|
|
memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
|
|
}
|
|
|
|
lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
|
|
lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
|
|
wmb();
|
|
lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
|
|
writel(VAL2 | RDMD0, lp->mmio + CMD0);
|
|
readl(lp->mmio + CMD0);
|
|
|
|
lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
|
|
return pkt_ok;
|
|
}
|
|
|
|
static void amd8111e_disable(struct nic *nic)
|
|
{
|
|
struct amd8111e_priv *lp = nic->priv_data;
|
|
|
|
/* disable interrupt */
|
|
amd8111e_disable_interrupt(lp);
|
|
|
|
/* stop chip */
|
|
amd8111e_init_hw_default(lp);
|
|
|
|
/* unmap mmio */
|
|
iounmap(lp->mmio);
|
|
|
|
/* update status */
|
|
lp->opened = 0;
|
|
}
|
|
|
|
static void amd8111e_irq(struct nic *nic, irq_action_t action)
|
|
{
|
|
struct amd8111e_priv *lp = nic->priv_data;
|
|
|
|
switch (action) {
|
|
case DISABLE:
|
|
amd8111e_disable_interrupt(lp);
|
|
break;
|
|
case ENABLE:
|
|
amd8111e_enable_interrupt(lp);
|
|
break;
|
|
case FORCE:
|
|
amd8111e_force_interrupt(lp);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static struct nic_operations amd8111e_operations = {
|
|
.connect = dummy_connect,
|
|
.poll = amd8111e_poll,
|
|
.transmit = amd8111e_transmit,
|
|
.irq = amd8111e_irq,
|
|
};
|
|
|
|
static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
|
|
{
|
|
struct amd8111e_priv *lp = &amd8111e;
|
|
unsigned long mmio_start, mmio_len;
|
|
|
|
pci_fill_nic ( nic, pdev );
|
|
|
|
mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
|
|
mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
|
|
|
|
memset(lp, 0, sizeof(*lp));
|
|
lp->pdev = pdev;
|
|
lp->nic = nic;
|
|
lp->mmio = ioremap(mmio_start, mmio_len);
|
|
lp->opened = 1;
|
|
adjust_pci_device(pdev);
|
|
|
|
nic->priv_data = lp;
|
|
|
|
amd8111e_restart(lp);
|
|
|
|
nic->nic_op = &amd8111e_operations;
|
|
return 1;
|
|
}
|
|
|
|
static struct pci_id amd8111e_nics[] = {
|
|
PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E"),
|
|
};
|
|
|
|
PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
|
|
|
|
DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
|
|
amd8111e_probe, amd8111e_disable );
|