ccb6e5c627
On an Asus Z87-K motherboard with an onboard 8168 NIC, booting into Windows 7 and then warm rebooting into iPXE results in a broken RX datapath: packets can be transmitted successfully but garbage is received. A cold reboot clears the problem. A dump of the PHY registers reveals only one difference: in the failure case the bits ADVERTISE_PAUSE_CAP and ADVERTISE_PAUSE_ASYM are cleared. Explicitly setting these bits does not fix the problem. A dump of the MAC registers reveals a few differences, of which the most obvious culprit is the undocumented bit 24 of the Receive Configuration Register (RCR), which is set in the failure case. Explicitly clearing this bit does fix the problem. Reported-by: Sebastian Nielsen <ipxe@sebbe.eu> Reported-by: Oliver Rath <rath@mglug.de> Debugged-by: Sebastian Nielsen <ipxe@sebbe.eu> Tested-by: Sebastian Nielsen <ipxe@sebbe.eu> Signed-off-by: Michael Brown <mcb30@ipxe.org>
308 lines
9.1 KiB
C
308 lines
9.1 KiB
C
#ifndef _REALTEK_H
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#define _REALTEK_H
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/** @file
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*
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* Realtek 10/100/1000 network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <ipxe/spi.h>
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#include <ipxe/spi_bit.h>
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#include <ipxe/nvo.h>
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#include <ipxe/if_ether.h>
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/** PCI memory BAR size */
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#define RTL_BAR_SIZE 0x100
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/** A packet descriptor */
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struct realtek_descriptor {
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/** Buffer size */
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uint16_t length;
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/** Flags */
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uint16_t flags;
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/** Reserved */
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uint32_t reserved;
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/** Buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Descriptor buffer size mask */
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#define RTL_DESC_SIZE_MASK 0x3fff
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/** Packet descriptor flags */
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enum realtek_descriptor_flags {
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/** Descriptor is owned by NIC */
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RTL_DESC_OWN = 0x8000,
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/** End of descriptor ring */
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RTL_DESC_EOR = 0x4000,
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/** First segment descriptor */
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RTL_DESC_FS = 0x2000,
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/** Last segment descriptor */
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RTL_DESC_LS = 0x1000,
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/** Receive error summary */
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RTL_DESC_RES = 0x0020,
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};
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/** Descriptor ring alignment */
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#define RTL_RING_ALIGN 256
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/** A legacy mode receive packet header */
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struct realtek_legacy_header {
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/** Status */
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uint16_t status;
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/** Length */
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uint16_t length;
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/** Packet data */
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uint8_t data[0];
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} __attribute__ (( packed ));
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/** Legacy mode status bits */
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enum realtek_legacy_status {
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/** Received OK */
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RTL_STAT_ROK = 0x0001,
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};
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/** ID Register 0 (6 bytes) */
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#define RTL_IDR0 0x00
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/** Multicast Register 0 (dword) */
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#define RTL_MAR0 0x08
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/** Multicast Register 4 (dword) */
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#define RTL_MAR4 0x0c
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/** Transmit Status of Descriptor N (dword, 8139 only) */
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#define RTL_TSD(n) ( 0x10 + 4 * (n) )
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#define RTL_TSD_ERTXTH(x) ( (x) << 16 ) /**< Early TX threshold */
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#define RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 )
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#define RTL_TSD_OWN 0x00002000UL /**< Ownership */
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/** Transmit Start Address of Descriptor N (dword, 8139 only) */
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#define RTL_TSAD(n) ( 0x20 + 4 * (n) )
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/** Transmit Normal Priority Descriptors (qword) */
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#define RTL_TNPDS 0x20
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/** Number of transmit descriptors
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*
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* This is a hardware limit when using legacy mode.
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*/
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#define RTL_NUM_TX_DESC 4
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/** Receive Buffer Start Address (dword, 8139 only) */
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#define RTL_RBSTART 0x30
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/** Receive buffer length */
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#define RTL_RXBUF_LEN 8192
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/** Receive buffer padding */
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#define RTL_RXBUF_PAD 2038 /* Allow space for WRAP */
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/** Receive buffer alignment */
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#define RTL_RXBUF_ALIGN 16
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/** Command Register (byte) */
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#define RTL_CR 0x37
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#define RTL_CR_RST 0x10 /**< Reset */
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#define RTL_CR_RE 0x08 /**< Receiver Enable */
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#define RTL_CR_TE 0x04 /**< Transmit Enable */
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#define RTL_CR_BUFE 0x01 /**< Receive buffer empty */
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/** Maximum time to wait for a reset, in milliseconds */
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#define RTL_RESET_MAX_WAIT_MS 100
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/** Current Address of Packet Read (word, 8139 only) */
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#define RTL_CAPR 0x38
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/** Transmit Priority Polling Register (byte, 8169 only) */
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#define RTL_TPPOLL_8169 0x38
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#define RTL_TPPOLL_NPQ 0x40 /**< Normal Priority Queue Polling */
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/** Interrupt Mask Register (word) */
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#define RTL_IMR 0x3c
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#define RTL_IRQ_PUN_LINKCHG 0x0020 /**< Packet underrun / link change */
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#define RTL_IRQ_TER 0x0008 /**< Transmit error */
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#define RTL_IRQ_TOK 0x0004 /**< Transmit OK */
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#define RTL_IRQ_RER 0x0002 /**< Receive error */
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#define RTL_IRQ_ROK 0x0001 /**< Receive OK */
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/** Interrupt Status Register (word) */
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#define RTL_ISR 0x3e
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/** Transmit (Tx) Configuration Register (dword) */
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#define RTL_TCR 0x40
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#define RTL_TCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
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#define RTL_TCR_MXDMA_MASK RTL_TCR_MXDMA ( 0x7 )
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#define RTL_TCR_MXDMA_DEFAULT RTL_TCR_MXDMA ( 0x7 /* Unlimited */ )
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/** Receive (Rx) Configuration Register (dword) */
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#define RTL_RCR 0x44
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#define RTL_RCR_STOP_WORKING 0x01000000UL /**< Here be dragons */
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#define RTL_RCR_RXFTH(x) ( (x) << 13 ) /**< Receive FIFO threshold */
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#define RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 )
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#define RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 /* Whole packet */ )
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#define RTL_RCR_RBLEN(x) ( (x) << 11 ) /**< Receive buffer length */
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#define RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 )
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#define RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 /* 8kB */ )
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#define RTL_RCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
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#define RTL_RCR_MXDMA_MASK RTL_RCR_MXDMA ( 0x7 )
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#define RTL_RCR_MXDMA_DEFAULT RTL_RCR_MXDMA ( 0x7 /* Unlimited */ )
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#define RTL_RCR_WRAP 0x00000080UL /**< Overrun receive buffer */
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#define RTL_RCR_9356SEL 0x00000040UL /**< EEPROM is a 93C56 */
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#define RTL_RCR_AB 0x00000008UL /**< Accept broadcast packets */
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#define RTL_RCR_AM 0x00000004UL /**< Accept multicast packets */
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#define RTL_RCR_APM 0x00000002UL /**< Accept physical match */
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#define RTL_RCR_AAP 0x00000001UL /**< Accept all packets */
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/** 93C46 (93C56) Command Register (byte) */
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#define RTL_9346CR 0x50
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#define RTL_9346CR_EEM(x) ( (x) << 6 ) /**< Mode select */
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#define RTL_9346CR_EEM_EEPROM RTL_9346CR_EEM ( 0x2 ) /**< EEPROM mode */
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#define RTL_9346CR_EEM_NORMAL RTL_9346CR_EEM ( 0x0 ) /**< Normal mode */
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#define RTL_9346CR_EECS 0x08 /**< Chip select */
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#define RTL_9346CR_EESK 0x04 /**< Clock */
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#define RTL_9346CR_EEDI 0x02 /**< Data in */
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#define RTL_9346CR_EEDO 0x01 /**< Data out */
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/** Word offset of ID code word within EEPROM */
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#define RTL_EEPROM_ID ( 0x00 / 2 )
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/** EEPROM code word magic value */
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#define RTL_EEPROM_ID_MAGIC 0x8129
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/** Word offset of MAC address within EEPROM */
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#define RTL_EEPROM_MAC ( 0x0e / 2 )
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/** Word offset of VPD / non-volatile options within EEPROM */
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#define RTL_EEPROM_VPD ( 0x40 / 2 )
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/** Length of VPD / non-volatile options within EEPROM */
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#define RTL_EEPROM_VPD_LEN 0x40
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/** Configuration Register 1 (byte) */
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#define RTL_CONFIG1 0x52
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#define RTL_CONFIG1_VPD 0x02 /**< Vital Product Data enabled */
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/** Media Status Register (byte, 8139 only) */
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#define RTL_MSR 0x58
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#define RTL_MSR_TXFCE 0x80 /**< TX flow control enabled */
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#define RTL_MSR_RXFCE 0x40 /**< RX flow control enabled */
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#define RTL_MSR_AUX_STATUS 0x10 /**< Aux power present */
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#define RTL_MSR_SPEED_10 0x08 /**< 10Mbps */
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#define RTL_MSR_LINKB 0x04 /**< Inverse of link status */
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#define RTL_MSR_TXPF 0x02 /**< TX pause flag */
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#define RTL_MSR_RXPF 0x01 /**< RX pause flag */
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/** PHY Access Register (dword, 8169 only) */
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#define RTL_PHYAR 0x60
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#define RTL_PHYAR_FLAG 0x80000000UL /**< Read/write flag */
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/** Construct PHY Access Register value */
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#define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
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/** Extract PHY Access Register data */
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#define RTL_PHYAR_DATA( value ) ( (value) & 0xffff )
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/** Maximum time to wait for PHY access, in microseconds */
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#define RTL_MII_MAX_WAIT_US 500
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/** PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) */
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#define RTL_PHYSTATUS 0x6c
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#define RTL_PHYSTATUS_ENTBI 0x80 /**< TBI / GMII mode */
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#define RTL_PHYSTATUS_TXFLOW 0x40 /**< TX flow control enabled */
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#define RTL_PHYSTATUS_RXFLOW 0x20 /**< RX flow control enabled */
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#define RTL_PHYSTATUS_1000MF 0x10 /**< 1000Mbps full-duplex */
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#define RTL_PHYSTATUS_100M 0x08 /**< 100Mbps */
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#define RTL_PHYSTATUS_10M 0x04 /**< 10Mbps */
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#define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */
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#define RTL_PHYSTATUS_FULLDUP 0x01 /**< Full duplex */
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/** Transmit Priority Polling Register (byte, 8139C+ only) */
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#define RTL_TPPOLL_8139CP 0xd9
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/** RX Packet Maximum Size Register (word) */
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#define RTL_RMS 0xda
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/** C+ Command Register (word) */
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#define RTL_CPCR 0xe0
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#define RTL_CPCR_DAC 0x0010 /**< PCI Dual Address Cycle Enable */
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#define RTL_CPCR_MULRW 0x0008 /**< PCI Multiple Read/Write Enable */
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#define RTL_CPCR_CPRX 0x0002 /**< C+ receive enable */
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#define RTL_CPCR_CPTX 0x0001 /**< C+ transmit enable */
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/** Receive Descriptor Start Address Register (qword) */
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#define RTL_RDSAR 0xe4
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/** Number of receive descriptors */
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#define RTL_NUM_RX_DESC 4
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/** Receive buffer length */
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#define RTL_RX_MAX_LEN \
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( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ + 4 /* extra space */ )
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/** A Realtek descriptor ring */
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struct realtek_ring {
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/** Descriptors */
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struct realtek_descriptor *desc;
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/** Producer index */
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unsigned int prod;
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/** Consumer index */
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unsigned int cons;
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/** Descriptor start address register */
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unsigned int reg;
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/** Length (in bytes) */
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size_t len;
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};
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/**
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* Initialise descriptor ring
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*
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* @v ring Descriptor ring
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* @v count Number of descriptors
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* @v reg Descriptor start address register
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*/
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static inline __attribute__ (( always_inline)) void
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realtek_init_ring ( struct realtek_ring *ring, unsigned int count,
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unsigned int reg ) {
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ring->len = ( count * sizeof ( ring->desc[0] ) );
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ring->reg = reg;
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}
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/** A Realtek network card */
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struct realtek_nic {
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/** Registers */
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void *regs;
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/** SPI bit-bashing interface */
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struct spi_bit_basher spibit;
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/** EEPROM */
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struct spi_device eeprom;
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/** Non-volatile options */
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struct nvo_block nvo;
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/** MII interface */
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struct mii_interface mii;
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/** Legacy datapath mode */
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int legacy;
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/** PHYAR and PHYSTATUS registers are present */
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int have_phy_regs;
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/** TPPoll register offset */
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unsigned int tppoll;
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/** Transmit descriptor ring */
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struct realtek_ring tx;
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/** Receive descriptor ring */
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struct realtek_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[RTL_NUM_RX_DESC];
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/** Receive buffer (legacy mode) */
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void *rx_buffer;
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/** Offset within receive buffer (legacy mode) */
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unsigned int rx_offset;
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};
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#endif /* _REALTEK_H */
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