739 lines
20 KiB
C
739 lines
20 KiB
C
/*
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* vxge-traffic.c: iPXE driver for Neterion Inc's X3100 Series 10GbE
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* PCIe I/O Virtualized Server Adapter.
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*
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* Copyright(c) 2002-2010 Neterion Inc.
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*
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* This software may be used and distributed according to the terms of
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* the GNU General Public License (GPL), incorporated herein by
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* reference. Drivers based on or derived from this code fall under
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* the GPL and must retain the authorship, copyright and license
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* notice.
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*
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*/
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FILE_LICENCE(GPL2_ONLY);
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#include <ipxe/netdevice.h>
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#include <errno.h>
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#include "vxge_traffic.h"
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#include "vxge_config.h"
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#include "vxge_main.h"
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/*
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* vxge_hw_vpath_intr_enable - Enable vpath interrupts.
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* @vpath: Virtual Path handle.
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*
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* Enable vpath interrupts. The function is to be executed the last in
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* vpath initialization sequence.
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*
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* See also: vxge_hw_vpath_intr_disable()
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*/
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enum vxge_hw_status
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vxge_hw_vpath_intr_enable(struct __vxge_hw_virtualpath *vpath)
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{
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struct vxge_hw_vpath_reg *vp_reg;
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enum vxge_hw_status status = VXGE_HW_OK;
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if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
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status = VXGE_HW_ERR_VPATH_NOT_OPEN;
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goto exit;
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}
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vp_reg = vpath->vp_reg;
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writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->general_errors_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->pci_config_errors_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->mrpcim_to_vpath_alarm_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->srpcim_to_vpath_alarm_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->vpath_ppif_int_status);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->srpcim_msg_to_vpath_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->vpath_pcipif_int_status);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->prc_alarm_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->wrdma_alarm_status);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->asic_ntwk_vp_err_reg);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->xgmac_vp_int_status);
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readq(&vp_reg->vpath_general_int_status);
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/* Mask unwanted interrupts */
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->vpath_pcipif_int_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->srpcim_msg_to_vpath_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->srpcim_to_vpath_alarm_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->mrpcim_to_vpath_alarm_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->pci_config_errors_mask);
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/* Unmask the individual interrupts */
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writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW|
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VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW|
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VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ|
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VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32),
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&vp_reg->general_errors_mask);
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__vxge_hw_pio_mem_write32_upper(
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(u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR|
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VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR|
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VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON|
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VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON|
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VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR|
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VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR), 0, 32),
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&vp_reg->kdfcctl_errors_mask);
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__vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask);
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__vxge_hw_pio_mem_write32_upper(
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(u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32),
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&vp_reg->prc_alarm_mask);
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__vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask);
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__vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask);
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if (vpath->hldev->first_vp_id != vpath->vp_id)
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->asic_ntwk_vp_err_mask);
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else
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__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn((
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VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT|
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VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK),
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0, 32), &vp_reg->asic_ntwk_vp_err_mask);
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__vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_general_int_mask);
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exit:
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return status;
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}
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/*
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* vxge_hw_vpath_intr_disable - Disable vpath interrupts.
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* @vpath: Virtual Path handle.
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*
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* Disable vpath interrupts. The function is to be executed the last in
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* vpath initialization sequence.
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*
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* See also: vxge_hw_vpath_intr_enable()
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*/
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enum vxge_hw_status
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vxge_hw_vpath_intr_disable(struct __vxge_hw_virtualpath *vpath)
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{
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enum vxge_hw_status status = VXGE_HW_OK;
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struct vxge_hw_vpath_reg __iomem *vp_reg;
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if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
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status = VXGE_HW_ERR_VPATH_NOT_OPEN;
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goto exit;
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}
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vp_reg = vpath->vp_reg;
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->vpath_general_int_mask);
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writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->general_errors_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->pci_config_errors_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->mrpcim_to_vpath_alarm_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->srpcim_to_vpath_alarm_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->vpath_ppif_int_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->srpcim_msg_to_vpath_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->vpath_pcipif_int_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->wrdma_alarm_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->prc_alarm_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->xgmac_vp_int_mask);
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__vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
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&vp_reg->asic_ntwk_vp_err_mask);
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exit:
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return status;
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}
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/**
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* vxge_hw_device_mask_all - Mask all device interrupts.
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* @hldev: HW device handle.
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*
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* Mask all device interrupts.
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*
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* See also: vxge_hw_device_unmask_all()
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*/
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void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
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{
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u64 val64;
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val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM |
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VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
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__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
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&hldev->common_reg->titan_mask_all_int);
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return;
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}
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/**
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* vxge_hw_device_unmask_all - Unmask all device interrupts.
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* @hldev: HW device handle.
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*
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* Unmask all device interrupts.
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*
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* See also: vxge_hw_device_mask_all()
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*/
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void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev)
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{
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u64 val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
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__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
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&hldev->common_reg->titan_mask_all_int);
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return;
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}
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/**
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* vxge_hw_device_intr_enable - Enable interrupts.
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* @hldev: HW device handle.
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*
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* Enable Titan interrupts. The function is to be executed the last in
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* Titan initialization sequence.
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*
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* See also: vxge_hw_device_intr_disable()
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*/
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void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev)
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{
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u64 val64;
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u32 val32;
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vxge_hw_device_mask_all(hldev);
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vxge_hw_vpath_intr_enable(&hldev->virtual_path);
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val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
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hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
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if (val64 != 0) {
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writeq(val64, &hldev->common_reg->tim_int_status0);
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writeq(~val64, &hldev->common_reg->tim_int_mask0);
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}
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val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
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hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX];
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if (val32 != 0) {
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__vxge_hw_pio_mem_write32_upper(val32,
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&hldev->common_reg->tim_int_status1);
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__vxge_hw_pio_mem_write32_upper(~val32,
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&hldev->common_reg->tim_int_mask1);
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}
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val64 = readq(&hldev->common_reg->titan_general_int_status);
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/* We have not enabled the top level interrupt yet.
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* This will be controlled from vxge_irq() entry api.
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*/
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return;
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}
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/**
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* vxge_hw_device_intr_disable - Disable Titan interrupts.
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* @hldev: HW device handle.
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*
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* Disable Titan interrupts.
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*
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* See also: vxge_hw_device_intr_enable()
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*/
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void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev)
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{
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vxge_hw_device_mask_all(hldev);
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/* mask all the tim interrupts */
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writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
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__vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32,
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&hldev->common_reg->tim_int_mask1);
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vxge_hw_vpath_intr_disable(&hldev->virtual_path);
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return;
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}
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/**
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* vxge_hw_ring_rxd_post - Post descriptor on the ring.
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* @ring: Handle to the ring object used for receive
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* @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve().
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*
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* Post descriptor on the ring.
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* Prior to posting the descriptor should be filled in accordance with
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* Host/Titan interface specification for a given service (LL, etc.).
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*/
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void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring __unused,
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struct vxge_hw_ring_rxd_1 *rxdp)
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{
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rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
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}
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/**
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* __vxge_hw_non_offload_db_post - Post non offload doorbell
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*
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* @fifo: fifohandle
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* @txdl_ptr: The starting location of the TxDL in host memory
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* @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)
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*
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* This function posts a non-offload doorbell to doorbell FIFO
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*
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*/
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static void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo,
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u64 txdl_ptr, u32 num_txds)
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{
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writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) |
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VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds),
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&fifo->nofl_db->control_0);
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wmb();
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writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr);
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wmb();
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}
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/**
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* vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo
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*
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* @fifo: tx channel handle
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*/
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struct vxge_hw_fifo_txd *
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vxge_hw_fifo_free_txdl_get(struct __vxge_hw_fifo *fifo)
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{
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struct vxge_hw_fifo_txd *txdp;
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txdp = fifo->txdl + fifo->sw_offset;
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if (txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER) {
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vxge_debug(VXGE_ERR, "%s:%d, error: txd(%d) owned by hw\n",
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__func__, __LINE__, fifo->sw_offset);
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return NULL;
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}
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return txdp;
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}
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/**
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* vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the
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* descriptor.
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* @fifo: Handle to the fifo object used for non offload send
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* @txdlh: Descriptor handle.
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* @iob: data buffer.
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*/
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void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo,
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struct vxge_hw_fifo_txd *txdp,
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struct io_buffer *iob)
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{
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txdp->control_0 = VXGE_HW_FIFO_TXD_GATHER_CODE(
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VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST);
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txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(iob_len(iob));
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txdp->control_1 = VXGE_HW_FIFO_TXD_INT_NUMBER(fifo->tx_intr_num);
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txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
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txdp->host_control = (intptr_t)iob;
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txdp->buffer_pointer = virt_to_bus(iob->data);
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}
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/**
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* vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
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* @fifo: Handle to the fifo object used for non offload send
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* @txdp: Tx Descriptor
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*
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* Post descriptor on the 'fifo' type channel for transmission.
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* Prior to posting the descriptor should be filled in accordance with
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* Host/Titan interface specification for a given service (LL, etc.).
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*
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*/
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void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo,
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struct vxge_hw_fifo_txd *txdp)
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{
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txdp->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER;
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__vxge_hw_non_offload_db_post(fifo, (u64) virt_to_bus(txdp), 0);
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vxge_hw_fifo_txd_offset_up(&fifo->sw_offset);
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}
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/*
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* __vxge_hw_vpath_alarm_process - Process Alarms.
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* @vpath: Virtual Path.
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* @skip_alarms: Do not clear the alarms
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*
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* Process vpath alarms.
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*
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*/
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static enum vxge_hw_status __vxge_hw_vpath_alarm_process(
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struct __vxge_hw_virtualpath *vpath)
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{
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u64 val64;
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u64 alarm_status;
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enum vxge_hw_status status = VXGE_HW_OK;
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struct __vxge_hw_device *hldev = NULL;
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struct vxge_hw_vpath_reg *vp_reg;
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hldev = vpath->hldev;
|
|
vp_reg = vpath->vp_reg;
|
|
alarm_status = readq(&vp_reg->vpath_general_int_status);
|
|
|
|
if (alarm_status == VXGE_HW_ALL_FOXES) {
|
|
|
|
vxge_debug(VXGE_ERR, "%s: %s:%d, slot freeze error\n",
|
|
hldev->ndev->name, __func__, __LINE__);
|
|
status = VXGE_HW_ERR_SLOT_FREEZE;
|
|
goto out;
|
|
}
|
|
|
|
if (alarm_status & ~(
|
|
VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
|
|
VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
|
|
VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
|
|
VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
|
|
|
|
vxge_debug(VXGE_ERR, "%s: %s:%d, Unknown vpath alarm\n",
|
|
hldev->ndev->name, __func__, __LINE__);
|
|
status = VXGE_HW_FAIL;
|
|
goto out;
|
|
}
|
|
|
|
if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
|
|
|
|
val64 = readq(&vp_reg->xgmac_vp_int_status);
|
|
|
|
if (val64 &
|
|
VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
|
|
|
|
val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
|
|
|
|
if (((val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
|
|
(!(val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
|
|
((val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
|
|
&& (!(val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
|
|
))) {
|
|
writeq(VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
|
|
&vp_reg->asic_ntwk_vp_err_mask);
|
|
|
|
netdev_link_down(hldev->ndev);
|
|
vxge_debug(VXGE_INTR, "%s: %s:%d link down\n",
|
|
hldev->ndev->name, __func__, __LINE__);
|
|
}
|
|
|
|
if (((val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
|
|
(!(val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
|
|
((val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
|
|
&& (!(val64 &
|
|
VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
|
|
))) {
|
|
writeq(VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
|
|
&vp_reg->asic_ntwk_vp_err_mask);
|
|
|
|
netdev_link_up(hldev->ndev);
|
|
vxge_debug(VXGE_INTR, "%s: %s:%d link up\n",
|
|
hldev->ndev->name, __func__, __LINE__);
|
|
}
|
|
|
|
writeq(VXGE_HW_INTR_MASK_ALL,
|
|
&vp_reg->asic_ntwk_vp_err_reg);
|
|
}
|
|
} else {
|
|
vxge_debug(VXGE_INFO, "%s: %s:%d unhandled alarm %llx\n",
|
|
hldev->ndev->name, __func__, __LINE__,
|
|
alarm_status);
|
|
}
|
|
out:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the
|
|
* condition that has caused the Tx and RX interrupt.
|
|
* @hldev: HW device.
|
|
*
|
|
* Acknowledge (that is, clear) the condition that has caused
|
|
* the Tx and Rx interrupt.
|
|
* See also: vxge_hw_device_begin_irq(),
|
|
* vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx().
|
|
*/
|
|
void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev)
|
|
{
|
|
|
|
if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
|
|
(hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
|
|
writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
|
|
hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]),
|
|
&hldev->common_reg->tim_int_status0);
|
|
}
|
|
|
|
if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
|
|
(hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
|
|
__vxge_hw_pio_mem_write32_upper(
|
|
(hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
|
|
hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]),
|
|
&hldev->common_reg->tim_int_status1);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
/**
|
|
* vxge_hw_device_begin_irq - Begin IRQ processing.
|
|
* @hldev: HW device handle.
|
|
*
|
|
* The function performs two actions, It first checks whether (shared IRQ) the
|
|
* interrupt was raised by the device. Next, it masks the device interrupts.
|
|
*
|
|
* Note:
|
|
* vxge_hw_device_begin_irq() does not flush MMIO writes through the
|
|
* bridge. Therefore, two back-to-back interrupts are potentially possible.
|
|
*
|
|
* Returns: 0, if the interrupt is not "ours" (note that in this case the
|
|
* device remain enabled).
|
|
* Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter
|
|
* status.
|
|
*/
|
|
enum vxge_hw_status
|
|
vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev)
|
|
{
|
|
u64 val64;
|
|
u64 adapter_status;
|
|
u64 vpath_mask;
|
|
enum vxge_hw_status ret = VXGE_HW_OK;
|
|
|
|
val64 = readq(&hldev->common_reg->titan_general_int_status);
|
|
|
|
if (!val64) {
|
|
ret = VXGE_HW_ERR_WRONG_IRQ;
|
|
goto exit;
|
|
}
|
|
|
|
if (val64 == VXGE_HW_ALL_FOXES) {
|
|
|
|
adapter_status = readq(&hldev->common_reg->adapter_status);
|
|
|
|
if (adapter_status == VXGE_HW_ALL_FOXES) {
|
|
|
|
vxge_debug(VXGE_ERR, "%s: %s:%d critical error "
|
|
"occurred\n", hldev->ndev->name,
|
|
__func__, __LINE__);
|
|
ret = VXGE_HW_ERR_SLOT_FREEZE;
|
|
goto exit;
|
|
}
|
|
}
|
|
|
|
vpath_mask = hldev->vpaths_deployed >>
|
|
(64 - VXGE_HW_MAX_VIRTUAL_PATHS);
|
|
if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(
|
|
vpath_mask))
|
|
vxge_hw_device_clear_tx_rx(hldev);
|
|
|
|
if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)
|
|
ret = __vxge_hw_vpath_alarm_process(&hldev->virtual_path);
|
|
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive
|
|
* descriptors posted.
|
|
* @ring: Handle to the ring object used for receive
|
|
*
|
|
* The function writes the number of qwords of rxds posted during replishment.
|
|
* Since the function is called frequently, a flush is not required to post the
|
|
* write transaction. At the very least, the previous write will be flushed
|
|
* once the subsequent write is made.
|
|
*
|
|
* Returns: None.
|
|
*/
|
|
void vxge_hw_vpath_doorbell_rx(struct __vxge_hw_ring *ring)
|
|
{
|
|
u32 rxds_qw_per_block = VXGE_HW_MAX_RXDS_PER_BLOCK_1 *
|
|
VXGE_HW_RING_RXD_QWORDS_MODE_1;
|
|
|
|
ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
|
|
|
|
ring->total_db_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
|
|
|
|
if (ring->total_db_cnt >= rxds_qw_per_block) {
|
|
/* For each block add 4 more qwords */
|
|
ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
|
|
|
|
/* Reset total count */
|
|
ring->total_db_cnt -= rxds_qw_per_block;
|
|
}
|
|
|
|
if (ring->doorbell_cnt >= ring->rxd_qword_limit) {
|
|
wmb();
|
|
writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(
|
|
ring->doorbell_cnt),
|
|
&ring->vp_reg->prc_rxd_doorbell);
|
|
ring->doorbell_cnt = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed
|
|
* descriptors and process the same.
|
|
* @ring: Handle to the ring object used for receive
|
|
*
|
|
* The function polls the Rx for the completed descriptors.
|
|
*/
|
|
#define ETH_FCS_LEN 4
|
|
enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ring)
|
|
{
|
|
struct __vxge_hw_device *hldev;
|
|
enum vxge_hw_status status = VXGE_HW_OK;
|
|
struct vxge_hw_ring_rxd_1 *rxd;
|
|
unsigned int len;
|
|
enum vxge_hw_ring_tcode tcode;
|
|
struct io_buffer *rx_iob, *iobuf = NULL;
|
|
u16 poll_count = 0;
|
|
|
|
hldev = ring->vpathh->hldev;
|
|
|
|
do {
|
|
rxd = &ring->rxdl->rxd[ring->rxd_offset];
|
|
tcode = VXGE_HW_RING_RXD_T_CODE_GET(rxd->control_0);
|
|
|
|
/* if tcode is VXGE_HW_RING_T_CODE_FRM_DROP, it is
|
|
* possible the ownership bit still set to adapter
|
|
*/
|
|
if ((rxd->control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER)
|
|
&& (tcode == VXGE_HW_RING_T_CODE_OK)) {
|
|
|
|
status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
|
|
goto err0;
|
|
}
|
|
|
|
vxge_debug(VXGE_INFO, "%s: rx frame received at offset %d\n",
|
|
hldev->ndev->name, ring->rxd_offset);
|
|
|
|
iobuf = (struct io_buffer *)(intptr_t)rxd->host_control;
|
|
|
|
if (tcode != VXGE_HW_RING_T_CODE_OK) {
|
|
netdev_rx_err(hldev->ndev, NULL, -EINVAL);
|
|
vxge_debug(VXGE_ERR, "%s:%d, rx error tcode %d\n",
|
|
__func__, __LINE__, tcode);
|
|
status = VXGE_HW_FAIL;
|
|
goto err1;
|
|
}
|
|
|
|
len = VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxd->control_1);
|
|
len -= ETH_FCS_LEN;
|
|
|
|
rx_iob = alloc_iob(len);
|
|
if (!rx_iob) {
|
|
netdev_rx_err(hldev->ndev, NULL, -ENOMEM);
|
|
vxge_debug(VXGE_ERR, "%s:%d, alloc_iob error\n",
|
|
__func__, __LINE__);
|
|
status = VXGE_HW_ERR_OUT_OF_MEMORY;
|
|
goto err1;
|
|
}
|
|
|
|
memcpy(iob_put(rx_iob, len), iobuf->data, len);
|
|
/* Add this packet to the receive queue. */
|
|
netdev_rx(hldev->ndev, rx_iob);
|
|
|
|
err1:
|
|
/* repost the rxd */
|
|
rxd->control_0 = rxd->control_1 = 0;
|
|
vxge_hw_ring_rxd_1b_set(rxd, iobuf,
|
|
VXGE_LL_MAX_FRAME_SIZE(hldev->vdev));
|
|
vxge_hw_ring_rxd_post(ring, rxd);
|
|
|
|
/* repost the qword count for doorbell */
|
|
vxge_hw_vpath_doorbell_rx(ring);
|
|
|
|
/* increment the descriptor offset */
|
|
vxge_hw_ring_rxd_offset_up(&ring->rxd_offset);
|
|
|
|
} while (++poll_count < ring->rx_poll_weight);
|
|
err0:
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process
|
|
* the same.
|
|
* @fifo: Handle to the fifo object used for non offload send
|
|
*
|
|
* The function polls the Tx for the completed descriptors and calls
|
|
* the driver via supplied completion callback.
|
|
*/
|
|
enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo)
|
|
{
|
|
enum vxge_hw_status status = VXGE_HW_OK;
|
|
struct vxge_hw_fifo_txd *txdp;
|
|
|
|
txdp = fifo->txdl + fifo->hw_offset;
|
|
if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)
|
|
&& (txdp->host_control)) {
|
|
|
|
vxge_xmit_compl(fifo, txdp,
|
|
VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0));
|
|
|
|
vxge_hw_fifo_txd_offset_up(&fifo->hw_offset);
|
|
}
|
|
|
|
return status;
|
|
}
|