409 lines
12 KiB
C
409 lines
12 KiB
C
/* virtio-pci.c - pci interface for virtio interface
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*
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* (c) Copyright 2008 Bull S.A.S.
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*
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* Author: Laurent Vivier <Laurent.Vivier@bull.net>
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*
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* some parts from Linux Virtio PCI driver
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*
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* Copyright IBM Corp. 2007
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* Authors: Anthony Liguori <aliguori@us.ibm.com>
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*
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*/
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#include "errno.h"
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#include "byteswap.h"
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#include "etherboot.h"
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#include "ipxe/io.h"
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#include "ipxe/iomap.h"
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#include "ipxe/pci.h"
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#include "ipxe/reboot.h"
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#include "ipxe/virtio-pci.h"
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#include "ipxe/virtio-ring.h"
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int vp_find_vq(unsigned int ioaddr, int queue_index,
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struct vring_virtqueue *vq)
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{
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struct vring * vr = &vq->vring;
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u16 num;
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/* select the queue */
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outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_SEL);
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/* check if the queue is available */
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num = inw(ioaddr + VIRTIO_PCI_QUEUE_NUM);
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if (!num) {
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DBG("VIRTIO-PCI ERROR: queue size is 0\n");
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return -1;
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}
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if (num > MAX_QUEUE_NUM) {
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DBG("VIRTIO-PCI ERROR: queue size %d > %d\n", num, MAX_QUEUE_NUM);
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return -1;
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}
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/* check if the queue is already active */
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if (inl(ioaddr + VIRTIO_PCI_QUEUE_PFN)) {
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DBG("VIRTIO-PCI ERROR: queue already active\n");
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return -1;
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}
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vq->queue_index = queue_index;
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/* initialize the queue */
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vring_init(vr, num, (unsigned char*)&vq->queue);
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/* activate the queue
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*
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* NOTE: vr->desc is initialized by vring_init()
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*/
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outl((unsigned long)virt_to_phys(vr->desc) >> PAGE_SHIFT,
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ioaddr + VIRTIO_PCI_QUEUE_PFN);
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return num;
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}
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#define CFG_POS(vdev, field) \
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(vdev->cfg_cap_pos + offsetof(struct virtio_pci_cfg_cap, field))
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static void prep_pci_cfg_cap(struct virtio_pci_modern_device *vdev,
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struct virtio_pci_region *region,
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size_t offset, u32 length)
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{
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pci_write_config_byte(vdev->pci, CFG_POS(vdev, cap.bar), region->bar);
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pci_write_config_dword(vdev->pci, CFG_POS(vdev, cap.length), length);
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pci_write_config_dword(vdev->pci, CFG_POS(vdev, cap.offset),
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(intptr_t)(region->base + offset));
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}
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void vpm_iowrite8(struct virtio_pci_modern_device *vdev,
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struct virtio_pci_region *region, u8 data, size_t offset)
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{
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switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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case VIRTIO_PCI_REGION_MEMORY:
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writeb(data, region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PORT:
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outb(data, region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PCI_CONFIG:
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prep_pci_cfg_cap(vdev, region, offset, 1);
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pci_write_config_byte(vdev->pci, CFG_POS(vdev, pci_cfg_data), data);
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break;
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default:
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assert(0);
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break;
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}
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}
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void vpm_iowrite16(struct virtio_pci_modern_device *vdev,
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struct virtio_pci_region *region, u16 data, size_t offset)
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{
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data = cpu_to_le16(data);
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switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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case VIRTIO_PCI_REGION_MEMORY:
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writew(data, region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PORT:
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outw(data, region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PCI_CONFIG:
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prep_pci_cfg_cap(vdev, region, offset, 2);
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pci_write_config_word(vdev->pci, CFG_POS(vdev, pci_cfg_data), data);
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break;
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default:
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assert(0);
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break;
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}
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}
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void vpm_iowrite32(struct virtio_pci_modern_device *vdev,
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struct virtio_pci_region *region, u32 data, size_t offset)
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{
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data = cpu_to_le32(data);
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switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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case VIRTIO_PCI_REGION_MEMORY:
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writel(data, region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PORT:
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outl(data, region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PCI_CONFIG:
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prep_pci_cfg_cap(vdev, region, offset, 4);
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pci_write_config_dword(vdev->pci, CFG_POS(vdev, pci_cfg_data), data);
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break;
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default:
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assert(0);
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break;
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}
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}
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u8 vpm_ioread8(struct virtio_pci_modern_device *vdev,
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struct virtio_pci_region *region, size_t offset)
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{
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uint8_t data;
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switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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case VIRTIO_PCI_REGION_MEMORY:
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data = readb(region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PORT:
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data = inb(region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PCI_CONFIG:
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prep_pci_cfg_cap(vdev, region, offset, 1);
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pci_read_config_byte(vdev->pci, CFG_POS(vdev, pci_cfg_data), &data);
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break;
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default:
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assert(0);
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data = 0;
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break;
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}
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return data;
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}
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u16 vpm_ioread16(struct virtio_pci_modern_device *vdev,
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struct virtio_pci_region *region, size_t offset)
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{
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uint16_t data;
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switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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case VIRTIO_PCI_REGION_MEMORY:
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data = readw(region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PORT:
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data = inw(region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PCI_CONFIG:
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prep_pci_cfg_cap(vdev, region, offset, 2);
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pci_read_config_word(vdev->pci, CFG_POS(vdev, pci_cfg_data), &data);
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break;
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default:
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assert(0);
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data = 0;
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break;
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}
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return le16_to_cpu(data);
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}
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u32 vpm_ioread32(struct virtio_pci_modern_device *vdev,
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struct virtio_pci_region *region, size_t offset)
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{
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uint32_t data;
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switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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case VIRTIO_PCI_REGION_MEMORY:
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data = readw(region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PORT:
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data = inw(region->base + offset);
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break;
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case VIRTIO_PCI_REGION_PCI_CONFIG:
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prep_pci_cfg_cap(vdev, region, offset, 4);
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pci_read_config_dword(vdev->pci, CFG_POS(vdev, pci_cfg_data), &data);
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break;
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default:
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assert(0);
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data = 0;
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break;
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}
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return le32_to_cpu(data);
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}
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int virtio_pci_find_capability(struct pci_device *pci, uint8_t cfg_type)
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{
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int pos;
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uint8_t type, bar;
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for (pos = pci_find_capability(pci, PCI_CAP_ID_VNDR);
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pos > 0;
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pos = pci_find_next_capability(pci, pos, PCI_CAP_ID_VNDR)) {
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pci_read_config_byte(pci, pos + offsetof(struct virtio_pci_cap,
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cfg_type), &type);
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pci_read_config_byte(pci, pos + offsetof(struct virtio_pci_cap,
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bar), &bar);
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/* Ignore structures with reserved BAR values */
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if (bar > 0x5) {
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continue;
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}
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if (type == cfg_type) {
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return pos;
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}
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}
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return 0;
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}
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int virtio_pci_map_capability(struct pci_device *pci, int cap, size_t minlen,
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u32 align, u32 start, u32 size,
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struct virtio_pci_region *region)
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{
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u8 bar;
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u32 offset, length, base_raw;
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unsigned long base;
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pci_read_config_byte(pci, cap + offsetof(struct virtio_pci_cap, bar), &bar);
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pci_read_config_dword(pci, cap + offsetof(struct virtio_pci_cap, offset),
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&offset);
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pci_read_config_dword(pci, cap + offsetof(struct virtio_pci_cap, length),
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&length);
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if (length <= start) {
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DBG("VIRTIO-PCI bad capability len %d (>%d expected)\n", length, start);
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return -EINVAL;
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}
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if (length - start < minlen) {
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DBG("VIRTIO-PCI bad capability len %d (>=%zd expected)\n", length, minlen);
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return -EINVAL;
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}
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length -= start;
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if (start + offset < offset) {
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DBG("VIRTIO-PCI map wrap-around %d+%d\n", start, offset);
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return -EINVAL;
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}
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offset += start;
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if (offset & (align - 1)) {
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DBG("VIRTIO-PCI offset %d not aligned to %d\n", offset, align);
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return -EINVAL;
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}
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if (length > size) {
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length = size;
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}
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if (minlen + offset < minlen ||
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minlen + offset > pci_bar_size(pci, PCI_BASE_ADDRESS(bar))) {
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DBG("VIRTIO-PCI map virtio %zd@%d out of range on bar %i length %ld\n",
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minlen, offset,
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bar, pci_bar_size(pci, PCI_BASE_ADDRESS(bar)));
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return -EINVAL;
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}
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region->base = NULL;
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region->length = length;
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region->bar = bar;
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base = pci_bar_start(pci, PCI_BASE_ADDRESS(bar));
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if (base) {
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pci_read_config_dword(pci, PCI_BASE_ADDRESS(bar), &base_raw);
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if (base_raw & PCI_BASE_ADDRESS_SPACE_IO) {
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/* Region accessed using port I/O */
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region->base = (void *)(base + offset);
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region->flags = VIRTIO_PCI_REGION_PORT;
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} else {
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/* Region mapped into memory space */
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region->base = ioremap(base + offset, length);
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region->flags = VIRTIO_PCI_REGION_MEMORY;
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}
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}
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if (!region->base) {
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/* Region accessed via PCI config space window */
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region->base = (void *)(intptr_t)offset;
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region->flags = VIRTIO_PCI_REGION_PCI_CONFIG;
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}
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return 0;
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}
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void virtio_pci_unmap_capability(struct virtio_pci_region *region)
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{
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unsigned region_type = region->flags & VIRTIO_PCI_REGION_TYPE_MASK;
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if (region_type == VIRTIO_PCI_REGION_MEMORY) {
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iounmap(region->base);
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}
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}
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void vpm_notify(struct virtio_pci_modern_device *vdev,
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struct vring_virtqueue *vq)
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{
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vpm_iowrite16(vdev, &vq->notification, (u16)vq->queue_index, 0);
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}
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int vpm_find_vqs(struct virtio_pci_modern_device *vdev,
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unsigned nvqs, struct vring_virtqueue *vqs)
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{
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unsigned i;
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struct vring_virtqueue *vq;
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u16 size, off;
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u32 notify_offset_multiplier;
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int err;
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if (nvqs > vpm_ioread16(vdev, &vdev->common, COMMON_OFFSET(num_queues))) {
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return -ENOENT;
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}
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/* Read notify_off_multiplier from config space. */
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pci_read_config_dword(vdev->pci,
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vdev->notify_cap_pos + offsetof(struct virtio_pci_notify_cap,
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notify_off_multiplier),
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¬ify_offset_multiplier);
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for (i = 0; i < nvqs; i++) {
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/* Select the queue we're interested in */
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vpm_iowrite16(vdev, &vdev->common, (u16)i, COMMON_OFFSET(queue_select));
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/* Check if queue is either not available or already active. */
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size = vpm_ioread16(vdev, &vdev->common, COMMON_OFFSET(queue_size));
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/* QEMU has a bug where queues don't revert to inactive on device
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* reset. Skip checking the queue_enable field until it is fixed.
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*/
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if (!size /*|| vpm_ioread16(vdev, &vdev->common.queue_enable)*/)
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return -ENOENT;
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if (size & (size - 1)) {
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DBG("VIRTIO-PCI %p: bad queue size %d", vdev, size);
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return -EINVAL;
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}
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if (size > MAX_QUEUE_NUM) {
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/* iPXE networking tends to be not perf critical so there's no
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* need to accept large queue sizes.
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*/
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size = MAX_QUEUE_NUM;
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}
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vq = &vqs[i];
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vq->queue_index = i;
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/* get offset of notification word for this vq */
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off = vpm_ioread16(vdev, &vdev->common, COMMON_OFFSET(queue_notify_off));
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vring_init(&vq->vring, size, (unsigned char *)vq->queue);
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/* activate the queue */
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vpm_iowrite16(vdev, &vdev->common, size, COMMON_OFFSET(queue_size));
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vpm_iowrite64(vdev, &vdev->common, virt_to_phys(vq->vring.desc),
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COMMON_OFFSET(queue_desc_lo),
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COMMON_OFFSET(queue_desc_hi));
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vpm_iowrite64(vdev, &vdev->common, virt_to_phys(vq->vring.avail),
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COMMON_OFFSET(queue_avail_lo),
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COMMON_OFFSET(queue_avail_hi));
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vpm_iowrite64(vdev, &vdev->common, virt_to_phys(vq->vring.used),
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COMMON_OFFSET(queue_used_lo),
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COMMON_OFFSET(queue_used_hi));
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err = virtio_pci_map_capability(vdev->pci,
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vdev->notify_cap_pos, 2, 2,
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off * notify_offset_multiplier, 2,
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&vq->notification);
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if (err) {
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return err;
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}
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}
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/* Select and activate all queues. Has to be done last: once we do
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* this, there's no way to go back except reset.
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*/
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for (i = 0; i < nvqs; i++) {
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vq = &vqs[i];
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vpm_iowrite16(vdev, &vdev->common, (u16)vq->queue_index,
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COMMON_OFFSET(queue_select));
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vpm_iowrite16(vdev, &vdev->common, 1, COMMON_OFFSET(queue_enable));
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}
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return 0;
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}
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