601 lines
19 KiB
C
601 lines
19 KiB
C
/*
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* forcedeth.h -- Driver for NVIDIA nForce media access controllers for iPXE
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* Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* Portions of this code are taken from the Linux forcedeth driver that was
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* based on a cleanroom reimplementation which was based on reverse engineered
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* documentation written by Carl-Daniel Hailfinger and Andrew de Quincey:
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* Copyright (C) 2003,4,5 Manfred Spraul
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* Copyright (C) 2004 Andrew de Quincey (wol support)
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* Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
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* IRQ rate fixes, bigendian fixes, cleanups, verification)
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* Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
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*
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* This header is a direct copy of #define lines and structs found in the
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* above mentioned driver, modified where necessary to make them work for iPXE.
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#ifndef _FORCEDETH_H_
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#define _FORCEDETH_H_
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struct ring_desc {
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u32 buf;
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u32 flaglen;
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};
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struct ring_desc_ex {
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u32 bufhigh;
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u32 buflow;
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u32 txvlan;
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u32 flaglen;
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};
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#define DESC_VER_1 1
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#define DESC_VER_2 2
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#define DESC_VER_3 3
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#define RX_RING_SIZE 16
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#define TX_RING_SIZE 32
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#define RXTX_RING_SIZE ( ( RX_RING_SIZE ) + ( TX_RING_SIZE ) )
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#define RX_RING_MIN 128
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#define TX_RING_MIN 64
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#define RING_MAX_DESC_VER_1 1024
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#define RING_MAX_DESC_VER_2_3 16384
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#define NV_RX_ALLOC_PAD (64)
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#define NV_RX_HEADERS (64)
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#define RX_BUF_SZ ( ( ETH_FRAME_LEN ) + ( NV_RX_HEADERS ) )
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#define NV_PKTLIMIT_1 1500
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#define NV_PKTLIMIT_2 9100
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#define NV_LINK_POLL_FREQUENCY 128
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/* PHY defines */
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#define PHY_OUI_MARVELL 0x5043
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#define PHY_OUI_CICADA 0x03f1
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#define PHY_OUI_VITESSE 0x01c1
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#define PHY_OUI_REALTEK 0x0732
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#define PHY_OUI_REALTEK2 0x0020
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#define PHYID1_OUI_MASK 0x03ff
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#define PHYID1_OUI_SHFT 6
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#define PHYID2_OUI_MASK 0xfc00
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#define PHYID2_OUI_SHFT 10
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#define PHYID2_MODEL_MASK 0x03f0
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#define PHY_MODEL_REALTEK_8211 0x0110
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#define PHY_REV_MASK 0x0001
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#define PHY_REV_REALTEK_8211B 0x0000
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#define PHY_REV_REALTEK_8211C 0x0001
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#define PHY_MODEL_REALTEK_8201 0x0200
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#define PHY_MODEL_MARVELL_E3016 0x0220
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#define PHY_MARVELL_E3016_INITMASK 0x0300
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#define PHY_CICADA_INIT1 0x0f000
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#define PHY_CICADA_INIT2 0x0e00
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#define PHY_CICADA_INIT3 0x01000
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#define PHY_CICADA_INIT4 0x0200
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#define PHY_CICADA_INIT5 0x0004
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#define PHY_CICADA_INIT6 0x02000
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#define PHY_VITESSE_INIT_REG1 0x1f
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#define PHY_VITESSE_INIT_REG2 0x10
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#define PHY_VITESSE_INIT_REG3 0x11
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#define PHY_VITESSE_INIT_REG4 0x12
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#define PHY_VITESSE_INIT_MSK1 0xc
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#define PHY_VITESSE_INIT_MSK2 0x0180
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#define PHY_VITESSE_INIT1 0x52b5
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#define PHY_VITESSE_INIT2 0xaf8a
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#define PHY_VITESSE_INIT3 0x8
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#define PHY_VITESSE_INIT4 0x8f8a
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#define PHY_VITESSE_INIT5 0xaf86
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#define PHY_VITESSE_INIT6 0x8f86
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#define PHY_VITESSE_INIT7 0xaf82
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#define PHY_VITESSE_INIT8 0x0100
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#define PHY_VITESSE_INIT9 0x8f82
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#define PHY_VITESSE_INIT10 0x0
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#define PHY_REALTEK_INIT_REG1 0x1f
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#define PHY_REALTEK_INIT_REG2 0x19
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#define PHY_REALTEK_INIT_REG3 0x13
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#define PHY_REALTEK_INIT_REG4 0x14
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#define PHY_REALTEK_INIT_REG5 0x18
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#define PHY_REALTEK_INIT_REG6 0x11
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#define PHY_REALTEK_INIT_REG7 0x01
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#define PHY_REALTEK_INIT1 0x0000
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#define PHY_REALTEK_INIT2 0x8e00
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#define PHY_REALTEK_INIT3 0x0001
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#define PHY_REALTEK_INIT4 0xad17
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#define PHY_REALTEK_INIT5 0xfb54
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#define PHY_REALTEK_INIT6 0xf5c7
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#define PHY_REALTEK_INIT7 0x1000
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#define PHY_REALTEK_INIT8 0x0003
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#define PHY_REALTEK_INIT9 0x0008
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#define PHY_REALTEK_INIT10 0x0005
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#define PHY_REALTEK_INIT11 0x0200
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#define PHY_REALTEK_INIT_MSK1 0x0003
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#define PHY_GIGABIT 0x0100
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#define PHY_TIMEOUT 0x1
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#define PHY_ERROR 0x2
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#define PHY_100 0x1
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#define PHY_1000 0x2
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#define PHY_HALF 0x100
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#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
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#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
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#define NV_PAUSEFRAME_RX_ENABLE 0x0004
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#define NV_PAUSEFRAME_TX_ENABLE 0x0008
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#define NV_PAUSEFRAME_RX_REQ 0x0010
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#define NV_PAUSEFRAME_TX_REQ 0x0020
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#define NV_PAUSEFRAME_AUTONEG 0x0040
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/* MSI/MSI-X defines */
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#define NV_MSI_X_MAX_VECTORS 8
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#define NV_MSI_X_VECTORS_MASK 0x000f
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#define NV_MSI_CAPABLE 0x0010
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#define NV_MSI_X_CAPABLE 0x0020
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#define NV_MSI_ENABLED 0x0040
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#define NV_MSI_X_ENABLED 0x0080
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#define NV_MSI_X_VECTOR_ALL 0x0
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#define NV_MSI_X_VECTOR_RX 0x0
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#define NV_MSI_X_VECTOR_TX 0x1
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#define NV_MSI_X_VECTOR_OTHER 0x2
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#define NV_MSI_PRIV_OFFSET 0x68
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#define NV_MSI_PRIV_VALUE 0xffffffff
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#define NV_MIIBUSY_DELAY 50
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#define NV_MIIPHY_DELAY 10
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#define NV_MIIPHY_DELAYMAX 10000
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/* Hardware access */
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#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
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#define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
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#define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
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#define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
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#define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
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#define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
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#define DEV_HAS_MSI 0x0000040 /* device supports MSI */
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#define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
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#define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
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#define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
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#define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */
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#define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */
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#define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
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#define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
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#define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
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#define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
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#define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
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#define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
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#define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
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#define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
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#define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
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#define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
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#define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
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#define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
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#define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
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#define FLAG_MASK_V1 0xffff0000
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#define FLAG_MASK_V2 0xffffc000
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#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
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#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
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#define NV_TX_LASTPACKET (1<<16)
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#define NV_TX_RETRYERROR (1<<19)
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#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
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#define NV_TX_FORCED_INTERRUPT (1<<24)
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#define NV_TX_DEFERRED (1<<26)
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#define NV_TX_CARRIERLOST (1<<27)
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#define NV_TX_LATECOLLISION (1<<28)
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#define NV_TX_UNDERFLOW (1<<29)
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#define NV_TX_ERROR (1<<30)
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#define NV_TX_VALID (1<<31)
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#define NV_TX2_LASTPACKET (1<<29)
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#define NV_TX2_RETRYERROR (1<<18)
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#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
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#define NV_TX2_FORCED_INTERRUPT (1<<30)
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#define NV_TX2_DEFERRED (1<<25)
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#define NV_TX2_CARRIERLOST (1<<26)
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#define NV_TX2_LATECOLLISION (1<<27)
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#define NV_TX2_UNDERFLOW (1<<28)
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/* error and valid are the same for both */
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#define NV_TX2_ERROR (1<<30)
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#define NV_TX2_VALID (1<<31)
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#define NV_TX2_TSO (1<<28)
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#define NV_TX2_TSO_SHIFT 14
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#define NV_TX2_TSO_MAX_SHIFT 14
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#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
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#define NV_TX2_CHECKSUM_L3 (1<<27)
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#define NV_TX2_CHECKSUM_L4 (1<<26)
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#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
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#define NV_RX_DESCRIPTORVALID (1<<16)
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#define NV_RX_MISSEDFRAME (1<<17)
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#define NV_RX_SUBSTRACT1 (1<<18)
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#define NV_RX_ERROR1 (1<<23)
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#define NV_RX_ERROR2 (1<<24)
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#define NV_RX_ERROR3 (1<<25)
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#define NV_RX_ERROR4 (1<<26)
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#define NV_RX_CRCERR (1<<27)
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#define NV_RX_OVERFLOW (1<<28)
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#define NV_RX_FRAMINGERR (1<<29)
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#define NV_RX_ERROR (1<<30)
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#define NV_RX_AVAIL (1<<31)
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#define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
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#define NV_RX2_CHECKSUMMASK (0x1C000000)
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#define NV_RX2_CHECKSUM_IP (0x10000000)
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#define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
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#define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
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#define NV_RX2_DESCRIPTORVALID (1<<29)
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#define NV_RX2_SUBSTRACT1 (1<<25)
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#define NV_RX2_ERROR1 (1<<18)
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#define NV_RX2_ERROR2 (1<<19)
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#define NV_RX2_ERROR3 (1<<20)
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#define NV_RX2_ERROR4 (1<<21)
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#define NV_RX2_CRCERR (1<<22)
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#define NV_RX2_OVERFLOW (1<<23)
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#define NV_RX2_FRAMINGERR (1<<24)
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/* error and avail are the same for both */
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#define NV_RX2_ERROR (1<<30)
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#define NV_RX2_AVAIL (1<<31)
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#define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
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#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
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#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
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/* Miscellaneous hardware related defines */
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#define NV_PCI_REGSZ_VER1 0x270
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#define NV_PCI_REGSZ_VER2 0x2d4
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#define NV_PCI_REGSZ_VER3 0x604
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#define NV_PCI_REGSZ_MAX 0x604
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/* various timeout delays: all in usec */
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#define NV_TXRX_RESET_DELAY 4
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#define NV_TXSTOP_DELAY1 10
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#define NV_TXSTOP_DELAY1MAX 500000
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#define NV_TXSTOP_DELAY2 100
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#define NV_RXSTOP_DELAY1 10
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#define NV_RXSTOP_DELAY1MAX 500000
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#define NV_RXSTOP_DELAY2 100
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#define NV_SETUP5_DELAY 5
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#define NV_SETUP5_DELAYMAX 50000
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#define NV_POWERUP_DELAY 5
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#define NV_POWERUP_DELAYMAX 5000
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#define NV_MIIBUSY_DELAY 50
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#define NV_MIIPHY_DELAY 10
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#define NV_MIIPHY_DELAYMAX 10000
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#define NV_MAC_RESET_DELAY 64
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#define NV_MSI_X_CAPABLE 0x0020
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#define MII_READ (-1)
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struct forcedeth_private {
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struct pci_device *pci_dev;
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struct net_device *netdev;
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void *mmio_addr;
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u32 linkspeed;
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int duplex;
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int phyaddr;
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unsigned int phy_oui;
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unsigned int phy_rev;
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unsigned int phy_model;
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u16 gigabit;
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u32 mac_in_use;
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int mgmt_version;
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int mgmt_sema;
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/* rx specific fields */
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struct ring_desc *rx_ring;
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struct io_buffer *rx_iobuf[RX_RING_SIZE];
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int rx_curr;
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/* tx specific fields */
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struct ring_desc *tx_ring;
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struct io_buffer *tx_iobuf[TX_RING_SIZE];
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int tx_fill_ctr;
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int tx_curr;
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int tx_tail;
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/* flow control */
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u32 pause_flags;
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unsigned long driver_data;
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};
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enum {
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NvRegIrqStatus = 0x000,
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#define NVREG_IRQSTAT_MIIEVENT 0x040
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#define NVREG_IRQSTAT_MASK 0x83ff
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NvRegIrqMask = 0x004,
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#define NVREG_IRQ_RX_ERROR 0x0001
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#define NVREG_IRQ_RX 0x0002
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#define NVREG_IRQ_RX_NOBUF 0x0004
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#define NVREG_IRQ_TX_ERR 0x0008
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#define NVREG_IRQ_TX_OK 0x0010
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#define NVREG_IRQ_TIMER 0x0020
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#define NVREG_IRQ_LINK 0x0040
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#define NVREG_IRQ_RX_FORCED 0x0080
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#define NVREG_IRQ_TX_FORCED 0x0100
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#define NVREG_IRQ_RECOVER_ERROR 0x8200
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#define NVREG_IRQMASK_THROUGHPUT 0x00df
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#define NVREG_IRQMASK_CPU 0x0060
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#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
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#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
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#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
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NvRegUnknownSetupReg6 = 0x008,
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#define NVREG_UNKSETUP6_VAL 3
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/*
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* NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
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* NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
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*/
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NvRegPollingInterval = 0x00c,
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#define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
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#define NVREG_POLL_DEFAULT_CPU 13
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NvRegMSIMap0 = 0x020,
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NvRegMSIMap1 = 0x024,
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NvRegMSIIrqMask = 0x030,
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#define NVREG_MSI_VECTOR_0_ENABLED 0x01
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NvRegMisc1 = 0x080,
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#define NVREG_MISC1_PAUSE_TX 0x01
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#define NVREG_MISC1_HD 0x02
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#define NVREG_MISC1_FORCE 0x3b0f3c
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NvRegMacReset = 0x34,
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#define NVREG_MAC_RESET_ASSERT 0x0F3
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NvRegTransmitterControl = 0x084,
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#define NVREG_XMITCTL_START 0x01
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#define NVREG_XMITCTL_MGMT_ST 0x40000000
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#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
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#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
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#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
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#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
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#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
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#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
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#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
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#define NVREG_XMITCTL_HOST_LOADED 0x00004000
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#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
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#define NVREG_XMITCTL_DATA_START 0x00100000
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#define NVREG_XMITCTL_DATA_READY 0x00010000
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#define NVREG_XMITCTL_DATA_ERROR 0x00020000
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NvRegTransmitterStatus = 0x088,
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#define NVREG_XMITSTAT_BUSY 0x01
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NvRegPacketFilterFlags = 0x8c,
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#define NVREG_PFF_PAUSE_RX 0x08
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#define NVREG_PFF_ALWAYS 0x7F0000
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#define NVREG_PFF_PROMISC 0x80
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#define NVREG_PFF_MYADDR 0x20
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#define NVREG_PFF_LOOPBACK 0x10
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NvRegOffloadConfig = 0x90,
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#define NVREG_OFFLOAD_HOMEPHY 0x601
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#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
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NvRegReceiverControl = 0x094,
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#define NVREG_RCVCTL_START 0x01
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#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
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NvRegReceiverStatus = 0x98,
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#define NVREG_RCVSTAT_BUSY 0x01
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NvRegSlotTime = 0x9c,
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#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
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#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
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#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
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#define NVREG_SLOTTIME_HALF 0x0000ff00
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#define NVREG_SLOTTIME_DEFAULT 0x00007f00
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#define NVREG_SLOTTIME_MASK 0x000000ff
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NvRegTxDeferral = 0xA0,
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#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
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#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
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#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
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#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
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#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
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#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
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NvRegRxDeferral = 0xA4,
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#define NVREG_RX_DEFERRAL_DEFAULT 0x16
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NvRegMacAddrA = 0xA8,
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NvRegMacAddrB = 0xAC,
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NvRegMulticastAddrA = 0xB0,
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#define NVREG_MCASTADDRA_FORCE 0x01
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NvRegMulticastAddrB = 0xB4,
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NvRegMulticastMaskA = 0xB8,
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#define NVREG_MCASTMASKA_NONE 0xffffffff
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NvRegMulticastMaskB = 0xBC,
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#define NVREG_MCASTMASKB_NONE 0xffff
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NvRegPhyInterface = 0xC0,
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#define PHY_RGMII 0x10000000
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NvRegBackOffControl = 0xC4,
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#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
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#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
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#define NVREG_BKOFFCTRL_SELECT 24
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#define NVREG_BKOFFCTRL_GEAR 12
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NvRegTxRingPhysAddr = 0x100,
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NvRegRxRingPhysAddr = 0x104,
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NvRegRingSizes = 0x108,
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#define NVREG_RINGSZ_TXSHIFT 0
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#define NVREG_RINGSZ_RXSHIFT 16
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NvRegTransmitPoll = 0x10c,
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#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
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NvRegLinkSpeed = 0x110,
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#define NVREG_LINKSPEED_FORCE 0x10000
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#define NVREG_LINKSPEED_10 1000
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#define NVREG_LINKSPEED_100 100
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#define NVREG_LINKSPEED_1000 50
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#define NVREG_LINKSPEED_MASK (0xFFF)
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NvRegUnknownSetupReg5 = 0x130,
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#define NVREG_UNKSETUP5_BIT31 (1<<31)
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NvRegTxWatermark = 0x13c,
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#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
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#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
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#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
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NvRegTxRxControl = 0x144,
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#define NVREG_TXRXCTL_KICK 0x0001
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#define NVREG_TXRXCTL_BIT1 0x0002
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#define NVREG_TXRXCTL_BIT2 0x0004
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#define NVREG_TXRXCTL_IDLE 0x0008
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#define NVREG_TXRXCTL_RESET 0x0010
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#define NVREG_TXRXCTL_RXCHECK 0x0400
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#define NVREG_TXRXCTL_DESC_1 0
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#define NVREG_TXRXCTL_DESC_2 0x002100
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#define NVREG_TXRXCTL_DESC_3 0xc02200
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#define NVREG_TXRXCTL_VLANSTRIP 0x00040
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#define NVREG_TXRXCTL_VLANINS 0x00080
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NvRegTxRingPhysAddrHigh = 0x148,
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NvRegRxRingPhysAddrHigh = 0x14C,
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NvRegTxPauseFrame = 0x170,
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#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
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#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
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#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
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#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
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NvRegTxPauseFrameLimit = 0x174,
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#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
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NvRegMIIStatus = 0x180,
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#define NVREG_MIISTAT_ERROR 0x0001
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#define NVREG_MIISTAT_LINKCHANGE 0x0008
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#define NVREG_MIISTAT_MASK_RW 0x0007
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#define NVREG_MIISTAT_MASK_ALL 0x000f
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NvRegMIIMask = 0x184,
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#define NVREG_MII_LINKCHANGE 0x0008
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NvRegAdapterControl = 0x188,
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#define NVREG_ADAPTCTL_START 0x02
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#define NVREG_ADAPTCTL_LINKUP 0x04
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#define NVREG_ADAPTCTL_PHYVALID 0x40000
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#define NVREG_ADAPTCTL_RUNNING 0x100000
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#define NVREG_ADAPTCTL_PHYSHIFT 24
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NvRegMIISpeed = 0x18c,
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#define NVREG_MIISPEED_BIT8 (1<<8)
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#define NVREG_MIIDELAY 5
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NvRegMIIControl = 0x190,
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#define NVREG_MIICTL_INUSE 0x08000
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#define NVREG_MIICTL_WRITE 0x00400
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#define NVREG_MIICTL_ADDRSHIFT 5
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NvRegMIIData = 0x194,
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NvRegTxUnicast = 0x1a0,
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NvRegTxMulticast = 0x1a4,
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NvRegTxBroadcast = 0x1a8,
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NvRegWakeUpFlags = 0x200,
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#define NVREG_WAKEUPFLAGS_VAL 0x7770
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#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
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#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
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#define NVREG_WAKEUPFLAGS_D3SHIFT 12
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#define NVREG_WAKEUPFLAGS_D2SHIFT 8
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#define NVREG_WAKEUPFLAGS_D1SHIFT 4
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#define NVREG_WAKEUPFLAGS_D0SHIFT 0
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#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
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#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
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#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
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#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
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NvRegMgmtUnitGetVersion = 0x204,
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#define NVREG_MGMTUNITGETVERSION 0x01
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NvRegMgmtUnitVersion = 0x208,
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#define NVREG_MGMTUNITVERSION 0x08
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NvRegPowerCap = 0x268,
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#define NVREG_POWERCAP_D3SUPP (1<<30)
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#define NVREG_POWERCAP_D2SUPP (1<<26)
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#define NVREG_POWERCAP_D1SUPP (1<<25)
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NvRegPowerState = 0x26c,
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#define NVREG_POWERSTATE_POWEREDUP 0x8000
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#define NVREG_POWERSTATE_VALID 0x0100
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#define NVREG_POWERSTATE_MASK 0x0003
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#define NVREG_POWERSTATE_D0 0x0000
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#define NVREG_POWERSTATE_D1 0x0001
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#define NVREG_POWERSTATE_D2 0x0002
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#define NVREG_POWERSTATE_D3 0x0003
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NvRegMgmtUnitControl = 0x278,
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#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
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NvRegTxCnt = 0x280,
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NvRegTxZeroReXmt = 0x284,
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NvRegTxOneReXmt = 0x288,
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NvRegTxManyReXmt = 0x28c,
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NvRegTxLateCol = 0x290,
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NvRegTxUnderflow = 0x294,
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NvRegTxLossCarrier = 0x298,
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NvRegTxExcessDef = 0x29c,
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NvRegTxRetryErr = 0x2a0,
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NvRegRxFrameErr = 0x2a4,
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NvRegRxExtraByte = 0x2a8,
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NvRegRxLateCol = 0x2ac,
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NvRegRxRunt = 0x2b0,
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NvRegRxFrameTooLong = 0x2b4,
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NvRegRxOverflow = 0x2b8,
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NvRegRxFCSErr = 0x2bc,
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NvRegRxFrameAlignErr = 0x2c0,
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NvRegRxLenErr = 0x2c4,
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NvRegRxUnicast = 0x2c8,
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NvRegRxMulticast = 0x2cc,
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NvRegRxBroadcast = 0x2d0,
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NvRegTxDef = 0x2d4,
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NvRegTxFrame = 0x2d8,
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NvRegRxCnt = 0x2dc,
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NvRegTxPause = 0x2e0,
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NvRegRxPause = 0x2e4,
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NvRegRxDropFrame = 0x2e8,
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NvRegVlanControl = 0x300,
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#define NVREG_VLANCONTROL_ENABLE 0x2000
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NvRegMSIXMap0 = 0x3e0,
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NvRegMSIXMap1 = 0x3e4,
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NvRegMSIXIrqStatus = 0x3f0,
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NvRegPowerState2 = 0x600,
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#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
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#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
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#define NVREG_POWERSTATE2_PHY_RESET 0x0004
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#define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
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};
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enum {
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NV_OPTIMIZATION_MODE_THROUGHPUT,
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NV_OPTIMIZATION_MODE_CPU,
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NV_OPTIMIZATION_MODE_DYNAMIC
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};
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|
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enum {
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NV_CROSSOVER_DETECTION_DISABLED,
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NV_CROSSOVER_DETECTION_ENABLED
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};
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#define NV_SETUP_RX_RING 0x01
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#define NV_SETUP_TX_RING 0x02
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#define NV_RESTART_TX 0x1
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#define NV_RESTART_RX 0x2
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#endif /* _FORCEDETH_H_ */
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