1020 lines
28 KiB
C
1020 lines
28 KiB
C
/**************************************************************************
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*
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* pcnet32.c -- Etherboot device driver for the AMD PCnet32
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* Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Portions of this code based on:
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* pcnet32.c: An AMD PCnet32 ethernet driver for linux:
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*
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* (C) 1996-1999 Thomas Bogendoerfer
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* See Linux Driver for full information
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*
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* The transmit and poll functions were written with reference to:
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* lance.c - LANCE NIC driver for Etherboot written by Ken Yap
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*
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* Linux Driver Version 1.27a, 10.02.2002
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*
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*
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* REVISION HISTORY:
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* ================
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* v1.0 08-06-2003 timlegge Initial port of Linux driver
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* v1.1 08-23-2003 timlegge Add multicast support
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* v1.2 01-17-2004 timlegge Initial driver output cleanup
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* v1.3 03-29-2004 timlegge More driver cleanup
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*
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* Indent Options: indent -kr -i8
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***************************************************************************/
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#include "etherboot.h"
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#include "nic.h"
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#include <gpxe/pci.h>
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#include <gpxe/ethernet.h>
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#include "timer.h"
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#include "mii.h"
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/* void hex_dump(const char *data, const unsigned int len); */
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/* Etherboot Specific definations */
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#define drv_version "v1.3"
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#define drv_date "03-29-2004"
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static u32 ioaddr; /* Globally used for the card's io address */
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static struct nic_operations pcnet32_operations;
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#ifdef EDEBUG
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#define dprintf(x) printf x
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#else
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#define dprintf(x)
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#endif
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/* Condensed operations for readability. */
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#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
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#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
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/* End Etherboot Specific */
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static int cards_found = 0 /* __initdata */ ;
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#ifdef REMOVE
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/* FIXME: Remove these they are probably pointless */
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/*
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* VLB I/O addresses
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*/
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static unsigned int pcnet32_portlist[] /*__initdata */ =
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{ 0x300, 0x320, 0x340, 0x360, 0 };
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static int pcnet32_debug = 1;
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static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
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static int pcnet32vlb; /* check for VLB cards ? */
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static struct net_device *pcnet32_dev;
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static int max_interrupt_work = 80;
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static int rx_copybreak = 200;
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#endif
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#define PCNET32_PORT_AUI 0x00
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#define PCNET32_PORT_10BT 0x01
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#define PCNET32_PORT_GPSI 0x02
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#define PCNET32_PORT_MII 0x03
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#define PCNET32_PORT_PORTSEL 0x03
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#define PCNET32_PORT_ASEL 0x04
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#define PCNET32_PORT_100 0x40
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#define PCNET32_PORT_FD 0x80
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#define PCNET32_DMA_MASK 0xffffffff
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/*
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* table to translate option values from tulip
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* to internal options
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*/
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static unsigned char options_mapping[] = {
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PCNET32_PORT_ASEL, /* 0 Auto-select */
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PCNET32_PORT_AUI, /* 1 BNC/AUI */
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PCNET32_PORT_AUI, /* 2 AUI/BNC */
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PCNET32_PORT_ASEL, /* 3 not supported */
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PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
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PCNET32_PORT_ASEL, /* 5 not supported */
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PCNET32_PORT_ASEL, /* 6 not supported */
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PCNET32_PORT_ASEL, /* 7 not supported */
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PCNET32_PORT_ASEL, /* 8 not supported */
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PCNET32_PORT_MII, /* 9 MII 10baseT */
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PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
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PCNET32_PORT_MII, /* 11 MII (autosel) */
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PCNET32_PORT_10BT, /* 12 10BaseT */
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PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
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PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
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PCNET32_PORT_ASEL /* 15 not supported */
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};
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#define MAX_UNITS 8 /* More are supported, limit only on options */
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static int options[MAX_UNITS];
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static int full_duplex[MAX_UNITS];
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/*
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* Theory of Operation
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*
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* This driver uses the same software structure as the normal lance
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* driver. So look for a verbose description in lance.c. The differences
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* to the normal lance driver is the use of the 32bit mode of PCnet32
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* and PCnetPCI chips. Because these chips are 32bit chips, there is no
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* 16MB limitation and we don't need bounce buffers.
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*/
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/*
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* Set the number of Tx and Rx buffers, using Log_2(# buffers).
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* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
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* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
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*/
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#ifndef PCNET32_LOG_TX_BUFFERS
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#define PCNET32_LOG_TX_BUFFERS 1
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#define PCNET32_LOG_RX_BUFFERS 2
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#endif
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#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
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#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
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/* FIXME: Fix this to allow multiple tx_ring descriptors */
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#define TX_RING_LEN_BITS 0x0000 /*PCNET32_LOG_TX_BUFFERS) << 12) */
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#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
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#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
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#define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
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#define PKT_BUF_SZ 1544
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/* Offsets from base I/O address. */
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#define PCNET32_WIO_RDP 0x10
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#define PCNET32_WIO_RAP 0x12
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#define PCNET32_WIO_RESET 0x14
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#define PCNET32_WIO_BDP 0x16
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#define PCNET32_DWIO_RDP 0x10
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#define PCNET32_DWIO_RAP 0x14
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#define PCNET32_DWIO_RESET 0x18
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#define PCNET32_DWIO_BDP 0x1C
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#define PCNET32_TOTAL_SIZE 0x20
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/* The PCNET32 Rx and Tx ring descriptors. */
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struct pcnet32_rx_head {
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u32 base;
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s16 buf_length;
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s16 status;
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u32 msg_length;
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u32 reserved;
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};
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struct pcnet32_tx_head {
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u32 base;
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s16 length;
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s16 status;
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u32 misc;
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u32 reserved;
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};
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/* The PCNET32 32-Bit initialization block, described in databook. */
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struct pcnet32_init_block {
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u16 mode;
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u16 tlen_rlen;
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u8 phys_addr[6];
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u16 reserved;
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u32 filter[2];
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/* Receive and transmit ring base, along with extra bits. */
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u32 rx_ring;
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u32 tx_ring;
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};
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/* PCnet32 access functions */
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struct pcnet32_access {
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u16(*read_csr) (unsigned long, int);
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void (*write_csr) (unsigned long, int, u16);
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u16(*read_bcr) (unsigned long, int);
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void (*write_bcr) (unsigned long, int, u16);
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u16(*read_rap) (unsigned long);
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void (*write_rap) (unsigned long, u16);
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void (*reset) (unsigned long);
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};
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/* Define the TX and RX Descriptors and Rings */
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struct {
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struct pcnet32_tx_head tx_ring[TX_RING_SIZE]
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__attribute__ ((aligned(16)));
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struct pcnet32_rx_head rx_ring[RX_RING_SIZE]
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__attribute__ ((aligned(16)));
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unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
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unsigned char rxb[RX_RING_SIZE * PKT_BUF_SZ];
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} pcnet32_bufs __shared;
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/* May need to be moved to mii.h */
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struct mii_if_info {
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int phy_id;
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int advertising;
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unsigned int full_duplex:1; /* is full duplex? */
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};
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/*
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* The first three fields of pcnet32_private are read by the ethernet device
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* so we allocate the structure should be allocated by pci_alloc_consistent().
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*/
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#define MII_CNT 4
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struct pcnet32_private {
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struct pcnet32_init_block init_block;
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struct pci_dev *pci_dev; /* Pointer to the associated pci device structure */
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const char *name;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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struct sk_buff *tx_skbuff[TX_RING_SIZE];
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struct sk_buff *rx_skbuff[RX_RING_SIZE];
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struct pcnet32_access a;
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unsigned int cur_rx, cur_tx; /* The next free ring entry */
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char tx_full;
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int options;
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int shared_irq:1, /* shared irq possible */
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ltint:1, /* enable TxDone-intr inhibitor */
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dxsuflo:1, /* disable transmit stop on uflo */
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mii:1; /* mii port available */
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struct mii_if_info mii_if;
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unsigned char phys[MII_CNT];
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struct net_device *next;
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int full_duplex:1;
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} lpx;
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static struct pcnet32_private *lp;
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static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num);
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#if 0
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static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
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int val);
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#endif
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enum pci_flags_bit {
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PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
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PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 =
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0x10 << 2, PCI_ADDR3 = 0x10 << 3,
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};
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static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
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{
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outw(index, addr + PCNET32_WIO_RAP);
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return inw(addr + PCNET32_WIO_RDP);
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}
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static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
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{
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outw(index, addr + PCNET32_WIO_RAP);
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outw(val, addr + PCNET32_WIO_RDP);
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}
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static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
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{
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outw(index, addr + PCNET32_WIO_RAP);
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return inw(addr + PCNET32_WIO_BDP);
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}
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static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
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{
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outw(index, addr + PCNET32_WIO_RAP);
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outw(val, addr + PCNET32_WIO_BDP);
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}
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static u16 pcnet32_wio_read_rap(unsigned long addr)
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{
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return inw(addr + PCNET32_WIO_RAP);
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}
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static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
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{
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outw(val, addr + PCNET32_WIO_RAP);
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}
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static void pcnet32_wio_reset(unsigned long addr)
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{
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inw(addr + PCNET32_WIO_RESET);
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}
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static int pcnet32_wio_check(unsigned long addr)
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{
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outw(88, addr + PCNET32_WIO_RAP);
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return (inw(addr + PCNET32_WIO_RAP) == 88);
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}
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static struct pcnet32_access pcnet32_wio = {
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read_csr:pcnet32_wio_read_csr,
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write_csr:pcnet32_wio_write_csr,
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read_bcr:pcnet32_wio_read_bcr,
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write_bcr:pcnet32_wio_write_bcr,
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read_rap:pcnet32_wio_read_rap,
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write_rap:pcnet32_wio_write_rap,
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reset:pcnet32_wio_reset
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};
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static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
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{
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outl(index, addr + PCNET32_DWIO_RAP);
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return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
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}
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static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
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{
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outl(index, addr + PCNET32_DWIO_RAP);
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outl(val, addr + PCNET32_DWIO_RDP);
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}
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static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
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{
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outl(index, addr + PCNET32_DWIO_RAP);
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return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
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}
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static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
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{
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outl(index, addr + PCNET32_DWIO_RAP);
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outl(val, addr + PCNET32_DWIO_BDP);
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}
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static u16 pcnet32_dwio_read_rap(unsigned long addr)
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{
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return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
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}
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static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
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{
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outl(val, addr + PCNET32_DWIO_RAP);
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}
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static void pcnet32_dwio_reset(unsigned long addr)
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{
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inl(addr + PCNET32_DWIO_RESET);
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}
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static int pcnet32_dwio_check(unsigned long addr)
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{
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outl(88, addr + PCNET32_DWIO_RAP);
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return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
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}
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static struct pcnet32_access pcnet32_dwio = {
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read_csr:pcnet32_dwio_read_csr,
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write_csr:pcnet32_dwio_write_csr,
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read_bcr:pcnet32_dwio_read_bcr,
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write_bcr:pcnet32_dwio_write_bcr,
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read_rap:pcnet32_dwio_read_rap,
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write_rap:pcnet32_dwio_write_rap,
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reset:pcnet32_dwio_reset
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};
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/* Initialize the PCNET32 Rx and Tx rings. */
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static int pcnet32_init_ring(struct nic *nic)
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{
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int i;
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lp->tx_full = 0;
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lp->cur_rx = lp->cur_tx = 0;
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for (i = 0; i < RX_RING_SIZE; i++) {
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pcnet32_bufs.rx_ring[i].base =
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virt_to_le32desc(&pcnet32_bufs.rxb[i]);
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pcnet32_bufs.rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
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pcnet32_bufs.rx_ring[i].status = le16_to_cpu(0x8000);
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}
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/* The Tx buffer address is filled in as needed, but we do need to clear
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the upper ownership bit. */
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for (i = 0; i < TX_RING_SIZE; i++) {
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pcnet32_bufs.tx_ring[i].base = 0;
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pcnet32_bufs.tx_ring[i].status = 0;
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}
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lp->init_block.tlen_rlen =
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le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
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for (i = 0; i < 6; i++)
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lp->init_block.phys_addr[i] = nic->node_addr[i];
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lp->init_block.rx_ring = virt_to_le32desc(&pcnet32_bufs.rx_ring[0]);
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lp->init_block.tx_ring = virt_to_le32desc(&pcnet32_bufs.tx_ring[0]);
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return 0;
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}
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/**************************************************************************
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RESET - Reset adapter
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***************************************************************************/
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static void pcnet32_reset(struct nic *nic)
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{
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/* put the card in its initial state */
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u16 val;
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int i;
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/* Reset the PCNET32 */
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lp->a.reset(ioaddr);
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/* switch pcnet32 to 32bit mode */
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lp->a.write_bcr(ioaddr, 20, 2);
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/* set/reset autoselect bit */
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val = lp->a.read_bcr(ioaddr, 2) & ~2;
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if (lp->options & PCNET32_PORT_ASEL)
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val |= 2;
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lp->a.write_bcr(ioaddr, 2, val);
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/* handle full duplex setting */
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if (lp->full_duplex) {
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val = lp->a.read_bcr(ioaddr, 9) & ~3;
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if (lp->options & PCNET32_PORT_FD) {
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val |= 1;
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if (lp->options ==
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(PCNET32_PORT_FD | PCNET32_PORT_AUI))
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val |= 2;
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} else if (lp->options & PCNET32_PORT_ASEL) {
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/* workaround of xSeries250, turn on for 79C975 only */
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i = ((lp->a.
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read_csr(ioaddr,
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88) | (lp->a.read_csr(ioaddr,
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89) << 16)) >>
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12) & 0xffff;
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if (i == 0x2627)
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val |= 3;
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}
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lp->a.write_bcr(ioaddr, 9, val);
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}
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/* set/reset GPSI bit in test register */
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val = lp->a.read_csr(ioaddr, 124) & ~0x10;
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if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
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val |= 0x10;
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lp->a.write_csr(ioaddr, 124, val);
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if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
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val = lp->a.read_bcr(ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
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if (lp->options & PCNET32_PORT_FD)
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val |= 0x10;
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if (lp->options & PCNET32_PORT_100)
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val |= 0x08;
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lp->a.write_bcr(ioaddr, 32, val);
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} else {
|
|
if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */
|
|
val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
|
|
val |= 0x20;
|
|
lp->a.write_bcr(ioaddr, 32, val);
|
|
}
|
|
}
|
|
|
|
#ifdef DO_DXSUFLO
|
|
if (lp->dxsuflo) { /* Disable transmit stop on underflow */
|
|
val = lp->a.read_csr(ioaddr, 3);
|
|
val |= 0x40;
|
|
lp->a.write_csr(ioaddr, 3, val);
|
|
}
|
|
#endif
|
|
if (1)
|
|
{
|
|
//disable interrupts
|
|
val = lp->a.read_csr(ioaddr, 3);
|
|
val = val
|
|
| (1 << 14) //BABLM intr disabled
|
|
| (1 << 12) //MISSM missed frame mask intr disabled
|
|
| (1 << 10) //RINTM receive intr disabled
|
|
| (1 << 9) //TINTM transmit intr disabled
|
|
| (1 << 8) //IDONM init done intr disabled
|
|
;
|
|
lp->a.write_csr(ioaddr, 3, val);
|
|
}
|
|
|
|
if (lp->ltint) { /* Enable TxDone-intr inhibitor */
|
|
val = lp->a.read_csr(ioaddr, 5);
|
|
val |= (1 << 14);
|
|
lp->a.write_csr(ioaddr, 5, val);
|
|
}
|
|
lp->init_block.mode =
|
|
le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
|
|
lp->init_block.filter[0] = 0xffffffff;
|
|
lp->init_block.filter[1] = 0xffffffff;
|
|
|
|
pcnet32_init_ring(nic);
|
|
|
|
|
|
/* Re-initialize the PCNET32, and start it when done. */
|
|
lp->a.write_csr(ioaddr, 1,
|
|
(virt_to_bus(&lp->init_block)) & 0xffff);
|
|
lp->a.write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
|
|
lp->a.write_csr(ioaddr, 4, 0x0915);
|
|
lp->a.write_csr(ioaddr, 0, 0x0001);
|
|
|
|
|
|
i = 0;
|
|
while (i++ < 100)
|
|
if (lp->a.read_csr(ioaddr, 0) & 0x0100)
|
|
break;
|
|
/*
|
|
* We used to clear the InitDone bit, 0x0100, here but Mark Stockton
|
|
* reports that doing so triggers a bug in the '974.
|
|
*/
|
|
lp->a.write_csr(ioaddr, 0, 0x0042);
|
|
|
|
dprintf(("pcnet32 open, csr0 %hX.\n", lp->a.read_csr(ioaddr, 0)));
|
|
|
|
}
|
|
|
|
/**************************************************************************
|
|
POLL - Wait for a frame
|
|
***************************************************************************/
|
|
static int pcnet32_poll(struct nic *nic __unused, int retrieve)
|
|
{
|
|
/* return true if there's an ethernet packet ready to read */
|
|
/* nic->packet should contain data on return */
|
|
/* nic->packetlen should contain length of data */
|
|
|
|
signed char status;
|
|
int entry;
|
|
|
|
entry = lp->cur_rx & RX_RING_MOD_MASK;
|
|
status = (le16_to_cpu(pcnet32_bufs.rx_ring[entry].status) >> 8);
|
|
|
|
if (status < 0)
|
|
return 0;
|
|
|
|
if ( ! retrieve ) return 1;
|
|
|
|
if (status == 0x03) {
|
|
nic->packetlen =
|
|
(le32_to_cpu(pcnet32_bufs.rx_ring[entry].msg_length)
|
|
& 0xfff) - 4;
|
|
memcpy(nic->packet, &pcnet32_bufs.rxb[entry], nic->packetlen);
|
|
|
|
/* Andrew Boyd of QNX reports that some revs of the 79C765
|
|
* clear the buffer length */
|
|
pcnet32_bufs.rx_ring[entry].buf_length
|
|
= le16_to_cpu(-PKT_BUF_SZ);
|
|
/* prime for next receive */
|
|
pcnet32_bufs.rx_ring[entry].status |= le16_to_cpu(0x8000);
|
|
/* Switch to the next Rx ring buffer */
|
|
lp->cur_rx++;
|
|
|
|
} else {
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**************************************************************************
|
|
TRANSMIT - Transmit a frame
|
|
***************************************************************************/
|
|
static void pcnet32_transmit(struct nic *nic __unused, const char *d, /* Destination */
|
|
unsigned int t, /* Type */
|
|
unsigned int s, /* size */
|
|
const char *p)
|
|
{ /* Packet */
|
|
/* send the packet to destination */
|
|
unsigned long time;
|
|
u8 *ptxb;
|
|
u16 nstype;
|
|
u16 status;
|
|
int entry = 0; /*lp->cur_tx & TX_RING_MOD_MASK; */
|
|
|
|
status = 0x8300;
|
|
/* point to the current txb incase multiple tx_rings are used */
|
|
ptxb = pcnet32_bufs.txb + (lp->cur_tx * PKT_BUF_SZ);
|
|
|
|
/* copy the packet to ring buffer */
|
|
memcpy(ptxb, d, ETH_ALEN); /* dst */
|
|
memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
|
|
nstype = htons((u16) t); /* type */
|
|
memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2); /* type */
|
|
memcpy(ptxb + ETH_HLEN, p, s);
|
|
|
|
s += ETH_HLEN;
|
|
while (s < ETH_ZLEN) /* pad to min length */
|
|
ptxb[s++] = '\0';
|
|
|
|
pcnet32_bufs.tx_ring[entry].length = le16_to_cpu(-s);
|
|
pcnet32_bufs.tx_ring[entry].misc = 0x00000000;
|
|
pcnet32_bufs.tx_ring[entry].base = (u32) virt_to_le32desc(ptxb);
|
|
|
|
/* we set the top byte as the very last thing */
|
|
pcnet32_bufs.tx_ring[entry].status = le16_to_cpu(status);
|
|
|
|
|
|
/* Trigger an immediate send poll */
|
|
lp->a.write_csr(ioaddr, 0, 0x0048);
|
|
|
|
/* wait for transmit complete */
|
|
lp->cur_tx = 0; /* (lp->cur_tx + 1); */
|
|
time = currticks() + TICKS_PER_SEC; /* wait one second */
|
|
while (currticks() < time &&
|
|
((short) le16_to_cpu(pcnet32_bufs.tx_ring[entry].status) < 0));
|
|
|
|
if ((short) le16_to_cpu(pcnet32_bufs.tx_ring[entry].status) < 0)
|
|
printf("PCNET32 timed out on transmit\n");
|
|
|
|
/* Stop pointing at the current txb
|
|
* otherwise the card continues to send the packet */
|
|
pcnet32_bufs.tx_ring[entry].base = 0;
|
|
|
|
}
|
|
|
|
/**************************************************************************
|
|
DISABLE - Turn off ethernet interface
|
|
***************************************************************************/
|
|
static void pcnet32_disable ( struct nic *nic __unused ) {
|
|
/* Stop the PCNET32 here -- it ocassionally polls memory if we don't */
|
|
lp->a.write_csr(ioaddr, 0, 0x0004);
|
|
|
|
/*
|
|
* Switch back to 16-bit mode to avoid problems with dumb
|
|
* DOS packet driver after a warm reboot
|
|
*/
|
|
lp->a.write_bcr(ioaddr, 20, 0);
|
|
}
|
|
|
|
/**************************************************************************
|
|
IRQ - Enable, Disable, or Force interrupts
|
|
***************************************************************************/
|
|
static void pcnet32_irq(struct nic *nic __unused, irq_action_t action __unused)
|
|
{
|
|
switch ( action ) {
|
|
case DISABLE :
|
|
break;
|
|
case ENABLE :
|
|
break;
|
|
case FORCE :
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
/**************************************************************************
|
|
PROBE - Look for an adapter, this routine's visible to the outside
|
|
You should omit the last argument struct pci_device * for a non-PCI NIC
|
|
***************************************************************************/
|
|
static int pcnet32_probe ( struct nic *nic, struct pci_device *pci ) {
|
|
|
|
int i, media;
|
|
int fdx, mii, fset, dxsuflo, ltint;
|
|
int chip_version;
|
|
struct pcnet32_access *a = NULL;
|
|
char *chipname;
|
|
u8 promaddr[6];
|
|
int shared = 1;
|
|
|
|
if (pci->ioaddr == 0)
|
|
return 0;
|
|
|
|
/* BASE is used throughout to address the card */
|
|
ioaddr = pci->ioaddr;
|
|
printf("pcnet32.c: Found %s, Vendor=0x%hX Device=0x%hX\n",
|
|
pci->driver_name, pci->vendor, pci->device);
|
|
|
|
nic->irqno = 0;
|
|
pci_fill_nic ( nic, pci );
|
|
nic->ioaddr = pci->ioaddr & ~3;
|
|
|
|
/* reset the chip */
|
|
pcnet32_wio_reset(ioaddr);
|
|
|
|
/* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
|
|
if (pcnet32_wio_read_csr(ioaddr, 0) == 4
|
|
&& pcnet32_wio_check(ioaddr)) {
|
|
a = &pcnet32_wio;
|
|
} else {
|
|
pcnet32_dwio_reset(ioaddr);
|
|
if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
|
|
&& pcnet32_dwio_check(ioaddr)) {
|
|
a = &pcnet32_dwio;
|
|
} else
|
|
return 0;
|
|
}
|
|
|
|
chip_version =
|
|
a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
|
|
|
|
dprintf(("PCnet chip version is 0x%X\n", chip_version));
|
|
if ((chip_version & 0xfff) != 0x003)
|
|
return 0;
|
|
|
|
/* initialize variables */
|
|
fdx = mii = fset = dxsuflo = ltint = 0;
|
|
chip_version = (chip_version >> 12) & 0xffff;
|
|
|
|
switch (chip_version) {
|
|
case 0x2420:
|
|
chipname = "PCnet/PCI 79C970"; /* PCI */
|
|
break;
|
|
case 0x2430:
|
|
if (shared)
|
|
chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
|
|
else
|
|
chipname = "PCnet/32 79C965"; /* 486/VL bus */
|
|
break;
|
|
case 0x2621:
|
|
chipname = "PCnet/PCI II 79C970A"; /* PCI */
|
|
fdx = 1;
|
|
break;
|
|
case 0x2623:
|
|
chipname = "PCnet/FAST 79C971"; /* PCI */
|
|
fdx = 1;
|
|
mii = 1;
|
|
fset = 1;
|
|
ltint = 1;
|
|
break;
|
|
case 0x2624:
|
|
chipname = "PCnet/FAST+ 79C972"; /* PCI */
|
|
fdx = 1;
|
|
mii = 1;
|
|
fset = 1;
|
|
break;
|
|
case 0x2625:
|
|
chipname = "PCnet/FAST III 79C973"; /* PCI */
|
|
fdx = 1;
|
|
mii = 1;
|
|
break;
|
|
case 0x2626:
|
|
chipname = "PCnet/Home 79C978"; /* PCI */
|
|
fdx = 1;
|
|
/*
|
|
* This is based on specs published at www.amd.com. This section
|
|
* assumes that a card with a 79C978 wants to go into 1Mb HomePNA
|
|
* mode. The 79C978 can also go into standard ethernet, and there
|
|
* probably should be some sort of module option to select the
|
|
* mode by which the card should operate
|
|
*/
|
|
/* switch to home wiring mode */
|
|
media = a->read_bcr(ioaddr, 49);
|
|
|
|
printf("media reset to %#x.\n", media);
|
|
a->write_bcr(ioaddr, 49, media);
|
|
break;
|
|
case 0x2627:
|
|
chipname = "PCnet/FAST III 79C975"; /* PCI */
|
|
fdx = 1;
|
|
mii = 1;
|
|
break;
|
|
default:
|
|
chipname = "UNKNOWN";
|
|
printf("PCnet version %#x, no PCnet32 chip.\n",
|
|
chip_version);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
|
|
* starting until the packet is loaded. Strike one for reliability, lose
|
|
* one for latency - although on PCI this isnt a big loss. Older chips
|
|
* have FIFO's smaller than a packet, so you can't do this.
|
|
*/
|
|
|
|
if (fset) {
|
|
a->write_bcr(ioaddr, 18,
|
|
(a->read_bcr(ioaddr, 18) | 0x0800));
|
|
a->write_csr(ioaddr, 80,
|
|
(a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
|
|
dxsuflo = 1;
|
|
ltint = 1;
|
|
}
|
|
|
|
DBG ( "%s at %hX,", chipname, (unsigned int) ioaddr );
|
|
|
|
/* read PROM address */
|
|
for (i = 0; i < 6; i++)
|
|
promaddr[i] = inb(ioaddr + i);
|
|
|
|
/* Update the nic structure with the MAC Address */
|
|
for (i = 0; i < ETH_ALEN; i++) {
|
|
nic->node_addr[i] = promaddr[i];
|
|
}
|
|
|
|
/* Print out some hardware info */
|
|
DBG ( "%s: IO Addr 0x%hX, MAC Addr %s\n ", chipname, (unsigned int) ioaddr,
|
|
eth_ntoa ( nic->node_addr ) );
|
|
|
|
/* Set to pci bus master */
|
|
adjust_pci_device(pci);
|
|
|
|
/* point to private storage */
|
|
lp = &lpx;
|
|
|
|
#if EBDEBUG
|
|
if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
|
|
i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
|
|
dprintf((" tx_start_pt(0x%hX):", i));
|
|
switch (i >> 10) {
|
|
case 0:
|
|
dprintf((" 20 bytes,"));
|
|
break;
|
|
case 1:
|
|
dprintf((" 64 bytes,"));
|
|
break;
|
|
case 2:
|
|
dprintf((" 128 bytes,"));
|
|
break;
|
|
case 3:
|
|
dprintf(("~220 bytes,"));
|
|
break;
|
|
}
|
|
i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
|
|
dprintf((" BCR18(%hX):", i & 0xffff));
|
|
if (i & (1 << 5))
|
|
dprintf(("BurstWrEn "));
|
|
if (i & (1 << 6))
|
|
dprintf(("BurstRdEn "));
|
|
if (i & (1 << 7))
|
|
dprintf(("DWordIO "));
|
|
if (i & (1 << 11))
|
|
dprintf(("NoUFlow "));
|
|
i = a->read_bcr(ioaddr, 25);
|
|
dprintf((" SRAMSIZE=0x%hX,", i << 8));
|
|
i = a->read_bcr(ioaddr, 26);
|
|
dprintf((" SRAM_BND=0x%hX,", i << 8));
|
|
i = a->read_bcr(ioaddr, 27);
|
|
if (i & (1 << 14))
|
|
dprintf(("LowLatRx"));
|
|
}
|
|
#endif
|
|
lp->name = chipname;
|
|
lp->shared_irq = shared;
|
|
lp->full_duplex = fdx;
|
|
lp->dxsuflo = dxsuflo;
|
|
lp->ltint = ltint;
|
|
lp->mii = mii;
|
|
/* FIXME: Fix Options for only one card */
|
|
if ((cards_found >= MAX_UNITS)
|
|
|| ((unsigned int) options[cards_found] > sizeof(options_mapping)))
|
|
lp->options = PCNET32_PORT_ASEL;
|
|
else
|
|
lp->options = options_mapping[options[cards_found]];
|
|
|
|
if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
|
|
((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
|
|
lp->options |= PCNET32_PORT_FD;
|
|
|
|
if (!a) {
|
|
printf("No access methods\n");
|
|
return 0;
|
|
}
|
|
|
|
// lp->a = *a;
|
|
// Causes a loader:
|
|
// bin/blib.a(pcnet32.o)(.text+0x6b6): In function `pcnet32_probe':
|
|
// drivers/net/pcnet32.c:871: undefined reference to `memcpy'
|
|
// make: *** [bin/pcnet32.dsk.tmp] Error 1
|
|
// So we do:
|
|
memcpy ( &lp->a, a, sizeof ( lp->a ) );
|
|
// To explicity call memcpy.
|
|
|
|
/* detect special T1/E1 WAN card by checking for MAC address */
|
|
if (nic->node_addr[0] == 0x00 && nic->node_addr[1] == 0xe0
|
|
&& nic->node_addr[2] == 0x75)
|
|
lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
|
|
|
|
lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
|
|
lp->init_block.tlen_rlen =
|
|
le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
|
|
for (i = 0; i < 6; i++)
|
|
lp->init_block.phys_addr[i] = nic->node_addr[i];
|
|
lp->init_block.filter[0] = 0xffffffff;
|
|
lp->init_block.filter[1] = 0xffffffff;
|
|
lp->init_block.rx_ring = virt_to_bus(&pcnet32_bufs.rx_ring);
|
|
lp->init_block.tx_ring = virt_to_bus(&pcnet32_bufs.tx_ring);
|
|
|
|
/* switch pcnet32 to 32bit mode */
|
|
a->write_bcr(ioaddr, 20, 2);
|
|
|
|
a->write_csr(ioaddr, 1, (virt_to_bus(&lp->init_block)) & 0xffff);
|
|
a->write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
|
|
|
|
/*
|
|
* To auto-IRQ we enable the initialization-done and DMA error
|
|
* interrupts. For ISA boards we get a DMA error, but VLB and PCI
|
|
* boards will work.
|
|
*/
|
|
/* Trigger an initialization just for the interrupt. */
|
|
|
|
|
|
// a->write_csr(ioaddr, 0, 0x41);
|
|
// mdelay(1);
|
|
|
|
cards_found++;
|
|
|
|
/* point to NIC specific routines */
|
|
pcnet32_reset(nic);
|
|
if (mii) {
|
|
int tmp;
|
|
int phy, phy_idx = 0;
|
|
u16 mii_lpa;
|
|
lp->phys[0] = 1; /* Default Setting */
|
|
for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
|
|
int mii_status = mdio_read(nic, phy, MII_BMSR);
|
|
if (mii_status != 0xffff && mii_status != 0x0000) {
|
|
lp->phys[phy_idx++] = phy;
|
|
lp->mii_if.advertising =
|
|
mdio_read(nic, phy, MII_ADVERTISE);
|
|
if ((mii_status & 0x0040) == 0) {
|
|
tmp = phy;
|
|
dprintf (("MII PHY found at address %d, status "
|
|
"%hX advertising %hX\n", phy, mii_status,
|
|
lp->mii_if.advertising));
|
|
}
|
|
}
|
|
}
|
|
if (phy_idx == 0)
|
|
printf("No MII transceiver found!\n");
|
|
lp->mii_if.phy_id = lp->phys[0];
|
|
|
|
lp->mii_if.advertising =
|
|
mdio_read(nic, lp->phys[0], MII_ADVERTISE);
|
|
|
|
mii_lpa = mdio_read(nic, lp->phys[0], MII_LPA);
|
|
lp->mii_if.advertising &= mii_lpa;
|
|
if (lp->mii_if.advertising & ADVERTISE_100FULL)
|
|
printf("100Mbps Full-Duplex\n");
|
|
else if (lp->mii_if.advertising & ADVERTISE_100HALF)
|
|
printf("100Mbps Half-Duplex\n");
|
|
else if (lp->mii_if.advertising & ADVERTISE_10FULL)
|
|
printf("10Mbps Full-Duplex\n");
|
|
else if (lp->mii_if.advertising & ADVERTISE_10HALF)
|
|
printf("10Mbps Half-Duplex\n");
|
|
else
|
|
printf("\n");
|
|
} else {
|
|
/* The older chips are fixed 10Mbps, and some support full duplex,
|
|
* although not via autonegotiation, but only via configuration. */
|
|
if (fdx)
|
|
printf("10Mbps Full-Duplex\n");
|
|
else
|
|
printf("10Mbps Half-Duplex\n");
|
|
}
|
|
|
|
nic->nic_op = &pcnet32_operations;
|
|
|
|
return 1;
|
|
}
|
|
static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num)
|
|
{
|
|
u16 val_out;
|
|
int phyaddr;
|
|
|
|
if (!lp->mii)
|
|
return 0;
|
|
|
|
phyaddr = lp->a.read_bcr(ioaddr, 33);
|
|
|
|
lp->a.write_bcr(ioaddr, 33,
|
|
((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
|
|
val_out = lp->a.read_bcr(ioaddr, 34);
|
|
lp->a.write_bcr(ioaddr, 33, phyaddr);
|
|
|
|
return val_out;
|
|
}
|
|
|
|
#if 0
|
|
static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
|
|
int val)
|
|
{
|
|
int phyaddr;
|
|
|
|
if (!lp->mii)
|
|
return;
|
|
|
|
phyaddr = lp->a.read_bcr(ioaddr, 33);
|
|
|
|
lp->a.write_bcr(ioaddr, 33,
|
|
((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
|
|
lp->a.write_bcr(ioaddr, 34, val);
|
|
lp->a.write_bcr(ioaddr, 33, phyaddr);
|
|
}
|
|
#endif
|
|
|
|
static struct nic_operations pcnet32_operations = {
|
|
.connect = dummy_connect,
|
|
.poll = pcnet32_poll,
|
|
.transmit = pcnet32_transmit,
|
|
.irq = pcnet32_irq,
|
|
|
|
};
|
|
|
|
static struct pci_device_id pcnet32_nics[] = {
|
|
PCI_ROM(0x1022, 0x2000, "pcnet32", "AMD PCnet/PCI"),
|
|
PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD PCNet FAST III"),
|
|
PCI_ROM(0x1022, 0x2001, "amdhomepna", "AMD PCnet/HomePNA"),
|
|
};
|
|
|
|
PCI_DRIVER ( pcnet32_driver, pcnet32_nics, PCI_NO_CLASS );
|
|
|
|
DRIVER ( "PCNET32/PCI", nic_driver, pci_driver, pcnet32_driver,
|
|
pcnet32_probe, pcnet32_disable );
|