1151 lines
34 KiB
C
1151 lines
34 KiB
C
/*
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* Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <string.h>
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#include <unistd.h>
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#include <errno.h>
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#include <byteswap.h>
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#include <ipxe/netdevice.h>
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#include <ipxe/ethernet.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/iobuf.h>
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#include <ipxe/malloc.h>
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#include <ipxe/pci.h>
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#include <ipxe/profile.h>
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#include "intel.h"
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/** @file
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*
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* Intel 10/100/1000 network card driver
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*
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*/
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/** VM transmit profiler */
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static struct profiler intel_vm_tx_profiler __profiler =
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{ .name = "intel.vm_tx" };
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/** VM receive refill profiler */
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static struct profiler intel_vm_refill_profiler __profiler =
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{ .name = "intel.vm_refill" };
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/** VM poll profiler */
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static struct profiler intel_vm_poll_profiler __profiler =
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{ .name = "intel.vm_poll" };
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/******************************************************************************
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*
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* EEPROM interface
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*
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******************************************************************************
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*/
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/**
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* Read data from EEPROM
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*
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* @v nvs NVS device
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* @v address Address from which to read
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* @v data Data buffer
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* @v len Length of data buffer
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* @ret rc Return status code
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*/
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static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
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void *data, size_t len ) {
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struct intel_nic *intel =
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container_of ( nvs, struct intel_nic, eeprom );
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unsigned int i;
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uint32_t value;
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uint16_t *data_word = data;
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/* Sanity check. We advertise a blocksize of one word, so
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* should only ever receive single-word requests.
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*/
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assert ( len == sizeof ( *data_word ) );
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/* Initiate read */
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writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
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intel->regs + INTEL_EERD );
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/* Wait for read to complete */
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for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
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/* If read is not complete, delay 1ms and retry */
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value = readl ( intel->regs + INTEL_EERD );
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if ( ! ( value & intel->eerd_done ) ) {
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mdelay ( 1 );
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continue;
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}
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/* Extract data */
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*data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
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return 0;
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}
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DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
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return -ETIMEDOUT;
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}
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/**
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* Write data to EEPROM
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*
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* @v nvs NVS device
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* @v address Address to which to write
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* @v data Data buffer
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* @v len Length of data buffer
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* @ret rc Return status code
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*/
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static int intel_write_eeprom ( struct nvs_device *nvs,
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unsigned int address __unused,
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const void *data __unused,
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size_t len __unused ) {
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struct intel_nic *intel =
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container_of ( nvs, struct intel_nic, eeprom );
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DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
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return -ENOTSUP;
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}
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/**
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* Initialise EEPROM
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*
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* @v intel Intel device
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* @ret rc Return status code
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*/
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static int intel_init_eeprom ( struct intel_nic *intel ) {
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unsigned int i;
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uint32_t value;
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/* The NIC automatically detects the type of attached EEPROM.
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* The EERD register provides access to only a single word at
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* a time, so we pretend to have a single-word block size.
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*
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* The EEPROM size may be larger than the minimum size, but
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* this doesn't matter to us since we access only the first
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* few words.
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*/
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intel->eeprom.word_len_log2 = INTEL_EEPROM_WORD_LEN_LOG2;
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intel->eeprom.size = INTEL_EEPROM_MIN_SIZE_WORDS;
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intel->eeprom.block_size = 1;
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intel->eeprom.read = intel_read_eeprom;
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intel->eeprom.write = intel_write_eeprom;
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/* The layout of the EERD register was changed at some point
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* to accommodate larger EEPROMs. Read from address zero (for
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* which the request layouts are compatible) to determine
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* which type of register we have.
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*/
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writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
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for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
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value = readl ( intel->regs + INTEL_EERD );
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if ( value & INTEL_EERD_DONE_LARGE ) {
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DBGC ( intel, "INTEL %p has large-format EERD\n",
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intel );
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intel->eerd_done = INTEL_EERD_DONE_LARGE;
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intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_LARGE;
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return 0;
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}
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if ( value & INTEL_EERD_DONE_SMALL ) {
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DBGC ( intel, "INTEL %p has small-format EERD\n",
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intel );
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intel->eerd_done = INTEL_EERD_DONE_SMALL;
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intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_SMALL;
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return 0;
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}
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mdelay ( 1 );
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}
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DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
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"(value %08x)\n", intel, value );
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return -ETIMEDOUT;
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}
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/******************************************************************************
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*
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* MAC address
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*
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******************************************************************************
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*/
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/**
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* Fetch initial MAC address from EEPROM
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*
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* @v intel Intel device
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* @v hw_addr Hardware address to fill in
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* @ret rc Return status code
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*/
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static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
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uint8_t *hw_addr ) {
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int rc;
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/* Initialise EEPROM */
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if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
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return rc;
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/* Read base MAC address from EEPROM */
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if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
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hw_addr, ETH_ALEN ) ) != 0 ) {
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DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
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"address: %s\n", intel, strerror ( rc ) );
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return rc;
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}
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/* Adjust MAC address for multi-port devices */
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hw_addr[ETH_ALEN-1] ^= intel->port;
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DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
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intel, eth_ntoa ( hw_addr ), intel->port );
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return 0;
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}
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/**
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* Fetch initial MAC address
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*
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* @v intel Intel device
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* @v hw_addr Hardware address to fill in
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* @ret rc Return status code
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*/
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static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
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union intel_receive_address mac;
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int rc;
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/* Read current address from RAL0/RAH0 */
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mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
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mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
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DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
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intel, eth_ntoa ( mac.raw ) );
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/* Use current address if valid */
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if ( is_valid_ether_addr ( mac.raw ) ) {
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memcpy ( hw_addr, mac.raw, ETH_ALEN );
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return 0;
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}
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/* Otherwise, try to read address from EEPROM */
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if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
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return 0;
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DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
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return -ENOENT;
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}
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/******************************************************************************
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*
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* Device reset
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*
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******************************************************************************
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*/
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/**
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* Reset hardware
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*
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* @v intel Intel device
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* @ret rc Return status code
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*/
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static int intel_reset ( struct intel_nic *intel ) {
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uint32_t pbs;
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uint32_t pba;
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uint32_t ctrl;
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uint32_t status;
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uint32_t orig_ctrl;
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uint32_t orig_status;
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/* Record initial control and status register values */
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orig_ctrl = ctrl = readl ( intel->regs + INTEL_CTRL );
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orig_status = readl ( intel->regs + INTEL_STATUS );
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/* Force RX and TX packet buffer allocation, to work around an
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* errata in ICH devices.
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*/
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if ( intel->flags & INTEL_PBS_ERRATA ) {
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DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
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intel );
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pbs = readl ( intel->regs + INTEL_PBS );
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pba = readl ( intel->regs + INTEL_PBA );
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writel ( 0x08, intel->regs + INTEL_PBA );
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writel ( 0x10, intel->regs + INTEL_PBS );
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DBGC ( intel, "INTEL %p PBS %#08x->%#08x PBA %#08x->%#08x\n",
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intel, pbs, readl ( intel->regs + INTEL_PBS ),
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pba, readl ( intel->regs + INTEL_PBA ) );
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}
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/* Always reset MAC. Required to reset the TX and RX rings. */
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writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
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mdelay ( INTEL_RESET_DELAY_MS );
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/* Set a sensible default configuration */
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if ( ! ( intel->flags & INTEL_NO_ASDE ) )
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ctrl |= INTEL_CTRL_ASDE;
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ctrl |= INTEL_CTRL_SLU;
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ctrl &= ~( INTEL_CTRL_LRST | INTEL_CTRL_FRCSPD | INTEL_CTRL_FRCDPLX );
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writel ( ctrl, intel->regs + INTEL_CTRL );
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mdelay ( INTEL_RESET_DELAY_MS );
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/* On some models (notably ICH), the PHY reset mechanism
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* appears to be broken. In particular, the PHY_CTRL register
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* will be correctly loaded from NVM but the values will not
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* be propagated to the "OEM bits" PHY register. This
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* typically has the effect of dropping the link speed to
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* 10Mbps.
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*
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* Work around this problem by skipping the PHY reset if
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* either (a) the link is already up, or (b) this particular
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* NIC is known to be broken.
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*/
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status = readl ( intel->regs + INTEL_STATUS );
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if ( ( intel->flags & INTEL_NO_PHY_RST ) ||
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( status & INTEL_STATUS_LU ) ) {
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DBGC ( intel, "INTEL %p %sMAC reset (%08x/%08x was "
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"%08x/%08x)\n", intel,
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( ( intel->flags & INTEL_NO_PHY_RST ) ? "forced " : "" ),
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ctrl, status, orig_ctrl, orig_status );
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return 0;
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}
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/* Reset PHY and MAC simultaneously */
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writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
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intel->regs + INTEL_CTRL );
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mdelay ( INTEL_RESET_DELAY_MS );
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/* PHY reset is not self-clearing on all models */
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writel ( ctrl, intel->regs + INTEL_CTRL );
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mdelay ( INTEL_RESET_DELAY_MS );
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status = readl ( intel->regs + INTEL_STATUS );
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DBGC ( intel, "INTEL %p MAC+PHY reset (%08x/%08x was %08x/%08x)\n",
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intel, ctrl, status, orig_ctrl, orig_status );
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return 0;
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}
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/******************************************************************************
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*
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* Link state
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*
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******************************************************************************
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*/
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/**
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* Check link state
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*
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* @v netdev Network device
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*/
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static void intel_check_link ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t status;
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/* Read link status */
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status = readl ( intel->regs + INTEL_STATUS );
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DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
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/* Update network device */
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if ( status & INTEL_STATUS_LU ) {
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netdev_link_up ( netdev );
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} else {
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netdev_link_down ( netdev );
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}
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}
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/******************************************************************************
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*
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* Descriptors
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*
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******************************************************************************
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*/
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/**
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* Populate transmit descriptor
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*
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* @v tx Transmit descriptor
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* @v addr Data buffer address
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* @v len Length of data
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*/
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void intel_describe_tx ( struct intel_descriptor *tx, physaddr_t addr,
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size_t len ) {
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/* Populate transmit descriptor */
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tx->address = cpu_to_le64 ( addr );
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tx->length = cpu_to_le16 ( len );
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tx->flags = 0;
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tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
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INTEL_DESC_CMD_EOP );
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tx->status = 0;
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}
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/**
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* Populate advanced transmit descriptor
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*
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* @v tx Transmit descriptor
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* @v addr Data buffer address
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* @v len Length of data
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*/
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void intel_describe_tx_adv ( struct intel_descriptor *tx, physaddr_t addr,
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size_t len ) {
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/* Populate advanced transmit descriptor */
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tx->address = cpu_to_le64 ( addr );
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tx->length = cpu_to_le16 ( len );
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tx->flags = INTEL_DESC_FL_DTYP_DATA;
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tx->command = ( INTEL_DESC_CMD_DEXT | INTEL_DESC_CMD_RS |
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INTEL_DESC_CMD_IFCS | INTEL_DESC_CMD_EOP );
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tx->status = cpu_to_le32 ( INTEL_DESC_STATUS_PAYLEN ( len ) );
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}
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/**
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* Populate receive descriptor
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*
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* @v rx Receive descriptor
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* @v addr Data buffer address
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* @v len Length of data
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*/
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void intel_describe_rx ( struct intel_descriptor *rx, physaddr_t addr,
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size_t len __unused ) {
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/* Populate transmit descriptor */
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rx->address = cpu_to_le64 ( addr );
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rx->length = 0;
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rx->status = 0;
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}
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/******************************************************************************
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*
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* Network device interface
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*
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******************************************************************************
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*/
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/**
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* Disable descriptor ring
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*
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* @v intel Intel device
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* @v reg Register block
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* @ret rc Return status code
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*/
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static int intel_disable_ring ( struct intel_nic *intel, unsigned int reg ) {
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uint32_t dctl;
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unsigned int i;
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/* Disable ring */
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writel ( 0, ( intel->regs + reg + INTEL_xDCTL ) );
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/* Wait for disable to complete */
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for ( i = 0 ; i < INTEL_DISABLE_MAX_WAIT_MS ; i++ ) {
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/* Check if ring is disabled */
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dctl = readl ( intel->regs + reg + INTEL_xDCTL );
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if ( ! ( dctl & INTEL_xDCTL_ENABLE ) )
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return 0;
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/* Delay */
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mdelay ( 1 );
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}
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DBGC ( intel, "INTEL %p ring %05x timed out waiting for disable "
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"(dctl %08x)\n", intel, reg, dctl );
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return -ETIMEDOUT;
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}
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/**
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* Reset descriptor ring
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*
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* @v intel Intel device
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* @v reg Register block
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* @ret rc Return status code
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*/
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void intel_reset_ring ( struct intel_nic *intel, unsigned int reg ) {
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/* Disable ring. Ignore errors and continue to reset the ring anyway */
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intel_disable_ring ( intel, reg );
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/* Clear ring length */
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writel ( 0, ( intel->regs + reg + INTEL_xDLEN ) );
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/* Clear ring address */
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writel ( 0, ( intel->regs + reg + INTEL_xDBAH ) );
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writel ( 0, ( intel->regs + reg + INTEL_xDBAL ) );
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/* Reset head and tail pointers */
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writel ( 0, ( intel->regs + reg + INTEL_xDH ) );
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writel ( 0, ( intel->regs + reg + INTEL_xDT ) );
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}
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|
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/**
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* Create descriptor ring
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*
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* @v intel Intel device
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* @v ring Descriptor ring
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* @ret rc Return status code
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*/
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int intel_create_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
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physaddr_t address;
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uint32_t dctl;
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|
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/* Allocate descriptor ring. Align ring on its own size to
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* prevent any possible page-crossing errors due to hardware
|
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* errata.
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*/
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ring->desc = malloc_dma ( ring->len, ring->len );
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if ( ! ring->desc )
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return -ENOMEM;
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|
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/* Initialise descriptor ring */
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memset ( ring->desc, 0, ring->len );
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|
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/* Program ring address */
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address = virt_to_bus ( ring->desc );
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writel ( ( address & 0xffffffffUL ),
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( intel->regs + ring->reg + INTEL_xDBAL ) );
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if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
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writel ( ( ( ( uint64_t ) address ) >> 32 ),
|
|
( intel->regs + ring->reg + INTEL_xDBAH ) );
|
|
} else {
|
|
writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
|
|
}
|
|
|
|
/* Program ring length */
|
|
writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
|
|
|
|
/* Reset head and tail pointers */
|
|
writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
|
|
writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
|
|
|
|
/* Enable ring */
|
|
dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
|
|
dctl |= INTEL_xDCTL_ENABLE;
|
|
writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
|
|
|
|
DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
|
|
intel, ring->reg, ( ( unsigned long long ) address ),
|
|
( ( unsigned long long ) address + ring->len ) );
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Destroy descriptor ring
|
|
*
|
|
* @v intel Intel device
|
|
* @v ring Descriptor ring
|
|
*/
|
|
void intel_destroy_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
|
|
|
|
/* Reset ring */
|
|
intel_reset_ring ( intel, ring->reg );
|
|
|
|
/* Free descriptor ring */
|
|
free_dma ( ring->desc, ring->len );
|
|
ring->desc = NULL;
|
|
ring->prod = 0;
|
|
ring->cons = 0;
|
|
}
|
|
|
|
/**
|
|
* Refill receive descriptor ring
|
|
*
|
|
* @v intel Intel device
|
|
*/
|
|
void intel_refill_rx ( struct intel_nic *intel ) {
|
|
struct intel_descriptor *rx;
|
|
struct io_buffer *iobuf;
|
|
unsigned int rx_idx;
|
|
unsigned int rx_tail;
|
|
physaddr_t address;
|
|
unsigned int refilled = 0;
|
|
|
|
/* Refill ring */
|
|
while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
|
|
|
|
/* Allocate I/O buffer */
|
|
iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
|
|
if ( ! iobuf ) {
|
|
/* Wait for next refill */
|
|
break;
|
|
}
|
|
|
|
/* Get next receive descriptor */
|
|
rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
|
|
rx = &intel->rx.desc[rx_idx];
|
|
|
|
/* Populate receive descriptor */
|
|
address = virt_to_bus ( iobuf->data );
|
|
intel->rx.describe ( rx, address, 0 );
|
|
|
|
/* Record I/O buffer */
|
|
assert ( intel->rx_iobuf[rx_idx] == NULL );
|
|
intel->rx_iobuf[rx_idx] = iobuf;
|
|
|
|
DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
|
|
( ( unsigned long long ) address ),
|
|
( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
|
|
refilled++;
|
|
}
|
|
|
|
/* Push descriptors to card, if applicable */
|
|
if ( refilled ) {
|
|
wmb();
|
|
rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
|
|
profile_start ( &intel_vm_refill_profiler );
|
|
writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
|
|
profile_stop ( &intel_vm_refill_profiler );
|
|
profile_exclude ( &intel_vm_refill_profiler );
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Discard unused receive I/O buffers
|
|
*
|
|
* @v intel Intel device
|
|
*/
|
|
void intel_empty_rx ( struct intel_nic *intel ) {
|
|
unsigned int i;
|
|
|
|
for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
|
|
if ( intel->rx_iobuf[i] )
|
|
free_iob ( intel->rx_iobuf[i] );
|
|
intel->rx_iobuf[i] = NULL;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Open network device
|
|
*
|
|
* @v netdev Network device
|
|
* @ret rc Return status code
|
|
*/
|
|
static int intel_open ( struct net_device *netdev ) {
|
|
struct intel_nic *intel = netdev->priv;
|
|
union intel_receive_address mac;
|
|
uint32_t tctl;
|
|
uint32_t rctl;
|
|
int rc;
|
|
|
|
/* Create transmit descriptor ring */
|
|
if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
|
|
goto err_create_tx;
|
|
|
|
/* Create receive descriptor ring */
|
|
if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
|
|
goto err_create_rx;
|
|
|
|
/* Program MAC address */
|
|
memset ( &mac, 0, sizeof ( mac ) );
|
|
memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
|
|
writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
|
|
writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
|
|
intel->regs + INTEL_RAH0 );
|
|
|
|
/* Enable transmitter */
|
|
tctl = readl ( intel->regs + INTEL_TCTL );
|
|
tctl &= ~( INTEL_TCTL_CT_MASK | INTEL_TCTL_COLD_MASK );
|
|
tctl |= ( INTEL_TCTL_EN | INTEL_TCTL_PSP | INTEL_TCTL_CT_DEFAULT |
|
|
INTEL_TCTL_COLD_DEFAULT );
|
|
writel ( tctl, intel->regs + INTEL_TCTL );
|
|
|
|
/* Enable receiver */
|
|
rctl = readl ( intel->regs + INTEL_RCTL );
|
|
rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
|
|
rctl |= ( INTEL_RCTL_EN | INTEL_RCTL_UPE | INTEL_RCTL_MPE |
|
|
INTEL_RCTL_BAM | INTEL_RCTL_BSIZE_2048 | INTEL_RCTL_SECRC );
|
|
writel ( rctl, intel->regs + INTEL_RCTL );
|
|
|
|
/* Fill receive ring */
|
|
intel_refill_rx ( intel );
|
|
|
|
/* Update link state */
|
|
intel_check_link ( netdev );
|
|
|
|
/* Apply required errata */
|
|
if ( intel->flags & INTEL_VMWARE ) {
|
|
DBGC ( intel, "INTEL %p applying VMware errata workaround\n",
|
|
intel );
|
|
intel->force_icr = INTEL_IRQ_RXT0;
|
|
}
|
|
|
|
return 0;
|
|
|
|
intel_destroy_ring ( intel, &intel->rx );
|
|
err_create_rx:
|
|
intel_destroy_ring ( intel, &intel->tx );
|
|
err_create_tx:
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* Close network device
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
static void intel_close ( struct net_device *netdev ) {
|
|
struct intel_nic *intel = netdev->priv;
|
|
|
|
/* Disable receiver */
|
|
writel ( 0, intel->regs + INTEL_RCTL );
|
|
|
|
/* Disable transmitter */
|
|
writel ( 0, intel->regs + INTEL_TCTL );
|
|
|
|
/* Destroy receive descriptor ring */
|
|
intel_destroy_ring ( intel, &intel->rx );
|
|
|
|
/* Discard any unused receive buffers */
|
|
intel_empty_rx ( intel );
|
|
|
|
/* Destroy transmit descriptor ring */
|
|
intel_destroy_ring ( intel, &intel->tx );
|
|
|
|
/* Reset the NIC, to flush the transmit and receive FIFOs */
|
|
intel_reset ( intel );
|
|
}
|
|
|
|
/**
|
|
* Transmit packet
|
|
*
|
|
* @v netdev Network device
|
|
* @v iobuf I/O buffer
|
|
* @ret rc Return status code
|
|
*/
|
|
int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
|
|
struct intel_nic *intel = netdev->priv;
|
|
struct intel_descriptor *tx;
|
|
unsigned int tx_idx;
|
|
unsigned int tx_tail;
|
|
physaddr_t address;
|
|
size_t len;
|
|
|
|
/* Get next transmit descriptor */
|
|
if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
|
|
DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
|
|
return -ENOBUFS;
|
|
}
|
|
tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
|
|
tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
|
|
tx = &intel->tx.desc[tx_idx];
|
|
|
|
/* Populate transmit descriptor */
|
|
address = virt_to_bus ( iobuf->data );
|
|
len = iob_len ( iobuf );
|
|
intel->tx.describe ( tx, address, len );
|
|
wmb();
|
|
|
|
/* Notify card that there are packets ready to transmit */
|
|
profile_start ( &intel_vm_tx_profiler );
|
|
writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
|
|
profile_stop ( &intel_vm_tx_profiler );
|
|
profile_exclude ( &intel_vm_tx_profiler );
|
|
|
|
DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
|
|
( ( unsigned long long ) address ),
|
|
( ( unsigned long long ) address + len ) );
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Poll for completed packets
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
void intel_poll_tx ( struct net_device *netdev ) {
|
|
struct intel_nic *intel = netdev->priv;
|
|
struct intel_descriptor *tx;
|
|
unsigned int tx_idx;
|
|
|
|
/* Check for completed packets */
|
|
while ( intel->tx.cons != intel->tx.prod ) {
|
|
|
|
/* Get next transmit descriptor */
|
|
tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
|
|
tx = &intel->tx.desc[tx_idx];
|
|
|
|
/* Stop if descriptor is still in use */
|
|
if ( ! ( tx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
|
|
return;
|
|
|
|
DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
|
|
|
|
/* Complete TX descriptor */
|
|
netdev_tx_complete_next ( netdev );
|
|
intel->tx.cons++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Poll for received packets
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
void intel_poll_rx ( struct net_device *netdev ) {
|
|
struct intel_nic *intel = netdev->priv;
|
|
struct intel_descriptor *rx;
|
|
struct io_buffer *iobuf;
|
|
unsigned int rx_idx;
|
|
size_t len;
|
|
|
|
/* Check for received packets */
|
|
while ( intel->rx.cons != intel->rx.prod ) {
|
|
|
|
/* Get next receive descriptor */
|
|
rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
|
|
rx = &intel->rx.desc[rx_idx];
|
|
|
|
/* Stop if descriptor is still in use */
|
|
if ( ! ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
|
|
return;
|
|
|
|
/* Populate I/O buffer */
|
|
iobuf = intel->rx_iobuf[rx_idx];
|
|
intel->rx_iobuf[rx_idx] = NULL;
|
|
len = le16_to_cpu ( rx->length );
|
|
iob_put ( iobuf, len );
|
|
|
|
/* Hand off to network stack */
|
|
if ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_RXE ) ) {
|
|
DBGC ( intel, "INTEL %p RX %d error (length %zd, "
|
|
"status %08x)\n", intel, rx_idx, len,
|
|
le32_to_cpu ( rx->status ) );
|
|
netdev_rx_err ( netdev, iobuf, -EIO );
|
|
} else {
|
|
DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
|
|
intel, rx_idx, len );
|
|
netdev_rx ( netdev, iobuf );
|
|
}
|
|
intel->rx.cons++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Poll for completed and received packets
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
static void intel_poll ( struct net_device *netdev ) {
|
|
struct intel_nic *intel = netdev->priv;
|
|
uint32_t icr;
|
|
|
|
/* Check for and acknowledge interrupts */
|
|
profile_start ( &intel_vm_poll_profiler );
|
|
icr = readl ( intel->regs + INTEL_ICR );
|
|
profile_stop ( &intel_vm_poll_profiler );
|
|
profile_exclude ( &intel_vm_poll_profiler );
|
|
icr |= intel->force_icr;
|
|
if ( ! icr )
|
|
return;
|
|
|
|
/* Poll for TX completions, if applicable */
|
|
if ( icr & INTEL_IRQ_TXDW )
|
|
intel_poll_tx ( netdev );
|
|
|
|
/* Poll for RX completions, if applicable */
|
|
if ( icr & ( INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) )
|
|
intel_poll_rx ( netdev );
|
|
|
|
/* Report receive overruns */
|
|
if ( icr & INTEL_IRQ_RXO )
|
|
netdev_rx_err ( netdev, NULL, -ENOBUFS );
|
|
|
|
/* Check link state, if applicable */
|
|
if ( icr & INTEL_IRQ_LSC )
|
|
intel_check_link ( netdev );
|
|
|
|
/* Check for unexpected interrupts */
|
|
if ( icr & ~( INTEL_IRQ_TXDW | INTEL_IRQ_TXQE | INTEL_IRQ_LSC |
|
|
INTEL_IRQ_RXDMT0 | INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) ) {
|
|
DBGC ( intel, "INTEL %p unexpected ICR %08x\n", intel, icr );
|
|
/* Report as a TX error */
|
|
netdev_tx_err ( netdev, NULL, -ENOTSUP );
|
|
}
|
|
|
|
/* Refill RX ring */
|
|
intel_refill_rx ( intel );
|
|
}
|
|
|
|
/**
|
|
* Enable or disable interrupts
|
|
*
|
|
* @v netdev Network device
|
|
* @v enable Interrupts should be enabled
|
|
*/
|
|
static void intel_irq ( struct net_device *netdev, int enable ) {
|
|
struct intel_nic *intel = netdev->priv;
|
|
uint32_t mask;
|
|
|
|
mask = ( INTEL_IRQ_TXDW | INTEL_IRQ_LSC | INTEL_IRQ_RXT0 );
|
|
if ( enable ) {
|
|
writel ( mask, intel->regs + INTEL_IMS );
|
|
} else {
|
|
writel ( mask, intel->regs + INTEL_IMC );
|
|
}
|
|
}
|
|
|
|
/** Intel network device operations */
|
|
static struct net_device_operations intel_operations = {
|
|
.open = intel_open,
|
|
.close = intel_close,
|
|
.transmit = intel_transmit,
|
|
.poll = intel_poll,
|
|
.irq = intel_irq,
|
|
};
|
|
|
|
/******************************************************************************
|
|
*
|
|
* PCI interface
|
|
*
|
|
******************************************************************************
|
|
*/
|
|
|
|
/**
|
|
* Probe PCI device
|
|
*
|
|
* @v pci PCI device
|
|
* @ret rc Return status code
|
|
*/
|
|
static int intel_probe ( struct pci_device *pci ) {
|
|
struct net_device *netdev;
|
|
struct intel_nic *intel;
|
|
int rc;
|
|
|
|
/* Allocate and initialise net device */
|
|
netdev = alloc_etherdev ( sizeof ( *intel ) );
|
|
if ( ! netdev ) {
|
|
rc = -ENOMEM;
|
|
goto err_alloc;
|
|
}
|
|
netdev_init ( netdev, &intel_operations );
|
|
intel = netdev->priv;
|
|
pci_set_drvdata ( pci, netdev );
|
|
netdev->dev = &pci->dev;
|
|
memset ( intel, 0, sizeof ( *intel ) );
|
|
intel->port = PCI_FUNC ( pci->busdevfn );
|
|
intel->flags = pci->id->driver_data;
|
|
intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD,
|
|
intel_describe_tx );
|
|
intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD,
|
|
intel_describe_rx );
|
|
|
|
/* Fix up PCI device */
|
|
adjust_pci_device ( pci );
|
|
|
|
/* Map registers */
|
|
intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
|
|
if ( ! intel->regs ) {
|
|
rc = -ENODEV;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
/* Reset the NIC */
|
|
if ( ( rc = intel_reset ( intel ) ) != 0 )
|
|
goto err_reset;
|
|
|
|
/* Fetch MAC address */
|
|
if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
|
|
goto err_fetch_mac;
|
|
|
|
/* Register network device */
|
|
if ( ( rc = register_netdev ( netdev ) ) != 0 )
|
|
goto err_register_netdev;
|
|
|
|
/* Set initial link state */
|
|
intel_check_link ( netdev );
|
|
|
|
return 0;
|
|
|
|
unregister_netdev ( netdev );
|
|
err_register_netdev:
|
|
err_fetch_mac:
|
|
intel_reset ( intel );
|
|
err_reset:
|
|
iounmap ( intel->regs );
|
|
err_ioremap:
|
|
netdev_nullify ( netdev );
|
|
netdev_put ( netdev );
|
|
err_alloc:
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* Remove PCI device
|
|
*
|
|
* @v pci PCI device
|
|
*/
|
|
static void intel_remove ( struct pci_device *pci ) {
|
|
struct net_device *netdev = pci_get_drvdata ( pci );
|
|
struct intel_nic *intel = netdev->priv;
|
|
|
|
/* Unregister network device */
|
|
unregister_netdev ( netdev );
|
|
|
|
/* Reset the NIC */
|
|
intel_reset ( intel );
|
|
|
|
/* Free network device */
|
|
iounmap ( intel->regs );
|
|
netdev_nullify ( netdev );
|
|
netdev_put ( netdev );
|
|
}
|
|
|
|
/** Intel PCI device IDs */
|
|
static struct pci_device_id intel_nics[] = {
|
|
PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
|
|
PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
|
|
PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
|
|
PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
|
|
PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", INTEL_VMWARE ),
|
|
PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
|
|
PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
|
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PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
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PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
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PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
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PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
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PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
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PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
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PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
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PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
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PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
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PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
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PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
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PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
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PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
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PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
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PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
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PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
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PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
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PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
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PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
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PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
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PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
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PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
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PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
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PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
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PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
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PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
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PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
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PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
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PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
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PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
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PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
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PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
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PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
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PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
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PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
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PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
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PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2", 0 ),
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PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2", 0 ),
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PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2", 0 ),
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PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
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PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
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PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
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PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
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PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
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PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
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PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
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PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
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PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
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PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
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PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
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PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
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PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
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PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
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PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
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PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
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PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
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PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
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PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
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PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
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PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
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PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
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PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", INTEL_PBS_ERRATA ),
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PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
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PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
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PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
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PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
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PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
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PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
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PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
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PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
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PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
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PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
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PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
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PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
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PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", INTEL_NO_ASDE ),
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PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
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PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
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PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
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PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
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PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
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PCI_ROM ( 0x8086, 0x1539, "i211", "I211", 0 ),
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PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217-LM", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x153b, "i217v", "I217-V", 0 ),
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PCI_ROM ( 0x8086, 0x1559, "i218v", "I218-V", 0),
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PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218-LM", 0),
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PCI_ROM ( 0x8086, 0x156f, "i219lm", "I219-LM", 0 ),
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PCI_ROM ( 0x8086, 0x1570, "i219v", "I219-V", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x157b, "i210-2", "I210", 0 ),
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PCI_ROM ( 0x8086, 0x15a0, "i218lm-2", "I218-LM", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15a1, "i218v-2", "I218-V", 0 ),
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PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15a3, "i218v-3", "I218-V", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15b7, "i219lm-2", "I219-LM (2)", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15b8, "i219v-2", "I219-V (2)", 0 ),
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PCI_ROM ( 0x8086, 0x15b9, "i219lm-3", "I219-LM (3)", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15d6, "i219v-5", "I219-V (5)", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15d7, "i219lm-4", "I219-LM (4)", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15d8, "i219v-4", "I219-V (4)", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x15e3, "i219lm-5", "I219-LM (5)", INTEL_NO_PHY_RST ),
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PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
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PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
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};
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/** Intel PCI driver */
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struct pci_driver intel_driver __pci_driver = {
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.ids = intel_nics,
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.id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
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.probe = intel_probe,
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.remove = intel_remove,
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};
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