93f1d69a77
Reported-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
930 lines
25 KiB
C
930 lines
25 KiB
C
/*
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* Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <stdint.h>
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#include <string.h>
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#include <unistd.h>
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#include <errno.h>
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#include <byteswap.h>
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#include <ipxe/netdevice.h>
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#include <ipxe/ethernet.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/iobuf.h>
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#include <ipxe/malloc.h>
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#include <ipxe/pci.h>
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#include <ipxe/nvs.h>
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#include <ipxe/bitbash.h>
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#include <ipxe/spi_bit.h>
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#include <ipxe/threewire.h>
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#include "natsemi.h"
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/** @file
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*
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* National Semiconductor "MacPhyter" network card driver
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*
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* Based on the following datasheets:
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*
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* http://www.ti.com/lit/ds/symlink/dp83820.pdf
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* http://www.datasheets.org.uk/indexdl/Datasheet-03/DSA0041338.pdf
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*
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*/
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/******************************************************************************
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*
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* EEPROM interface
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*
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******************************************************************************
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*/
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/** Pin mapping for SPI bit-bashing interface */
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static const uint8_t natsemi_eeprom_bits[] = {
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[SPI_BIT_SCLK] = NATSEMI_MEAR_EECLK,
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[SPI_BIT_MOSI] = NATSEMI_MEAR_EEDI,
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[SPI_BIT_MISO] = NATSEMI_MEAR_EEDO,
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[SPI_BIT_SS(0)] = NATSEMI_MEAR_EESEL,
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};
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/**
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* Read input bit
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*
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* @v basher Bit-bashing interface
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* @v bit_id Bit number
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* @ret zero Input is a logic 0
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* @ret non-zero Input is a logic 1
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*/
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static int natsemi_spi_read_bit ( struct bit_basher *basher,
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unsigned int bit_id ) {
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struct natsemi_nic *natsemi = container_of ( basher, struct natsemi_nic,
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spibit.basher );
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uint32_t mask = natsemi_eeprom_bits[bit_id];
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uint32_t reg;
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DBG_DISABLE ( DBGLVL_IO );
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reg = readl ( natsemi->regs + NATSEMI_MEAR );
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DBG_ENABLE ( DBGLVL_IO );
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return ( reg & mask );
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}
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/**
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* Set/clear output bit
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*
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* @v basher Bit-bashing interface
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* @v bit_id Bit number
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* @v data Value to write
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*/
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static void natsemi_spi_write_bit ( struct bit_basher *basher,
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unsigned int bit_id, unsigned long data ) {
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struct natsemi_nic *natsemi = container_of ( basher, struct natsemi_nic,
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spibit.basher );
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uint32_t mask = natsemi_eeprom_bits[bit_id];
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uint32_t reg;
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DBG_DISABLE ( DBGLVL_IO );
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reg = readl ( natsemi->regs + NATSEMI_MEAR );
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reg &= ~mask;
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reg |= ( data & mask );
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writel ( reg, natsemi->regs + NATSEMI_MEAR );
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DBG_ENABLE ( DBGLVL_IO );
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}
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/** SPI bit-bashing interface */
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static struct bit_basher_operations natsemi_basher_ops = {
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.read = natsemi_spi_read_bit,
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.write = natsemi_spi_write_bit,
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};
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/**
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* Initialise EEPROM
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*
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* @v natsemi National Semiconductor device
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*/
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static void natsemi_init_eeprom ( struct natsemi_nic *natsemi ) {
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/* Initialise SPI bit-bashing interface */
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natsemi->spibit.basher.op = &natsemi_basher_ops;
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natsemi->spibit.bus.mode = SPI_MODE_THREEWIRE;
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natsemi->spibit.endianness =
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( ( natsemi->flags & NATSEMI_EEPROM_LITTLE_ENDIAN ) ?
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SPI_BIT_LITTLE_ENDIAN : SPI_BIT_BIG_ENDIAN );
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init_spi_bit_basher ( &natsemi->spibit );
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/* Initialise EEPROM device */
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init_at93c06 ( &natsemi->eeprom, 16 );
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natsemi->eeprom.bus = &natsemi->spibit.bus;
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}
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/**
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* Get hardware address from sane EEPROM data
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*
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* @v natsemi National Semiconductor device
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* @v eeprom EEPROM data
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* @v hw_addr Hardware address to fill in
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*/
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static void natsemi_hwaddr_sane ( struct natsemi_nic *natsemi,
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const uint16_t *eeprom, uint16_t *hw_addr ) {
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int i;
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/* Copy MAC address from EEPROM data */
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for ( i = ( ( ETH_ALEN / 2 ) - 1 ) ; i >= 0 ; i-- )
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*(hw_addr++) = eeprom[ NATSEMI_EEPROM_MAC_SANE + i ];
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DBGC ( natsemi, "NATSEMI %p has sane EEPROM layout\n", natsemi );
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}
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/**
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* Get hardware address from insane EEPROM data
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*
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* @v natsemi National Semiconductor device
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* @v eeprom EEPROM data
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* @v hw_addr Hardware address to fill in
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*/
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static void natsemi_hwaddr_insane ( struct natsemi_nic *natsemi,
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const uint16_t *eeprom,
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uint16_t *hw_addr ) {
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unsigned int i;
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unsigned int offset;
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uint16_t word;
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/* Copy MAC address from EEPROM data */
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for ( i = 0 ; i < ( ETH_ALEN / 2 ) ; i++ ) {
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offset = ( NATSEMI_EEPROM_MAC_INSANE + i );
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word = ( ( le16_to_cpu ( eeprom[ offset ] ) >> 15 ) |
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( le16_to_cpu ( eeprom[ offset + 1 ] << 1 ) ) );
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hw_addr[i] = cpu_to_le16 ( word );
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}
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DBGC ( natsemi, "NATSEMI %p has insane EEPROM layout\n", natsemi );
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}
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/**
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* Get hardware address from EEPROM
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*
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* @v natsemi National Semiconductor device
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* @v hw_addr Hardware address to fill in
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* @ret rc Return status code
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*/
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static int natsemi_hwaddr ( struct natsemi_nic *natsemi, void *hw_addr ) {
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uint16_t buf[NATSEMI_EEPROM_SIZE];
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void ( * extract ) ( struct natsemi_nic *natsemi,
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const uint16_t *eeprom, uint16_t *hw_addr );
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int rc;
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/* Read EEPROM contents */
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if ( ( rc = nvs_read ( &natsemi->eeprom.nvs, 0, buf,
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sizeof ( buf ) ) ) != 0 ) {
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DBGC ( natsemi, "NATSEMI %p could not read EEPROM: %s\n",
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natsemi, strerror ( rc ) );
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return rc;
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}
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DBGC2 ( natsemi, "NATSEMI %p EEPROM contents:\n", natsemi );
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DBGC2_HDA ( natsemi, 0, buf, sizeof ( buf ) );
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/* Extract MAC address from EEPROM contents */
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extract = ( ( natsemi->flags & NATSEMI_EEPROM_INSANE ) ?
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natsemi_hwaddr_insane : natsemi_hwaddr_sane );
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extract ( natsemi, buf, hw_addr );
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return 0;
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}
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/******************************************************************************
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*
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* Device reset
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*
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******************************************************************************
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*/
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/**
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* Reset controller chip
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*
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* @v natsemi National Semiconductor device
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* @ret rc Return status code
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*/
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static int natsemi_soft_reset ( struct natsemi_nic *natsemi ) {
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unsigned int i;
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/* Initiate reset */
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writel ( NATSEMI_CR_RST, natsemi->regs + NATSEMI_CR );
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/* Wait for reset to complete */
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for ( i = 0 ; i < NATSEMI_RESET_MAX_WAIT_MS ; i++ ) {
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/* If reset is not complete, delay 1ms and retry */
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if ( readl ( natsemi->regs + NATSEMI_CR ) & NATSEMI_CR_RST ) {
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mdelay ( 1 );
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continue;
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}
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return 0;
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}
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DBGC ( natsemi, "NATSEMI %p timed out waiting for reset\n", natsemi );
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return -ETIMEDOUT;
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}
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/**
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* Reload configuration from EEPROM
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*
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* @v natsemi National Semiconductor device
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* @ret rc Return status code
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*/
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static int natsemi_reload_config ( struct natsemi_nic *natsemi ) {
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unsigned int i;
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/* Initiate reload */
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writel ( NATSEMI_PTSCR_EELOAD_EN, natsemi->regs + NATSEMI_PTSCR );
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/* Wait for reload to complete */
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for ( i = 0 ; i < NATSEMI_EELOAD_MAX_WAIT_MS ; i++ ) {
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/* If reload is not complete, delay 1ms and retry */
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if ( readl ( natsemi->regs + NATSEMI_PTSCR ) &
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NATSEMI_PTSCR_EELOAD_EN ) {
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mdelay ( 1 );
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continue;
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}
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return 0;
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}
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DBGC ( natsemi, "NATSEMI %p timed out waiting for configuration "
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"reload\n", natsemi );
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return -ETIMEDOUT;
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}
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/**
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* Reset hardware
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*
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* @v natsemi National Semiconductor device
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* @ret rc Return status code
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*/
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static int natsemi_reset ( struct natsemi_nic *natsemi ) {
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uint32_t cfg;
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int rc;
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/* Perform soft reset */
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if ( ( rc = natsemi_soft_reset ( natsemi ) ) != 0 )
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return rc;
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/* Reload configuration from EEPROM */
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if ( ( rc = natsemi_reload_config ( natsemi ) ) != 0 )
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return rc;
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/* Configure 64-bit operation, if applicable */
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cfg = readl ( natsemi->regs + NATSEMI_CFG );
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if ( natsemi->flags & NATSEMI_64BIT ) {
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cfg |= ( NATSEMI_CFG_M64ADDR | NATSEMI_CFG_EXTSTS_EN );
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if ( ! ( cfg & NATSEMI_CFG_PCI64_DET ) )
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cfg &= ~NATSEMI_CFG_DATA64_EN;
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}
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writel ( cfg, natsemi->regs + NATSEMI_CFG );
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/* Invalidate link status cache to force an update */
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natsemi->cfg = ~cfg;
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DBGC ( natsemi, "NATSEMI %p using configuration %08x\n",
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natsemi, cfg );
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return 0;
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}
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/******************************************************************************
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*
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* Link state
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*
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******************************************************************************
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*/
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/**
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* Check link state
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*
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* @v netdev Network device
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*/
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static void natsemi_check_link ( struct net_device *netdev ) {
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struct natsemi_nic *natsemi = netdev->priv;
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uint32_t cfg;
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/* Read link status */
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cfg = readl ( natsemi->regs + NATSEMI_CFG );
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/* Do nothing unless link status has changed */
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if ( cfg == natsemi->cfg )
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return;
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/* Set gigabit mode (if applicable) */
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if ( natsemi->flags & NATSEMI_1000 ) {
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cfg &= ~NATSEMI_CFG_MODE_1000;
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if ( ! ( cfg & NATSEMI_CFG_SPDSTS1 ) )
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cfg |= NATSEMI_CFG_MODE_1000;
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writel ( cfg, natsemi->regs + NATSEMI_CFG );
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}
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/* Update link status */
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natsemi->cfg = cfg;
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DBGC ( natsemi, "NATSEMI %p link status is %08x\n", natsemi, cfg );
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/* Update network device */
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if ( cfg & NATSEMI_CFG_LNKSTS ) {
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netdev_link_up ( netdev );
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} else {
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netdev_link_down ( netdev );
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}
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}
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/******************************************************************************
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*
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* Network device interface
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*
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******************************************************************************
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*/
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/**
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* Set perfect match filter address
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*
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* @v natsemi National Semiconductor device
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* @v mac MAC address
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*/
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static void natsemi_pmatch ( struct natsemi_nic *natsemi, const void *mac ) {
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const uint16_t *pmatch = mac;
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uint32_t rfcr;
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unsigned int rfaddr;
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unsigned int i;
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for ( i = 0 ; i < ETH_ALEN ; i += sizeof ( *pmatch ) ) {
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/* Select receive filter register address */
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rfaddr = ( NATSEMI_RFADDR_PMATCH_BASE + i );
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rfcr = readl ( natsemi->regs + NATSEMI_RFCR );
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rfcr &= ~NATSEMI_RFCR_RFADDR_MASK;
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rfcr |= NATSEMI_RFCR_RFADDR ( rfaddr );
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writel ( rfcr, natsemi->regs + NATSEMI_RFCR );
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/* Write receive filter data */
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writel ( ( le16_to_cpu ( *(pmatch++) ) | NATSEMI_RFDR_BMASK ),
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natsemi->regs + NATSEMI_RFDR );
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}
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}
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/**
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* Create descriptor ring
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*
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* @v natsemi National Semiconductor device
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* @v ring Descriptor ring
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* @ret rc Return status code
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*/
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static int natsemi_create_ring ( struct natsemi_nic *natsemi,
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struct natsemi_ring *ring ) {
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size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
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union natsemi_descriptor *desc;
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union natsemi_descriptor *linked_desc;
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physaddr_t address;
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physaddr_t link;
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size_t offset;
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unsigned int i;
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int rc;
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/* Calculate descriptor offset */
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offset = ( ( natsemi->flags & NATSEMI_64BIT ) ? 0 :
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offsetof ( typeof ( desc[i].d32pad ), d32 ) );
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/* Allocate descriptor ring. Align ring on its own size to
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* ensure that it can't possibly cross the boundary of 32-bit
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* address space.
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*/
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ring->desc = malloc_dma ( len, len );
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if ( ! ring->desc ) {
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rc = -ENOMEM;
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goto err_alloc;
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}
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address = ( virt_to_bus ( ring->desc ) + offset );
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/* Check address is usable by card */
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if ( ! natsemi_address_ok ( natsemi, address ) ) {
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DBGC ( natsemi, "NATSEMI %p cannot support 64-bit ring "
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"address\n", natsemi );
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rc = -ENOTSUP;
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goto err_64bit;
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}
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/* Initialise descriptor ring */
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memset ( ring->desc, 0, len );
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for ( i = 0 ; i < ring->count ; i++ ) {
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linked_desc = &ring->desc [ ( i + 1 ) % ring->count ];
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link = ( virt_to_bus ( linked_desc ) + offset );
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if ( natsemi->flags & NATSEMI_64BIT ) {
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ring->desc[i].d64.link = cpu_to_le64 ( link );
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} else {
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ring->desc[i].d32pad.d32.link = cpu_to_le32 ( link );
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}
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}
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/* Program ring address */
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writel ( ( address & 0xffffffffUL ), natsemi->regs + ring->reg );
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if ( natsemi->flags & NATSEMI_64BIT ) {
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if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
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writel ( ( ( ( uint64_t ) address ) >> 32 ),
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natsemi->regs + ring->reg + 4 );
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} else {
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writel ( 0, natsemi->regs + ring->reg + 4 );
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}
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}
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DBGC ( natsemi, "NATSEMI %p ring %02x is at [%08llx,%08llx)\n",
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natsemi, ring->reg,
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( ( unsigned long long ) virt_to_bus ( ring->desc ) ),
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( ( unsigned long long ) virt_to_bus ( ring->desc ) + len ) );
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return 0;
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err_64bit:
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free_dma ( ring->desc, len );
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ring->desc = NULL;
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err_alloc:
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return rc;
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}
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/**
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* Destroy descriptor ring
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*
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* @v natsemi National Semiconductor device
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* @v ring Descriptor ring
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*/
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static void natsemi_destroy_ring ( struct natsemi_nic *natsemi,
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struct natsemi_ring *ring ) {
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size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
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/* Clear ring address */
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writel ( 0, natsemi->regs + ring->reg );
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if ( natsemi->flags & NATSEMI_64BIT )
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writel ( 0, natsemi->regs + ring->reg + 4 );
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/* Free descriptor ring */
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free_dma ( ring->desc, len );
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ring->desc = NULL;
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ring->prod = 0;
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ring->cons = 0;
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}
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/**
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* Refill receive descriptor ring
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*
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* @v netdev Network device
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*/
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static void natsemi_refill_rx ( struct net_device *netdev ) {
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struct natsemi_nic *natsemi = netdev->priv;
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union natsemi_descriptor *rx;
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struct io_buffer *iobuf;
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unsigned int rx_idx;
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physaddr_t address;
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while ( ( natsemi->rx.prod - natsemi->rx.cons ) < NATSEMI_NUM_RX_DESC ){
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/* Allocate I/O buffer */
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iobuf = alloc_iob ( NATSEMI_RX_MAX_LEN );
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if ( ! iobuf ) {
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/* Wait for next refill */
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return;
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}
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/* Check address is usable by card */
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address = virt_to_bus ( iobuf->data );
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|
if ( ! natsemi_address_ok ( natsemi, address ) ) {
|
|
DBGC ( natsemi, "NATSEMI %p cannot support 64-bit RX "
|
|
"buffer address\n", natsemi );
|
|
netdev_rx_err ( netdev, iobuf, -ENOTSUP );
|
|
return;
|
|
}
|
|
|
|
/* Get next receive descriptor */
|
|
rx_idx = ( natsemi->rx.prod++ % NATSEMI_NUM_RX_DESC );
|
|
rx = &natsemi->rx.desc[rx_idx];
|
|
|
|
/* Populate receive descriptor */
|
|
if ( natsemi->flags & NATSEMI_64BIT ) {
|
|
rx->d64.bufptr = cpu_to_le64 ( address );
|
|
} else {
|
|
rx->d32pad.d32.bufptr = cpu_to_le32 ( address );
|
|
}
|
|
wmb();
|
|
rx->common.cmdsts = cpu_to_le32 ( NATSEMI_DESC_INTR |
|
|
NATSEMI_RX_MAX_LEN );
|
|
wmb();
|
|
|
|
/* Record I/O buffer */
|
|
assert ( natsemi->rx_iobuf[rx_idx] == NULL );
|
|
natsemi->rx_iobuf[rx_idx] = iobuf;
|
|
|
|
/* Notify card that there are descriptors available */
|
|
writel ( NATSEMI_CR_RXE, natsemi->regs + NATSEMI_CR );
|
|
|
|
DBGC2 ( natsemi, "NATSEMI %p RX %d is [%llx,%llx)\n", natsemi,
|
|
rx_idx, ( ( unsigned long long ) address ),
|
|
( ( unsigned long long ) address + NATSEMI_RX_MAX_LEN));
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Open network device
|
|
*
|
|
* @v netdev Network device
|
|
* @ret rc Return status code
|
|
*/
|
|
static int natsemi_open ( struct net_device *netdev ) {
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
int rc;
|
|
|
|
/* Set MAC address */
|
|
natsemi_pmatch ( natsemi, netdev->ll_addr );
|
|
|
|
/* Create transmit descriptor ring */
|
|
if ( ( rc = natsemi_create_ring ( natsemi, &natsemi->tx ) ) != 0 )
|
|
goto err_create_tx;
|
|
|
|
/* Set transmit configuration */
|
|
writel ( ( NATSEMI_TXCFG_CSI | NATSEMI_TXCFG_HBI | NATSEMI_TXCFG_ATP |
|
|
NATSEMI_TXCFG_ECRETRY | NATSEMI_TXCFG_MXDMA_DEFAULT |
|
|
NATSEMI_TXCFG_FLTH_DEFAULT | NATSEMI_TXCFG_DRTH_DEFAULT ),
|
|
( natsemi->regs + ( ( natsemi->flags & NATSEMI_64BIT ) ?
|
|
NATSEMI_TXCFG_64 : NATSEMI_TXCFG_32 ) ) );
|
|
|
|
/* Create receive descriptor ring */
|
|
if ( ( rc = natsemi_create_ring ( natsemi, &natsemi->rx ) ) != 0 )
|
|
goto err_create_rx;
|
|
|
|
/* Set receive configuration */
|
|
writel ( ( NATSEMI_RXCFG_ARP | NATSEMI_RXCFG_ATX | NATSEMI_RXCFG_ALP |
|
|
NATSEMI_RXCFG_MXDMA_DEFAULT | NATSEMI_RXCFG_DRTH_DEFAULT ),
|
|
( natsemi->regs + ( ( natsemi->flags & NATSEMI_64BIT ) ?
|
|
NATSEMI_RXCFG_64 : NATSEMI_RXCFG_32 ) ) );
|
|
|
|
/* Set receive filter configuration */
|
|
writel ( ( NATSEMI_RFCR_RFEN | NATSEMI_RFCR_AAB | NATSEMI_RFCR_AAM |
|
|
NATSEMI_RFCR_AAU ), natsemi->regs + NATSEMI_RFCR );
|
|
|
|
/* Fill receive ring */
|
|
natsemi_refill_rx ( netdev );
|
|
|
|
/* Unmask transmit and receive interrupts. (Interrupts will
|
|
* not be generated unless enabled via the IER.)
|
|
*/
|
|
writel ( ( NATSEMI_IRQ_TXDESC | NATSEMI_IRQ_RXDESC ),
|
|
natsemi->regs + NATSEMI_IMR );
|
|
|
|
/* Update link state */
|
|
natsemi_check_link ( netdev );
|
|
|
|
return 0;
|
|
|
|
natsemi_destroy_ring ( natsemi, &natsemi->rx );
|
|
err_create_rx:
|
|
natsemi_destroy_ring ( natsemi, &natsemi->tx );
|
|
err_create_tx:
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* Close network device
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
static void natsemi_close ( struct net_device *netdev ) {
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
unsigned int i;
|
|
|
|
/* Mask transmit and receive interrupts */
|
|
writel ( 0, natsemi->regs + NATSEMI_IMR );
|
|
|
|
/* Reset and disable transmitter and receiver */
|
|
writel ( ( NATSEMI_CR_RXR | NATSEMI_CR_TXR ),
|
|
natsemi->regs + NATSEMI_CR );
|
|
|
|
/* Discard any unused receive buffers */
|
|
for ( i = 0 ; i < NATSEMI_NUM_RX_DESC ; i++ ) {
|
|
if ( natsemi->rx_iobuf[i] )
|
|
free_iob ( natsemi->rx_iobuf[i] );
|
|
natsemi->rx_iobuf[i] = NULL;
|
|
}
|
|
|
|
/* Destroy receive descriptor ring */
|
|
natsemi_destroy_ring ( natsemi, &natsemi->rx );
|
|
|
|
/* Destroy transmit descriptor ring */
|
|
natsemi_destroy_ring ( natsemi, &natsemi->tx );
|
|
}
|
|
|
|
/**
|
|
* Transmit packet
|
|
*
|
|
* @v netdev Network device
|
|
* @v iobuf I/O buffer
|
|
* @ret rc Return status code
|
|
*/
|
|
static int natsemi_transmit ( struct net_device *netdev,
|
|
struct io_buffer *iobuf ) {
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
union natsemi_descriptor *tx;
|
|
unsigned int tx_idx;
|
|
physaddr_t address;
|
|
|
|
/* Check address is usable by card */
|
|
address = virt_to_bus ( iobuf->data );
|
|
if ( ! natsemi_address_ok ( natsemi, address ) ) {
|
|
DBGC ( natsemi, "NATSEMI %p cannot support 64-bit TX buffer "
|
|
"address\n", natsemi );
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
/* Get next transmit descriptor */
|
|
if ( ( natsemi->tx.prod - natsemi->tx.cons ) >= NATSEMI_NUM_TX_DESC ) {
|
|
DBGC ( natsemi, "NATSEMI %p out of transmit descriptors\n",
|
|
natsemi );
|
|
return -ENOBUFS;
|
|
}
|
|
tx_idx = ( natsemi->tx.prod++ % NATSEMI_NUM_TX_DESC );
|
|
tx = &natsemi->tx.desc[tx_idx];
|
|
|
|
/* Populate transmit descriptor */
|
|
if ( natsemi->flags & NATSEMI_64BIT ) {
|
|
tx->d64.bufptr = cpu_to_le64 ( address );
|
|
} else {
|
|
tx->d32pad.d32.bufptr = cpu_to_le32 ( address );
|
|
}
|
|
wmb();
|
|
tx->common.cmdsts = cpu_to_le32 ( NATSEMI_DESC_OWN | NATSEMI_DESC_INTR |
|
|
iob_len ( iobuf ) );
|
|
wmb();
|
|
|
|
/* Notify card that there are packets ready to transmit */
|
|
writel ( NATSEMI_CR_TXE, natsemi->regs + NATSEMI_CR );
|
|
|
|
DBGC2 ( natsemi, "NATSEMI %p TX %d is [%llx,%llx)\n", natsemi, tx_idx,
|
|
( ( unsigned long long ) address ),
|
|
( ( unsigned long long ) address + iob_len ( iobuf ) ) );
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Poll for completed packets
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
static void natsemi_poll_tx ( struct net_device *netdev ) {
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
union natsemi_descriptor *tx;
|
|
unsigned int tx_idx;
|
|
|
|
/* Check for completed packets */
|
|
while ( natsemi->tx.cons != natsemi->tx.prod ) {
|
|
|
|
/* Get next transmit descriptor */
|
|
tx_idx = ( natsemi->tx.cons % NATSEMI_NUM_TX_DESC );
|
|
tx = &natsemi->tx.desc[tx_idx];
|
|
|
|
/* Stop if descriptor is still in use */
|
|
if ( tx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OWN ) )
|
|
return;
|
|
|
|
/* Complete TX descriptor */
|
|
if ( tx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OK ) ) {
|
|
DBGC2 ( natsemi, "NATSEMI %p TX %d complete\n",
|
|
natsemi, tx_idx );
|
|
netdev_tx_complete_next ( netdev );
|
|
} else {
|
|
DBGC ( natsemi, "NATSEMI %p TX %d completion error "
|
|
"(%08x)\n", natsemi, tx_idx,
|
|
le32_to_cpu ( tx->common.cmdsts ) );
|
|
netdev_tx_complete_next_err ( netdev, -EIO );
|
|
}
|
|
natsemi->tx.cons++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Poll for received packets
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
static void natsemi_poll_rx ( struct net_device *netdev ) {
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
union natsemi_descriptor *rx;
|
|
struct io_buffer *iobuf;
|
|
unsigned int rx_idx;
|
|
size_t len;
|
|
|
|
/* Check for received packets */
|
|
while ( natsemi->rx.cons != natsemi->rx.prod ) {
|
|
|
|
/* Get next receive descriptor */
|
|
rx_idx = ( natsemi->rx.cons % NATSEMI_NUM_RX_DESC );
|
|
rx = &natsemi->rx.desc[rx_idx];
|
|
|
|
/* Stop if descriptor is still in use */
|
|
if ( ! ( rx->common.cmdsts & NATSEMI_DESC_OWN ) )
|
|
return;
|
|
|
|
/* Populate I/O buffer */
|
|
iobuf = natsemi->rx_iobuf[rx_idx];
|
|
natsemi->rx_iobuf[rx_idx] = NULL;
|
|
len = ( le32_to_cpu ( rx->common.cmdsts ) &
|
|
NATSEMI_DESC_SIZE_MASK );
|
|
iob_put ( iobuf, len - 4 /* strip CRC */ );
|
|
|
|
/* Hand off to network stack */
|
|
if ( rx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OK ) ) {
|
|
DBGC2 ( natsemi, "NATSEMI %p RX %d complete (length "
|
|
"%zd)\n", natsemi, rx_idx, len );
|
|
netdev_rx ( netdev, iobuf );
|
|
} else {
|
|
DBGC ( natsemi, "NATSEMI %p RX %d error (length %zd, "
|
|
"status %08x)\n", natsemi, rx_idx, len,
|
|
le32_to_cpu ( rx->common.cmdsts ) );
|
|
netdev_rx_err ( netdev, iobuf, -EIO );
|
|
}
|
|
natsemi->rx.cons++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Poll for completed and received packets
|
|
*
|
|
* @v netdev Network device
|
|
*/
|
|
static void natsemi_poll ( struct net_device *netdev ) {
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
uint32_t isr;
|
|
|
|
/* Poll for link state. The PHY interrupt seems not to
|
|
* function as expected, and polling for the link state is
|
|
* only a single register read.
|
|
*/
|
|
natsemi_check_link ( netdev );
|
|
|
|
/* Check for and acknowledge interrupts */
|
|
isr = readl ( natsemi->regs + NATSEMI_ISR );
|
|
if ( ! isr )
|
|
return;
|
|
|
|
/* Poll for TX completions, if applicable */
|
|
if ( isr & NATSEMI_IRQ_TXDESC )
|
|
natsemi_poll_tx ( netdev );
|
|
|
|
/* Poll for RX completionsm, if applicable */
|
|
if ( isr & NATSEMI_IRQ_RXDESC )
|
|
natsemi_poll_rx ( netdev );
|
|
|
|
/* Refill RX ring */
|
|
natsemi_refill_rx ( netdev );
|
|
}
|
|
|
|
/**
|
|
* Enable or disable interrupts
|
|
*
|
|
* @v netdev Network device
|
|
* @v enable Interrupts should be enabled
|
|
*/
|
|
static void natsemi_irq ( struct net_device *netdev, int enable ) {
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
|
|
/* Enable or disable interrupts */
|
|
writel ( ( enable ? NATSEMI_IER_IE : 0 ), natsemi->regs + NATSEMI_IER );
|
|
}
|
|
|
|
/** National Semiconductor network device operations */
|
|
static struct net_device_operations natsemi_operations = {
|
|
.open = natsemi_open,
|
|
.close = natsemi_close,
|
|
.transmit = natsemi_transmit,
|
|
.poll = natsemi_poll,
|
|
.irq = natsemi_irq,
|
|
};
|
|
|
|
/******************************************************************************
|
|
*
|
|
* PCI interface
|
|
*
|
|
******************************************************************************
|
|
*/
|
|
|
|
/**
|
|
* Probe PCI device
|
|
*
|
|
* @v pci PCI device
|
|
* @ret rc Return status code
|
|
*/
|
|
static int natsemi_probe ( struct pci_device *pci ) {
|
|
struct net_device *netdev;
|
|
struct natsemi_nic *natsemi;
|
|
int rc;
|
|
|
|
/* Allocate and initialise net device */
|
|
netdev = alloc_etherdev ( sizeof ( *natsemi ) );
|
|
if ( ! netdev ) {
|
|
rc = -ENOMEM;
|
|
goto err_alloc;
|
|
}
|
|
netdev_init ( netdev, &natsemi_operations );
|
|
natsemi = netdev->priv;
|
|
pci_set_drvdata ( pci, netdev );
|
|
netdev->dev = &pci->dev;
|
|
memset ( natsemi, 0, sizeof ( *natsemi ) );
|
|
natsemi->flags = pci->id->driver_data;
|
|
natsemi_init_ring ( &natsemi->tx, NATSEMI_NUM_TX_DESC, NATSEMI_TXDP );
|
|
natsemi_init_ring ( &natsemi->rx, NATSEMI_NUM_RX_DESC, NATSEMI_RXDP );
|
|
|
|
/* Fix up PCI device */
|
|
adjust_pci_device ( pci );
|
|
|
|
/* Map registers */
|
|
natsemi->regs = ioremap ( pci->membase, NATSEMI_BAR_SIZE );
|
|
|
|
/* Reset the NIC */
|
|
if ( ( rc = natsemi_reset ( natsemi ) ) != 0 )
|
|
goto err_reset;
|
|
|
|
/* Initialise EEPROM */
|
|
natsemi_init_eeprom ( natsemi );
|
|
|
|
/* Read initial MAC address */
|
|
if ( ( rc = natsemi_hwaddr ( natsemi, netdev->hw_addr ) ) != 0 )
|
|
goto err_hwaddr;
|
|
|
|
/* Register network device */
|
|
if ( ( rc = register_netdev ( netdev ) ) != 0 )
|
|
goto err_register_netdev;
|
|
|
|
/* Set initial link state */
|
|
natsemi_check_link ( netdev );
|
|
|
|
return 0;
|
|
|
|
unregister_netdev ( netdev );
|
|
err_register_netdev:
|
|
err_hwaddr:
|
|
natsemi_reset ( natsemi );
|
|
err_reset:
|
|
iounmap ( natsemi->regs );
|
|
netdev_nullify ( netdev );
|
|
netdev_put ( netdev );
|
|
err_alloc:
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* Remove PCI device
|
|
*
|
|
* @v pci PCI device
|
|
*/
|
|
static void natsemi_remove ( struct pci_device *pci ) {
|
|
struct net_device *netdev = pci_get_drvdata ( pci );
|
|
struct natsemi_nic *natsemi = netdev->priv;
|
|
|
|
/* Unregister network device */
|
|
unregister_netdev ( netdev );
|
|
|
|
/* Reset card */
|
|
natsemi_reset ( natsemi );
|
|
|
|
/* Free network device */
|
|
iounmap ( natsemi->regs );
|
|
netdev_nullify ( netdev );
|
|
netdev_put ( netdev );
|
|
}
|
|
|
|
/** Flags for DP83815 */
|
|
#define DP83815_FLAGS ( NATSEMI_EEPROM_LITTLE_ENDIAN | NATSEMI_EEPROM_INSANE )
|
|
|
|
/** Flags for DP83820 */
|
|
#define DP83820_FLAGS ( NATSEMI_64BIT | NATSEMI_1000 )
|
|
|
|
/** National Semiconductor PCI device IDs */
|
|
static struct pci_device_id natsemi_nics[] = {
|
|
PCI_ROM ( 0x100b, 0x0020, "dp83815", "DP83815", DP83815_FLAGS ),
|
|
PCI_ROM ( 0x100b, 0x0022, "dp83820", "DP83820", DP83820_FLAGS ),
|
|
};
|
|
|
|
/** National Semiconductor PCI driver */
|
|
struct pci_driver natsemi_driver __pci_driver = {
|
|
.ids = natsemi_nics,
|
|
.id_count = ( sizeof ( natsemi_nics ) / sizeof ( natsemi_nics[0] ) ),
|
|
.probe = natsemi_probe,
|
|
.remove = natsemi_remove,
|
|
};
|