836 lines
26 KiB
C
836 lines
26 KiB
C
/*
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* eepro100.c -- This file implements the eepro100 driver for etherboot.
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*
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*
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* Copyright (C) AW Computer Systems.
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* written by R.E.Wolff -- R.E.Wolff@BitWizard.nl
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*
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*
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* AW Computer Systems is contributing to the free software community
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* by paying for this driver and then putting the result under GPL.
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*
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* If you need a Linux device driver, please contact BitWizard for a
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* quote.
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* date version by what
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* Written: May 29 1997 V0.10 REW Initial revision.
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* changes: May 31 1997 V0.90 REW Works!
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* Jun 1 1997 V0.91 REW Cleanup
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* Jun 2 1997 V0.92 REW Add some code documentation
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* Jul 25 1997 V1.00 REW Tested by AW to work in a PROM
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* Cleanup for publication
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* Dez 11 2004 V1.10 Kiszka Add RX ring buffer support
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*
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* This is the etherboot intel etherexpress Pro/100B driver.
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*
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* It was written from scratch, with Donald Beckers eepro100.c kernel
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* driver as a guideline. Mostly the 82557 related definitions and the
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* lower level routines have been cut-and-pasted into this source.
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*
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* The driver was finished before Intel got the NDA out of the closet.
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* I still don't have the docs.
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*
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*
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* Datasheet is now published and available from
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* ftp://download.intel.com/design/network/manuals/8255X_OpenSDM.pdf
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* - Michael Brown
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* */
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/* Philosophy of this driver.
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*
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* Probing:
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*
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* Using the pci.c functions of the Etherboot code, the 82557 chip is detected.
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* It is verified that the BIOS initialized everything properly and if
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* something is missing it is done now.
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*
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*
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* Initialization:
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*
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*
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* The chip is then initialized to "know" its ethernet address, and to
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* start recieving packets. The Linux driver has a whole transmit and
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* recieve ring of buffers. This is neat if you need high performance:
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* you can write the buffers asynchronously to the chip reading the
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* buffers and transmitting them over the network. Performance is NOT
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* an issue here. We can boot a 400k kernel in about two
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* seconds. (Theory: 0.4 seconds). Booting a system is going to take
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* about half a minute anyway, so getting 10 times closer to the
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* theoretical limit is going to make a difference of a few percent. */
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/* Not totally true: busy networks can cause packet drops due to RX
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* buffer overflows. Fixed in V1.10 of this driver. [Kiszka] */
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/*
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*
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* Transmitting and recieving.
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*
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* We have only one transmit descriptor. It has two buffer descriptors:
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* one for the header, and the other for the data.
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* We have multiple receive buffers (currently: 4). The chip is told to
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* receive packets and suspend itself once it ran on the last free buffer.
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* The recieve (poll) routine simply looks at the current recieve buffer,
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* picks the packet if any, and releases this buffer again (classic ring
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* buffer concept). This helps to avoid packet drops on busy networks.
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*
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* Caveats:
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*
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* The Etherboot framework moves the code to the 48k segment from
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* 0x94000 to 0xa0000. There is just a little room between the end of
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* this driver and the 0xa0000 address. If you compile in too many
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* features, this will overflow.
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* The number under "hex" in the output of size that scrolls by while
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* compiling should be less than 8000. Maybe even the stack is up there,
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* so that you need even more headroom.
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*/
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/* The etherboot authors seem to dislike the argument ordering in
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* outb macros that Linux uses. I disklike the confusion that this
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* has caused even more.... This file uses the Linux argument ordering. */
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/* Sorry not us. It's inherited code from FreeBSD. [The authors] */
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#include "etherboot.h"
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#include "nic.h"
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#include <gpxe/ethernet.h>
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#include <gpxe/pci.h>
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#include "timer.h"
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static int ioaddr;
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enum speedo_offsets {
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SCBStatus = 0, SCBCmd = 2, /* Rx/Command Unit command and status. */
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SCBPointer = 4, /* General purpose pointer. */
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SCBPort = 8, /* Misc. commands and operands. */
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SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
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SCBCtrlMDI = 16, /* MDI interface control. */
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SCBEarlyRx = 20, /* Early receive byte count. */
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};
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enum SCBCmdBits {
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SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000,
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SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400,
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SCBTriggerIntr=0x0200, SCBMaskAll=0x0100,
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/* The rest are Rx and Tx commands. */
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CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, CUShowStats=0x0050,
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CUCmdBase=0x0060, /* CU Base address (set to zero) . */
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CUDumpStats=0x0070, /* Dump then reset stats counters. */
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RxStart=0x0001, RxResume=0x0002, RxAbort=0x0004, RxAddrLoad=0x0006,
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RxResumeNoResources=0x0007,
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};
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static int do_eeprom_cmd(int cmd, int cmd_len);
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void hd(void *where, int n);
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/***********************************************************************/
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/* I82557 related defines */
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/***********************************************************************/
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/* Serial EEPROM section.
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A "bit" grungy, but we work our way through bit-by-bit :->. */
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/* EEPROM_Ctrl bits. */
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#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
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#define EE_CS 0x02 /* EEPROM chip select. */
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#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
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#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
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#define EE_WRITE_0 0x4802
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#define EE_WRITE_1 0x4806
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#define EE_ENB (0x4800 | EE_CS)
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_READ_CMD 6
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/* The SCB accepts the following controls for the Tx and Rx units: */
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#define CU_START 0x0010
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#define CU_RESUME 0x0020
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#define CU_STATSADDR 0x0040
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#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
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#define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */
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#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
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#define RX_START 0x0001
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#define RX_RESUME 0x0002
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#define RX_ABORT 0x0004
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#define RX_ADDR_LOAD 0x0006
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#define RX_RESUMENR 0x0007
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#define INT_MASK 0x0100
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#define DRVR_INT 0x0200 /* Driver generated interrupt. */
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enum phy_chips { NonSuchPhy=0, I82553AB, I82553C, I82503, DP83840, S80C240,
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S80C24, PhyUndefined, DP83840A=10, };
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/* Commands that can be put in a command list entry. */
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enum commands {
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CmdNOp = 0,
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CmdIASetup = 1,
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CmdConfigure = 2,
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CmdMulticastList = 3,
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CmdTx = 4,
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CmdTDR = 5,
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CmdDump = 6,
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CmdDiagnose = 7,
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/* And some extra flags: */
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CmdSuspend = 0x4000, /* Suspend after completion. */
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CmdIntr = 0x2000, /* Interrupt after completion. */
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CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
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};
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/* How to wait for the command unit to accept a command.
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Typically this takes 0 ticks. */
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static inline void wait_for_cmd_done(int cmd_ioaddr)
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{
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int wait = 0;
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int delayed_cmd;
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do
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if (inb(cmd_ioaddr) == 0) return;
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while(++wait <= 100);
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delayed_cmd = inb(cmd_ioaddr);
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do
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if (inb(cmd_ioaddr) == 0) break;
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while(++wait <= 10000);
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printf("Command %2.2x was not immediately accepted, %d ticks!\n",
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delayed_cmd, wait);
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}
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/* Elements of the dump_statistics block. This block must be lword aligned. */
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static struct speedo_stats {
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u32 tx_good_frames;
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u32 tx_coll16_errs;
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u32 tx_late_colls;
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u32 tx_underruns;
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u32 tx_lost_carrier;
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u32 tx_deferred;
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u32 tx_one_colls;
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u32 tx_multi_colls;
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u32 tx_total_colls;
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u32 rx_good_frames;
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u32 rx_crc_errs;
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u32 rx_align_errs;
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u32 rx_resource_errs;
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u32 rx_overrun_errs;
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u32 rx_colls_errs;
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u32 rx_runt_errs;
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u32 done_marker;
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} lstats;
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/* A speedo3 TX buffer descriptor with two buffers... */
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static struct TxFD {
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volatile s16 status;
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s16 command;
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u32 link; /* void * */
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u32 tx_desc_addr; /* (almost) Always points to the tx_buf_addr element. */
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s32 count; /* # of TBD (=2), Tx start thresh., etc. */
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/* This constitutes two "TBD" entries: hdr and data */
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u32 tx_buf_addr0; /* void *, header of frame to be transmitted. */
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s32 tx_buf_size0; /* Length of Tx hdr. */
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u32 tx_buf_addr1; /* void *, data to be transmitted. */
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s32 tx_buf_size1; /* Length of Tx data. */
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} txfd;
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struct RxFD { /* Receive frame descriptor. */
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volatile s16 status;
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s16 command;
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u32 link; /* struct RxFD * */
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u32 rx_buf_addr; /* void * */
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u16 count;
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u16 size;
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char packet[1518];
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};
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static struct nic_operations eepro100_operations;
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#define RXFD_COUNT 4
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struct {
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struct RxFD rxfds[RXFD_COUNT];
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} eepro100_bufs __shared;
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#define rxfds eepro100_bufs.rxfds
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static unsigned int rxfd = 0;
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static int congenb = 0; /* Enable congestion control in the DP83840. */
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static int txfifo = 8; /* Tx FIFO threshold in 4 byte units, 0-15 */
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static int rxfifo = 8; /* Rx FIFO threshold, default 32 bytes. */
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static int txdmacount = 0; /* Tx DMA burst length, 0-127, default 0. */
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static int rxdmacount = 0; /* Rx DMA length, 0 means no preemption. */
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/* I don't understand a byte in this structure. It was copied from the
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* Linux kernel initialization for the eepro100. -- REW */
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static struct ConfCmd {
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s16 status;
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s16 command;
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u32 link;
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unsigned char data[22];
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} confcmd = {
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0, 0, 0, /* filled in later */
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{22, 0x08, 0, 0, 0, 0x80, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
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0, 0x2E, 0, 0x60, 0,
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0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
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0x3f, 0x05, }
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};
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/***********************************************************************/
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/* Locally used functions */
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/***********************************************************************/
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/* Support function: mdio_write
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*
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* This probably writes to the "physical media interface chip".
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* -- REW
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*/
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static int mdio_write(int phy_id, int location, int value)
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{
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int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */
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outl(0x04000000 | (location<<16) | (phy_id<<21) | value,
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ioaddr + SCBCtrlMDI);
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do {
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udelay(16);
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val = inl(ioaddr + SCBCtrlMDI);
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if (--boguscnt < 0) {
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printf(" mdio_write() timed out with val = %X.\n", val);
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break;
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}
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} while (! (val & 0x10000000));
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return val & 0xffff;
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}
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/* Support function: mdio_read
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*
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* This probably reads a register in the "physical media interface chip".
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* -- REW
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*/
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static int mdio_read(int phy_id, int location)
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{
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int val, boguscnt = 64*4; /* <64 usec. to complete, typ 27 ticks */
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outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI);
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do {
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udelay(16);
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val = inl(ioaddr + SCBCtrlMDI);
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if (--boguscnt < 0) {
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printf( " mdio_read() timed out with val = %X.\n", val);
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break;
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}
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} while (! (val & 0x10000000));
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return val & 0xffff;
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}
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/* The fixes for the code were kindly provided by Dragan Stancevic
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<visitor@valinux.com> to strictly follow Intel specifications of EEPROM
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access timing.
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The publicly available sheet 64486302 (sec. 3.1) specifies 1us access
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interval for serial EEPROM. However, it looks like that there is an
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additional requirement dictating larger udelay's in the code below.
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2000/05/24 SAW */
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static int do_eeprom_cmd(int cmd, int cmd_len)
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{
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unsigned retval = 0;
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long ee_addr = ioaddr + SCBeeprom;
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outw(EE_ENB, ee_addr); udelay(2);
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outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2);
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/* Shift the command bits out. */
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do {
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short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
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outw(dataval, ee_addr); udelay(2);
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outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2);
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retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
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} while (--cmd_len >= 0);
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outw(EE_ENB, ee_addr); udelay(2);
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/* Terminate the EEPROM access. */
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outw(EE_ENB & ~EE_CS, ee_addr);
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return retval;
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}
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#if 0
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static inline void whereami (const char *str)
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{
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printf ("%s\n", str);
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sleep (2);
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}
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#else
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#define whereami(s)
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#endif
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static void eepro100_irq(struct nic *nic __unused, irq_action_t action)
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{
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uint16_t enabled_mask = ( SCBMaskCmdDone | SCBMaskCmdIdle |
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SCBMaskEarlyRx | SCBMaskFlowCtl );
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switch ( action ) {
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case DISABLE :
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outw(SCBMaskAll, ioaddr + SCBCmd);
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break;
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case ENABLE :
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outw(enabled_mask, ioaddr + SCBCmd);
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break;
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case FORCE :
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outw(enabled_mask | SCBTriggerIntr, ioaddr + SCBCmd);
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break;
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}
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}
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/* function: eepro100_transmit
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* This transmits a packet.
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*
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* Arguments: char d[6]: destination ethernet address.
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* unsigned short t: ethernet protocol type.
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* unsigned short s: size of the data-part of the packet.
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* char *p: the data for the packet.
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* returns: void.
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*/
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static void eepro100_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
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{
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struct eth_hdr {
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unsigned char dst_addr[ETH_ALEN];
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unsigned char src_addr[ETH_ALEN];
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unsigned short type;
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} hdr;
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unsigned short status;
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int s1, s2;
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status = inw(ioaddr + SCBStatus);
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/* Acknowledge all of the current interrupt sources ASAP. */
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outw(status & 0xfc00, ioaddr + SCBStatus);
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#ifdef DEBUG
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printf ("transmitting type %hX packet (%d bytes). status = %hX, cmd=%hX\n",
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t, s, status, inw (ioaddr + SCBCmd));
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#endif
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memcpy (&hdr.dst_addr, d, ETH_ALEN);
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memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
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hdr.type = htons (t);
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txfd.status = 0;
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txfd.command = CmdSuspend | CmdTx | CmdTxFlex;
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txfd.link = virt_to_bus (&txfd);
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txfd.count = 0x02208000;
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txfd.tx_desc_addr = virt_to_bus(&txfd.tx_buf_addr0);
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txfd.tx_buf_addr0 = virt_to_bus (&hdr);
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txfd.tx_buf_size0 = sizeof (hdr);
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txfd.tx_buf_addr1 = virt_to_bus (p);
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txfd.tx_buf_size1 = s;
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#ifdef DEBUG
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printf ("txfd: \n");
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hd (&txfd, sizeof (txfd));
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#endif
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outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
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outb(CU_START, ioaddr + SCBCmd);
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wait_for_cmd_done(ioaddr + SCBCmd);
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s1 = inw (ioaddr + SCBStatus);
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load_timer2(10*TICKS_PER_MS); /* timeout 10 ms for transmit */
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while (!txfd.status && timer2_running())
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/* Wait */;
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s2 = inw (ioaddr + SCBStatus);
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#ifdef DEBUG
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printf ("s1 = %hX, s2 = %hX.\n", s1, s2);
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#endif
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}
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|
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/*
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* Sometimes the receiver stops making progress. This routine knows how to
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* get it going again, without losing packets or being otherwise nasty like
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* a chip reset would be. Previously the driver had a whole sequence
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* of if RxSuspended, if it's no buffers do one thing, if it's no resources,
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* do another, etc. But those things don't really matter. Separate logic
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* in the ISR provides for allocating buffers--the other half of operation
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|
* is just making sure the receiver is active. speedo_rx_soft_reset does that.
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|
* This problem with the old, more involved algorithm is shown up under
|
|
* ping floods on the order of 60K packets/second on a 100Mbps fdx network.
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|
*/
|
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static void
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speedo_rx_soft_reset(void)
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{
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int i;
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|
|
#ifdef DEBUG
|
|
printf("reset\n");
|
|
#endif
|
|
wait_for_cmd_done(ioaddr + SCBCmd);
|
|
/*
|
|
* Put the hardware into a known state.
|
|
*/
|
|
outb(RX_ABORT, ioaddr + SCBCmd);
|
|
|
|
for (i = 0; i < RXFD_COUNT; i++) {
|
|
rxfds[i].status = 0;
|
|
rxfds[i].rx_buf_addr = 0xffffffff;
|
|
rxfds[i].count = 0;
|
|
rxfds[i].size = 1528;
|
|
}
|
|
|
|
wait_for_cmd_done(ioaddr + SCBCmd);
|
|
|
|
outl(virt_to_bus(&rxfds[rxfd]), ioaddr + SCBPointer);
|
|
outb(RX_START, ioaddr + SCBCmd);
|
|
}
|
|
|
|
/* function: eepro100_poll / eth_poll
|
|
* This receives a packet from the network.
|
|
*
|
|
* Arguments: none
|
|
*
|
|
* returns: 1 if a packet was received.
|
|
* 0 if no packet was received.
|
|
* side effects:
|
|
* returns the packet in the array nic->packet.
|
|
* returns the length of the packet in nic->packetlen.
|
|
*/
|
|
|
|
static int eepro100_poll(struct nic *nic, int retrieve)
|
|
{
|
|
if (rxfds[rxfd].status) {
|
|
if (!retrieve)
|
|
return 1;
|
|
#ifdef DEBUG
|
|
printf("Got a packet: Len = %d, rxfd = %d.\n",
|
|
rxfds[rxfd].count & 0x3fff, rxfd);
|
|
#endif
|
|
/* First save the data from the rxfd */
|
|
nic->packetlen = rxfds[rxfd].count & 0x3fff;
|
|
memcpy(nic->packet, rxfds[rxfd].packet, nic->packetlen);
|
|
|
|
rxfds[rxfd].status = 0;
|
|
rxfds[rxfd].command = 0xc000;
|
|
rxfds[rxfd].rx_buf_addr = 0xFFFFFFFF;
|
|
rxfds[rxfd].count = 0;
|
|
rxfds[rxfd].size = 1528;
|
|
rxfds[(rxfd-1) % RXFD_COUNT].command = 0x0000;
|
|
rxfd = (rxfd+1) % RXFD_COUNT;
|
|
|
|
#ifdef DEBUG
|
|
hd (nic->packet, 0x30);
|
|
#endif
|
|
|
|
/* Acknowledge all conceivable interrupts */
|
|
outw(0xff00, ioaddr + SCBStatus);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* The chip may have suspended reception for various reasons.
|
|
* Check for that, and re-prime it should this be the case.
|
|
*/
|
|
switch ((inw(ioaddr + SCBStatus) >> 2) & 0xf) {
|
|
case 0: /* Idle */
|
|
break;
|
|
case 1: /* Suspended */
|
|
case 2: /* No resources (RxFDs) */
|
|
case 9: /* Suspended with no more RBDs */
|
|
case 10: /* No resources due to no RBDs */
|
|
case 12: /* Ready with no RBDs */
|
|
speedo_rx_soft_reset();
|
|
break;
|
|
default:
|
|
/* reserved values */
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* function: eepro100_disable
|
|
* resets the card. This is used to allow Etherboot or Linux
|
|
* to probe the card again from a "virginal" state....
|
|
* Arguments: none
|
|
*
|
|
* returns: void.
|
|
*/
|
|
static void eepro100_disable ( struct nic *nic __unused ) {
|
|
/* from eepro100_reset */
|
|
outl(0, ioaddr + SCBPort);
|
|
/* from eepro100_disable */
|
|
/* See if this PartialReset solves the problem with interfering with
|
|
kernel operation after Etherboot hands over. - Ken 20001102 */
|
|
outl(2, ioaddr + SCBPort);
|
|
|
|
/* The following is from the Intel e100 driver.
|
|
* This hopefully solves the problem with hanging hard DOS images. */
|
|
|
|
/* wait for the reset to take effect */
|
|
udelay(20);
|
|
|
|
/* Mask off our interrupt line -- it is unmasked after reset */
|
|
{
|
|
u16 intr_status;
|
|
/* Disable interrupts on our PCI board by setting the mask bit */
|
|
outw(INT_MASK, ioaddr + SCBCmd);
|
|
intr_status = inw(ioaddr + SCBStatus);
|
|
/* ack and clear intrs */
|
|
outw(intr_status, ioaddr + SCBStatus);
|
|
inw(ioaddr + SCBStatus);
|
|
}
|
|
}
|
|
|
|
/* exported function: eepro100_probe / eth_probe
|
|
* initializes a card
|
|
*
|
|
* side effects:
|
|
* leaves the ioaddress of the 82557 chip in the variable ioaddr.
|
|
* leaves the 82557 initialized, and ready to recieve packets.
|
|
*/
|
|
|
|
static int eepro100_probe ( struct nic *nic, struct pci_device *p ) {
|
|
|
|
unsigned short sum = 0;
|
|
int i;
|
|
int read_cmd, ee_size;
|
|
int options;
|
|
int rx_mode;
|
|
|
|
/* we cache only the first few words of the EEPROM data
|
|
be careful not to access beyond this array */
|
|
unsigned short eeprom[16];
|
|
|
|
if (p->ioaddr == 0)
|
|
return 0;
|
|
pci_fill_nic ( nic, p );
|
|
adjust_pci_device(p);
|
|
ioaddr = nic->ioaddr;
|
|
|
|
if ((do_eeprom_cmd(EE_READ_CMD << 24, 27) & 0xffe0000)
|
|
== 0xffe0000) {
|
|
ee_size = 0x100;
|
|
read_cmd = EE_READ_CMD << 24;
|
|
} else {
|
|
ee_size = 0x40;
|
|
read_cmd = EE_READ_CMD << 22;
|
|
}
|
|
|
|
for (i = 0, sum = 0; i < ee_size; i++) {
|
|
unsigned short value = do_eeprom_cmd(read_cmd | (i << 16), 27);
|
|
if (i < (int)(sizeof(eeprom)/sizeof(eeprom[0])))
|
|
eeprom[i] = value;
|
|
sum += value;
|
|
}
|
|
|
|
for (i=0;i<ETH_ALEN;i++) {
|
|
nic->node_addr[i] = (eeprom[i/2] >> (8*(i&1))) & 0xff;
|
|
}
|
|
|
|
DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
|
|
|
|
if (sum != 0xBABA)
|
|
printf("eepro100: Invalid EEPROM checksum %#hX, "
|
|
"check settings before activating this device!\n", sum);
|
|
outl(0, ioaddr + SCBPort);
|
|
udelay (10000);
|
|
whereami ("Got eeprom.");
|
|
|
|
/* Base = 0, disable all interrupts */
|
|
outl(0, ioaddr + SCBPointer);
|
|
outw(INT_MASK | RX_ADDR_LOAD, ioaddr + SCBCmd);
|
|
wait_for_cmd_done(ioaddr + SCBCmd);
|
|
whereami ("set rx base addr.");
|
|
|
|
outl(virt_to_bus(&lstats), ioaddr + SCBPointer);
|
|
outb(CU_STATSADDR, ioaddr + SCBCmd);
|
|
wait_for_cmd_done(ioaddr + SCBCmd);
|
|
whereami ("set stats addr.");
|
|
|
|
/* INIT RX stuff. */
|
|
for (i = 0; i < RXFD_COUNT; i++) {
|
|
rxfds[i].status = 0x0000;
|
|
rxfds[i].command = 0x0000;
|
|
rxfds[i].rx_buf_addr = 0xFFFFFFFF;
|
|
rxfds[i].count = 0;
|
|
rxfds[i].size = 1528;
|
|
rxfds[i].link = virt_to_bus(&rxfds[i+1]);
|
|
}
|
|
|
|
rxfds[RXFD_COUNT-1].status = 0x0000;
|
|
rxfds[RXFD_COUNT-1].command = 0xC000;
|
|
rxfds[RXFD_COUNT-1].link = virt_to_bus(&rxfds[0]);
|
|
|
|
outl(virt_to_bus(&rxfds[0]), ioaddr + SCBPointer);
|
|
outb(RX_START, ioaddr + SCBCmd);
|
|
wait_for_cmd_done(ioaddr + SCBCmd);
|
|
|
|
whereami ("started RX process.");
|
|
|
|
/* INIT TX stuff. */
|
|
|
|
/* Base = 0 */
|
|
outl(0, ioaddr + SCBPointer);
|
|
outb(CU_CMD_BASE, ioaddr + SCBCmd);
|
|
wait_for_cmd_done(ioaddr + SCBCmd);
|
|
|
|
whereami ("set TX base addr.");
|
|
|
|
txfd.command = (CmdIASetup);
|
|
txfd.status = 0x0000;
|
|
txfd.link = virt_to_bus (&confcmd);
|
|
|
|
{
|
|
char *t = (char *)&txfd.tx_desc_addr;
|
|
|
|
for (i=0;i<ETH_ALEN;i++)
|
|
t[i] = nic->node_addr[i];
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
printf ("Setup_eaddr:\n");
|
|
hd (&txfd, 0x20);
|
|
#endif
|
|
/* options = 0x40; */ /* 10mbps half duplex... */
|
|
options = 0x00; /* Autosense */
|
|
|
|
#ifdef PROMISC
|
|
rx_mode = 3;
|
|
#elif ALLMULTI
|
|
rx_mode = 1;
|
|
#else
|
|
rx_mode = 0;
|
|
#endif
|
|
|
|
if ( ((eeprom[6]>>8) & 0x3f) == DP83840
|
|
|| ((eeprom[6]>>8) & 0x3f) == DP83840A) {
|
|
int mdi_reg23 = mdio_read(eeprom[6] & 0x1f, 23) | 0x0422;
|
|
if (congenb)
|
|
mdi_reg23 |= 0x0100;
|
|
printf(" DP83840 specific setup, setting register 23 to %hX.\n",
|
|
mdi_reg23);
|
|
mdio_write(eeprom[6] & 0x1f, 23, mdi_reg23);
|
|
}
|
|
whereami ("Done DP8340 special setup.");
|
|
if (options != 0) {
|
|
mdio_write(eeprom[6] & 0x1f, 0,
|
|
((options & 0x20) ? 0x2000 : 0) | /* 100mbps? */
|
|
((options & 0x10) ? 0x0100 : 0)); /* Full duplex? */
|
|
whereami ("set mdio_register.");
|
|
}
|
|
|
|
confcmd.command = CmdSuspend | CmdConfigure;
|
|
confcmd.status = 0x0000;
|
|
confcmd.link = virt_to_bus (&txfd);
|
|
confcmd.data[1] = (txfifo << 4) | rxfifo;
|
|
confcmd.data[4] = rxdmacount;
|
|
confcmd.data[5] = txdmacount + 0x80;
|
|
confcmd.data[15] = (rx_mode & 2) ? 0x49: 0x48;
|
|
confcmd.data[19] = (options & 0x10) ? 0xC0 : 0x80;
|
|
confcmd.data[21] = (rx_mode & 1) ? 0x0D: 0x05;
|
|
|
|
outl(virt_to_bus(&txfd), ioaddr + SCBPointer);
|
|
outb(CU_START, ioaddr + SCBCmd);
|
|
wait_for_cmd_done(ioaddr + SCBCmd);
|
|
|
|
whereami ("started TX thingy (config, iasetup).");
|
|
|
|
load_timer2(10*TICKS_PER_MS);
|
|
while (!txfd.status && timer2_running())
|
|
/* Wait */;
|
|
|
|
/* Read the status register once to disgard stale data */
|
|
mdio_read(eeprom[6] & 0x1f, 1);
|
|
/* Check to see if the network cable is plugged in.
|
|
* This allows for faster failure if there is nothing
|
|
* we can do.
|
|
*/
|
|
if (!(mdio_read(eeprom[6] & 0x1f, 1) & (1 << 2))) {
|
|
printf("Valid link not established\n");
|
|
eepro100_disable(nic);
|
|
return 0;
|
|
}
|
|
nic->nic_op = &eepro100_operations;
|
|
return 1;
|
|
}
|
|
|
|
/*********************************************************************/
|
|
|
|
#ifdef DEBUG
|
|
|
|
/* Hexdump a number of bytes from memory... */
|
|
void hd (void *where, int n)
|
|
{
|
|
int i;
|
|
|
|
while (n > 0) {
|
|
printf ("%X ", where);
|
|
for (i=0;i < ( (n>16)?16:n);i++)
|
|
printf (" %hhX", ((char *)where)[i]);
|
|
printf ("\n");
|
|
n -= 16;
|
|
where += 16;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static struct nic_operations eepro100_operations = {
|
|
.connect = dummy_connect,
|
|
.poll = eepro100_poll,
|
|
.transmit = eepro100_transmit,
|
|
.irq = eepro100_irq,
|
|
|
|
};
|
|
|
|
static struct pci_device_id eepro100_nics[] = {
|
|
PCI_ROM(0x8086, 0x1029, "id1029", "Intel EtherExpressPro100 ID1029"),
|
|
PCI_ROM(0x8086, 0x1030, "id1030", "Intel EtherExpressPro100 ID1030"),
|
|
PCI_ROM(0x8086, 0x1031, "82801cam", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
|
|
PCI_ROM(0x8086, 0x1032, "eepro100-1032", "Intel PRO/100 VE Network Connection"),
|
|
PCI_ROM(0x8086, 0x1033, "eepro100-1033", "Intel PRO/100 VM Network Connection"),
|
|
PCI_ROM(0x8086, 0x1034, "eepro100-1034", "Intel PRO/100 VM Network Connection"),
|
|
PCI_ROM(0x8086, 0x1035, "eepro100-1035", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
|
|
PCI_ROM(0x8086, 0x1036, "eepro100-1036", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
|
|
PCI_ROM(0x8086, 0x1037, "eepro100-1037", "Intel 82801CAM (ICH3) Chipset Ethernet Controller"),
|
|
PCI_ROM(0x8086, 0x1038, "id1038", "Intel PRO/100 VM Network Connection"),
|
|
PCI_ROM(0x8086, 0x1039, "82562et", "Intel PRO100 VE 82562ET"),
|
|
PCI_ROM(0x8086, 0x103a, "id103a", "Intel Corporation 82559 InBusiness 10/100"),
|
|
PCI_ROM(0x8086, 0x103b, "82562etb", "Intel PRO100 VE 82562ETB"),
|
|
PCI_ROM(0x8086, 0x103c, "eepro100-103c", "Intel PRO/100 VM Network Connection"),
|
|
PCI_ROM(0x8086, 0x103d, "eepro100-103d", "Intel PRO/100 VE Network Connection"),
|
|
PCI_ROM(0x8086, 0x103e, "eepro100-103e", "Intel PRO/100 VM Network Connection"),
|
|
PCI_ROM(0x8086, 0x1051, "prove", "Intel PRO/100 VE Network Connection"),
|
|
PCI_ROM(0x8086, 0x1059, "82551qm", "Intel PRO/100 M Mobile Connection"),
|
|
PCI_ROM(0x8086, 0x1209, "82559er", "Intel EtherExpressPro100 82559ER"),
|
|
PCI_ROM(0x8086, 0x1227, "82865", "Intel 82865 EtherExpress PRO/100A"),
|
|
PCI_ROM(0x8086, 0x1228, "82556", "Intel 82556 EtherExpress PRO/100 Smart"),
|
|
PCI_ROM(0x8086, 0x1229, "eepro100", "Intel EtherExpressPro100"),
|
|
PCI_ROM(0x8086, 0x2449, "82562em", "Intel EtherExpressPro100 82562EM"),
|
|
PCI_ROM(0x8086, 0x2459, "82562-1", "Intel 82562 based Fast Ethernet Connection"),
|
|
PCI_ROM(0x8086, 0x245d, "82562-2", "Intel 82562 based Fast Ethernet Connection"),
|
|
PCI_ROM(0x8086, 0x1050, "82562ez", "Intel 82562EZ Network Connection"),
|
|
PCI_ROM(0x8086, 0x1051, "eepro100-1051", "Intel 82801EB/ER (ICH5/ICH5R) Chipset Ethernet Controller"),
|
|
PCI_ROM(0x8086, 0x5200, "eepro100-5200", "Intel EtherExpress PRO/100 Intelligent Server"),
|
|
PCI_ROM(0x8086, 0x5201, "eepro100-5201", "Intel EtherExpress PRO/100 Intelligent Server"),
|
|
};
|
|
|
|
/* Cards with device ids 0x1030 to 0x103F, 0x2449, 0x2459 or 0x245D might need
|
|
* a workaround for hardware bug on 10 mbit half duplex (see linux driver eepro100.c)
|
|
* 2003/03/17 gbaum */
|
|
|
|
|
|
PCI_DRIVER ( eepro100_driver, eepro100_nics, PCI_NO_CLASS );
|
|
|
|
DRIVER ( "EEPRO100", nic_driver, pci_driver, eepro100_driver,
|
|
eepro100_probe, eepro100_disable );
|