180 lines
7.3 KiB
C
180 lines
7.3 KiB
C
/*
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* Copyright (C) 2004 Tobias Lorenz
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Architecture: ARM9TDMI
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* Processor : P2001
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*/
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#ifndef ARCH_HARDWARE_H
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#define ARCH_HARDWARE_H
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#ifndef __ASSEMBLY__
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/* DMA descriptor */
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typedef struct {
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unsigned int stat; /* status: own, start, end, offset, status */
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unsigned int cntl; /* control: loop, int, type, channel, length */
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char *buf; /* buffer */
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void *next; /* nextdsc */
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} DMA_DSC;
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/* The address definitions are from asic_bf.h */
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typedef struct { // 0x00100000U
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volatile unsigned int reserved1[0x3];
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volatile unsigned int ArmDmaPri; // 0x0000000CU
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volatile unsigned int SDRAM_Ctrl; // 0x00000010U
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volatile unsigned int ExtMem_Ctrl; // 0x00000014U
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volatile unsigned int WaitState_Ext; // 0x00000018U
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volatile unsigned int WaitState_Asic; // 0x0000001CU
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volatile unsigned int TOP; // 0x00000020U
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volatile unsigned int reserved2[0x3];
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volatile unsigned int Adr1_EQ_30Bit; // 0x00000030U
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volatile unsigned int Adr2_EQ_30Bit; // 0x00000034U
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volatile unsigned int Adr3_EQ_30Bit; // 0x00000038U
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volatile unsigned int Dat3_EQ_32Bit; // 0x0000003CU
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volatile unsigned int Adr4_HE_20Bit; // 0x00000040U
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volatile unsigned int Adr4_LT_20Bit; // 0x00000044U
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volatile unsigned int Adr5_HE_20Bit; // 0x00000048U
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volatile unsigned int Adr5_LT_20Bit; // 0x0000004CU
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volatile unsigned int Adr_Control; // 0x00000050U
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volatile unsigned int ABORT_IA_32Bit; // 0x00000054U
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} *P2001_SYS_regs_ptr;
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#define P2001_SYS ((volatile P2001_SYS_regs_ptr) 0x00100000)
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typedef struct { // 0x00110000U
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volatile unsigned int Timer1; // 0x00000000U
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volatile unsigned int Timer2; // 0x00000004U
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volatile unsigned int TIMER_PRELOAD; // 0x00000008U
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volatile unsigned int Timer12_PreDiv; // 0x0000000CU
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volatile unsigned int TIMER_INT; // 0x00000010U
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volatile unsigned int Freerun_Timer; // 0x00000014U
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volatile unsigned int WatchDog_Timer; // 0x00000018U
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volatile unsigned int PWM_CNT; // 0x00000020U
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volatile unsigned int PWM_CNT2; // 0x00000024U
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volatile unsigned int PLL_12000_config; // 0x00000030U
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volatile unsigned int PLL_12288_config; // 0x00000034U
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volatile unsigned int DIV_12288_config; // 0x00000038U
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volatile unsigned int MOD_CNT_768; // 0x0000003CU
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volatile unsigned int FSC_IRQ_STATUS; // 0x00000040U
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volatile unsigned int FSC_CONFIG; // 0x00000044U
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volatile unsigned int FSC_CONSTRUCT; // 0x00000048U
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volatile unsigned int FSC_base_clk_reg; // 0x0000004CU
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volatile unsigned int SYSCLK_SHAPE; // 0x00000050U
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volatile unsigned int SDRAMCLK_SHAPE; // 0x00000054U
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volatile unsigned int RING_OSZI; // 0x00000058U
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} *P2001_TIMER_regs_ptr;
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#define P2001_TIMER ((volatile P2001_TIMER_regs_ptr) 0x00110000)
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typedef struct { // 0x00120000U
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volatile unsigned int reserved1[0x5];
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volatile unsigned int GPIO_Config; // 0x00000014U
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volatile unsigned int GPIO_INT; // 0x00000018U
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volatile unsigned int GPIO_Out; // 0x0000001CU
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volatile unsigned int GPIO_IN; // 0x00000020U
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volatile unsigned int GPIO_En; // 0x00000024U
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volatile unsigned int PIN_MUX; // 0x00000028U
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volatile unsigned int NRES_OUT; // 0x0000002CU
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volatile unsigned int GPIO2_Out; // 0x00000030U
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volatile unsigned int GPIO2_IN; // 0x00000034U
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volatile unsigned int GPIO2_En; // 0x00000038U
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volatile unsigned int GPIO_INT_SEL; // 0x0000003CU
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volatile unsigned int GPI3_IN; // 0x00000040U
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volatile unsigned int GPO4_OUT; // 0x00000044U
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} *P2001_GPIO_regs_ptr;
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#define P2001_GPIO ((volatile P2001_GPIO_regs_ptr) 0x00120000)
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typedef struct { // 0x00130000U
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volatile unsigned int Main_NFIQ_Int_Ctrl; // 0x00000000U
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volatile unsigned int Main_NIRQ_Int_Ctrl; // 0x00000004U
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volatile unsigned int Status_NFIQ; // 0x00000008U
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volatile unsigned int Status_NIRQ; // 0x0000000CU
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} *P2001_INT_CTRL_regs_ptr;
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#define P2001_INT_CTRL ((volatile P2001_INT_CTRL_regs_ptr) 0x00130000)
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typedef union { // 0x00140000U
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struct { // write
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volatile unsigned int TX1; // 0x00000000U
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volatile unsigned int TX2; // 0x00000004U
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volatile unsigned int TX3; // 0x00000008U
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volatile unsigned int TX4; // 0x0000000CU
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volatile unsigned int Baudrate; // 0x00000010U
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volatile unsigned int reserved1[0x3];
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volatile unsigned int Config; // 0x00000020U
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volatile unsigned int Clear; // 0x00000024U
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volatile unsigned int Echo_EN; // 0x00000028U
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volatile unsigned int IRQ_Status; // 0x0000002CU
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} w; // write
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struct { // read
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volatile unsigned int RX1; // 0x00000000U
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volatile unsigned int RX2; // 0x00000004U
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volatile unsigned int RX3; // 0x00000008U
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volatile unsigned int RX4; // 0x0000000CU
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volatile unsigned int reserved1[0x4];
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volatile unsigned int PRE_STATUS; // 0x00000020U
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volatile unsigned int STATUS; // 0x00000024U
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volatile unsigned int reserved2[0x1];
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volatile unsigned int IRQ_Status; // 0x0000002CU
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} r; // read
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} *P2001_UART_regs_ptr;
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#define P2001_UART ((volatile P2001_UART_regs_ptr) 0x00140000)
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typedef struct { // 0x0018_000U _=0,1,2,3
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volatile DMA_DSC * RMAC_DMA_DESC; // 0x00000000U
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volatile unsigned int RMAC_DMA_CNTL; // 0x00000004U
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volatile unsigned int RMAC_DMA_STAT; // 0x00000008U
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volatile unsigned int RMAC_DMA_EN; // 0x0000000CU
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volatile unsigned int RMAC_CNTL; // 0x00000010U
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volatile unsigned int RMAC_TLEN; // 0x00000014U
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volatile unsigned int RMAC_PHYU; // 0x00000018U
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volatile unsigned int RMAC_PHYL; // 0x0000001CU
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volatile unsigned int RMAC_PFM0; // 0x00000020U
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volatile unsigned int RMAC_PFM1; // 0x00000024U
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volatile unsigned int RMAC_PFM2; // 0x00000028U
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volatile unsigned int RMAC_PFM3; // 0x0000002CU
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volatile unsigned int RMAC_PFM4; // 0x00000030U
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volatile unsigned int RMAC_PFM5; // 0x00000034U
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volatile unsigned int RMAC_PFM6; // 0x00000038U
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volatile unsigned int RMAC_PFM7; // 0x0000003CU
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volatile unsigned int RMAC_MIB0; // 0x00000040U
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volatile unsigned int RMAC_MIB1; // 0x00000044U
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volatile unsigned int RMAC_MIB2; // 0x00000048U
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volatile unsigned int RMAC_MIB3; // 0x0000004CU
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volatile unsigned int RMAC_MIB4; // 0x00000050U
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volatile unsigned int RMAC_MIB5; // 0x00000054U
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volatile unsigned int reserved1[0x1e8];
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volatile unsigned int RMAC_DMA_DATA; // 0x000007F8U
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volatile unsigned int RMAC_DMA_ADR; // 0x000007FCU
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volatile DMA_DSC * TMAC_DMA_DESC; // 0x00000800U
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volatile unsigned int TMAC_DMA_CNTL; // 0x00000804U
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volatile unsigned int TMAC_DMA_STAT; // 0x00000808U
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volatile unsigned int TMAC_DMA_EN; // 0x0000080CU
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volatile unsigned int TMAC_CNTL; // 0x00000810U
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volatile unsigned int TMAC_MIB6; // 0x00000814U
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volatile unsigned int TMAC_MIB7; // 0x00000818U
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volatile unsigned int reserved2[0x1];
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volatile unsigned int MU_CNTL; // 0x00000820U
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volatile unsigned int MU_DATA; // 0x00000824U
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volatile unsigned int MU_DIV; // 0x00000828U
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volatile unsigned int CONF_RMII; // 0x0000082CU
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volatile unsigned int reserved3[0x1f2];
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volatile unsigned int TMAC_DMA_DATA; // 0x00000FF8U
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volatile unsigned int TMAC_DMA_ADR; // 0x00000FFCU
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} *P2001_ETH_regs_ptr;
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#define P2001_EU0 ((volatile P2001_ETH_regs_ptr) 0x00180000)
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#define P2001_EU1 ((volatile P2001_ETH_regs_ptr) 0x00181000)
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#define P2001_EU2 ((volatile P2001_ETH_regs_ptr) 0x00182000)
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#define P2001_EU3 ((volatile P2001_ETH_regs_ptr) 0x00183000)
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#define P2001_MU P2001_EU0
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#endif
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#endif /* ARCH_HARDWARE_H */
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