185 lines
3.8 KiB
ArmAsm
185 lines
3.8 KiB
ArmAsm
/*
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* Copyright (C) 2004 Tobias Lorenz
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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.global _start
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/* Mode definitions */
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#define Mode_USR 0x10
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#define Mode_FIQ 0x11
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#define Mode_IRQ 0x12
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#define Mode_SVC 0x13
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#define Mode_ABT 0x17
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#define Mode_UNDEF 0x1B
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#define Mode_SYS 0x1F // only available on ARM Arch. v4
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#define I_Bit 0x80
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#define F_Bit 0x40
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/* LPEC register definitions */
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#define Adr_SYS_BASE 0x00100000
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#define REL_Adr_SDRAM_Ctrl 0x10
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#define REL_Adr_ExtMem_Ctrl 0x14
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#define REL_Adr_WaitState_Ext 0x18
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#define REL_Adr_WaitState_Asic 0x1c
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#define Adr_TIMER_BASE 0x00110000
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#define REL_Adr_Timer12_PreDiv 0x0c
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#define REL_Adr_PLL_12000_config 0x30
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#define REL_Adr_PLL_12288_config 0x34
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#define REL_Adr_DIV_12288_config 0x38
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#define REL_Adr_FSC_CONFIG 0x44
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#define Adr_GPIO_BASE 0x00120000
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#define REL_Adr_NRES_OUT 0x2c
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/* Define entry point */
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.arm // Next instruction will be ARM
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_start:
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/*
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* Initialize memory system
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*/
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/*
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* Initialize stack pointer registers
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*/
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/* Enter SVC mode and set up the SVC stack pointer */
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mov r0, #(Mode_SVC|I_Bit|F_Bit)
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msr cpsr_c, r0
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ldr sp, SP_SVC
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/*
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* Initialize critical IO devices
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*/
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/* watchdog off */
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mov r0, #Adr_TIMER_BASE
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ldr r1, Timer12_PreDiv
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str r1, [r0, #REL_Adr_Timer12_PreDiv]
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/* NRES=1 */
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mov r0, #Adr_GPIO_BASE
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ldr r1, NRES_OUT
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str r1, [r0, #REL_Adr_NRES_OUT]
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/* ExtMem */
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mov r0, #Adr_SYS_BASE
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ldr r1, ExtMem_Ctrl
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str r1, [r0, #REL_Adr_ExtMem_Ctrl]
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/* SDRAM */
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mov r0, #Adr_SYS_BASE
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ldr r1, SDRAM_Ctrl
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str r1, [r0, #REL_Adr_SDRAM_Ctrl]
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/*
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_wait_sdram_ctrl:
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ldr r1, [r0]
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tst r1, #0x20000
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beq _wait_sdram_ctrl
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*/
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/* WaitState_Ext */
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ldr r1, WaitState_Ext
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str r1, [r0, #REL_Adr_WaitState_Ext]
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/* WaitState_Asic */
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ldr r1, WaitState_Asic
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str r1, [r0, #REL_Adr_WaitState_Asic]
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/* PLL_12288 */
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mov r0, #Adr_TIMER_BASE
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ldr r1, PLL_12288_config
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str r1, [r0, #REL_Adr_PLL_12288_config]
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/* DIV_12288 */
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ldr r1, DIV_12288_config
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str r1, [r0, #REL_Adr_DIV_12288_config]
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/* PLL_12200 */
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ldr r1, PLL_12000_config
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str r1, [r0, #REL_Adr_PLL_12000_config]
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/* FSC_CONFIG */
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ldr r1, [r0, #REL_Adr_FSC_CONFIG]
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bic r1, r1, #0x07
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ldr r2, FSC_CONFIG
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orr r1, r1, r2
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str r1, [r0, #REL_Adr_FSC_CONFIG]
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/*
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* Initialize interrupt system variables here
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*/
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/*
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* Initialize memory required by main C code
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*/
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/* jump to main program */
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mov r0, #0
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b main
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Timer12_PreDiv:
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.word 0x40bb0000 /* watchdog off */
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NRES_OUT:
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.word 0x00000003 /* NRES_OUT_DRV=1, NRES_OUT_DAT=1 */
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#if SYSCLK == 73728000
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ExtMem_Ctrl:
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.word 0x000000e8 /* fuer FPGA 32 Bit konfiguriert */
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SDRAM_Ctrl:
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// .word 0x28fc0037 /* default */
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.word 0xaef40027 /* p2001_bit_compact */
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WaitState_Ext:
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.word 0xa0001245 /* fuer 73 MHz */
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// .word 0x0000fff3 /* rom bootloader */
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WaitState_Asic:
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.word 0x00ff8a5f /* fuer 85 MHz */
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// .word 0x00000203 /* rom bootloader */
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PLL_12288_config:
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.word 0x00000004 /* fuer 73 MHz */
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DIV_12288_config:
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.word 0x00010601 /* fuer 73 MHz */
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PLL_12000_config:
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.word 0x10004e75 /* fuer 85 MHz */
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FSC_CONFIG:
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.word 0xc0000005 /* fuer 73 MHz */
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#else
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#error "Please define proper timings and wait states for that sysclk."
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#endif
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SP_SVC:
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.word 0x40fffffc
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#ifndef NORELOCATE
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/**************************************************************************
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RELOCATE_TO - relocate etherboot to the specified address
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**************************************************************************/
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.global relocate_to
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relocate_to:
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ldr r1, =_start
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ldr r2, =_end
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/* while (r1 < r2) { *(r0++) = *(r1++) } */
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_relocate_loop:
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cmp r1, r2
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ldrcc r3, [r1], #4
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strcc r3, [r0], #4
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bcc _relocate_loop
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mov pc, lr
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#endif
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.global __gccmain
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__gccmain:
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mov pc, lr /* return from subroutine */
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