ead70bf920
ICH8 devices have an errata which requires us to reconfigure the
packet buffer size (PBS) register, and correspondingly adjust the
packet buffer allocation (PBA) register. The "Intel I/O Controller
Hub ICH8/9/10 and 82566/82567/82562V Software Developer's Manual"
notes for the PBS register that:
10.4.20 Packet Buffer Size - PBS (01008h; R/W)
Note: The default setting of this register is 20 KB and is
incorrect. This register must be programmed to 16 KB.
Initial value: 0014h
0018h (ICH9/ICH10)
It is unclear from this comment precisely which devices require the
workaround to be applied. We currently attempt to err on the side of
caution: if we detect an initial value of either 0x14 or 0x18 then the
workaround will be applied. If the workaround is applied
unnecessarily, then the effect should be just that we use less than
the full amount of the available packet buffer memory.
Unfortunately this approach does not play nicely with other device
drivers. For example, the Linux e1000e driver will rewrite PBA while
assuming that PBS still contains the default value, which can result
in inconsistent values between the two registers, and a corresponding
inability to transmit or receive packets. Even more unfortunately,
the contents of PBS and PBA are not reset by anything less than a
power cycle, meaning that this error condition will survive a hardware
reset.
The Linux driver (written and maintained by Intel) applies the PBS/PBA
errata workaround only for devices in the ICH8 family, identified via
the PCI device ID. Adopt a similar approach, using the PCI_ROM()
driver data field to indicate when the workaround is required.
Reported-by: Donald Bindner <dbindner@truman.edu>
Debugged-by: Donald Bindner <dbindner@truman.edu>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
268 lines
7.3 KiB
C
268 lines
7.3 KiB
C
#ifndef _INTEL_H
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#define _INTEL_H
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/** @file
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*
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* Intel 10/100/1000 network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/nvs.h>
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/** Intel BAR size */
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#define INTEL_BAR_SIZE ( 128 * 1024 )
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/** A packet descriptor */
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struct intel_descriptor {
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/** Buffer address */
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uint64_t address;
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/** Length */
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uint16_t length;
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/** Reserved */
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uint8_t reserved_a;
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/** Command */
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uint8_t command;
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/** Status */
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uint8_t status;
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/** Errors */
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uint8_t errors;
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/** Reserved */
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uint16_t reserved_b;
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} __attribute__ (( packed ));
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/** Packet descriptor command bits */
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enum intel_descriptor_command {
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/** Report status */
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INTEL_DESC_CMD_RS = 0x08,
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/** Insert frame checksum (CRC) */
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INTEL_DESC_CMD_IFCS = 0x02,
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/** End of packet */
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INTEL_DESC_CMD_EOP = 0x01,
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};
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/** Packet descriptor status bits */
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enum intel_descriptor_status {
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/** Descriptor done */
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INTEL_DESC_STATUS_DD = 0x01,
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};
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/** Device Control Register */
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#define INTEL_CTRL 0x00000UL
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#define INTEL_CTRL_LRST 0x00000008UL /**< Link reset */
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#define INTEL_CTRL_ASDE 0x00000020UL /**< Auto-speed detection */
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#define INTEL_CTRL_SLU 0x00000040UL /**< Set link up */
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#define INTEL_CTRL_FRCSPD 0x00000800UL /**< Force speed */
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#define INTEL_CTRL_FRCDPLX 0x00001000UL /**< Force duplex */
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#define INTEL_CTRL_RST 0x04000000UL /**< Device reset */
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#define INTEL_CTRL_PHY_RST 0x80000000UL /**< PHY reset */
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/** Time to delay for device reset, in milliseconds */
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#define INTEL_RESET_DELAY_MS 20
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/** Device Status Register */
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#define INTEL_STATUS 0x00008UL
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#define INTEL_STATUS_LU 0x00000002UL /**< Link up */
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/** EEPROM Read Register */
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#define INTEL_EERD 0x00014UL
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#define INTEL_EERD_START 0x00000001UL /**< Start read */
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#define INTEL_EERD_DONE_SMALL 0x00000010UL /**< Read done (small EERD) */
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#define INTEL_EERD_DONE_LARGE 0x00000002UL /**< Read done (large EERD) */
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#define INTEL_EERD_ADDR_SHIFT_SMALL 8 /**< Address shift (small) */
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#define INTEL_EERD_ADDR_SHIFT_LARGE 2 /**< Address shift (large) */
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#define INTEL_EERD_DATA(value) ( (value) >> 16 ) /**< Read data */
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/** Maximum time to wait for EEPROM read, in milliseconds */
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#define INTEL_EEPROM_MAX_WAIT_MS 100
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/** EEPROM word length */
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#define INTEL_EEPROM_WORD_LEN_LOG2 1
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/** Minimum EEPROM size, in words */
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#define INTEL_EEPROM_MIN_SIZE_WORDS 64
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/** Offset of MAC address within EEPROM */
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#define INTEL_EEPROM_MAC 0x00
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/** Interrupt Cause Read Register */
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#define INTEL_ICR 0x000c0UL
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#define INTEL_IRQ_TXDW 0x00000001UL /**< Transmit descriptor done */
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#define INTEL_IRQ_LSC 0x00000004UL /**< Link status change */
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#define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
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#define INTEL_IRQ_RXO 0x00000400UL /**< Receive overrun */
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/** Interrupt Mask Set/Read Register */
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#define INTEL_IMS 0x000d0UL
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/** Interrupt Mask Clear Register */
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#define INTEL_IMC 0x000d8UL
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/** Receive Control Register */
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#define INTEL_RCTL 0x00100UL
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#define INTEL_RCTL_EN 0x00000002UL /**< Receive enable */
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#define INTEL_RCTL_UPE 0x00000008UL /**< Unicast promiscuous mode */
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#define INTEL_RCTL_MPE 0x00000010UL /**< Multicast promiscuous */
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#define INTEL_RCTL_BAM 0x00008000UL /**< Broadcast accept mode */
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#define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
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( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
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#define INTEL_RCTL_BSIZE_2048 INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
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#define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
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#define INTEL_RCTL_SECRC 0x04000000UL /**< Strip CRC */
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/** Transmit Control Register */
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#define INTEL_TCTL 0x00400UL
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#define INTEL_TCTL_EN 0x00000002UL /**< Transmit enable */
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#define INTEL_TCTL_PSP 0x00000008UL /**< Pad short packets */
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#define INTEL_TCTL_CT(x) ( (x) << 4 ) /**< Collision threshold */
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#define INTEL_TCTL_CT_DEFAULT INTEL_TCTL_CT ( 0x0f )
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#define INTEL_TCTL_CT_MASK INTEL_TCTL_CT ( 0xff )
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#define INTEL_TCTL_COLD(x) ( (x) << 12 ) /**< Collision distance */
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#define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
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#define INTEL_TCTL_COLD_MASK INTEL_TCTL_COLD ( 0x3ff )
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/** Packet Buffer Allocation */
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#define INTEL_PBA 0x01000UL
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/** Packet Buffer Size */
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#define INTEL_PBS 0x01008UL
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/** Receive Descriptor register block */
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#define INTEL_RD 0x02800UL
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/** Number of receive descriptors
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*
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* Minimum value is 8, since the descriptor ring length must be a
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* multiple of 128.
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*/
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#define INTEL_NUM_RX_DESC 16
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/** Receive descriptor ring fill level */
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#define INTEL_RX_FILL 8
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/** Receive buffer length */
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#define INTEL_RX_MAX_LEN 2048
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/** Transmit Descriptor register block */
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#define INTEL_TD 0x03800UL
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/** Number of transmit descriptors
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*
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* Descriptor ring length must be a multiple of 16. ICH8/9/10
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* requires a minimum of 16 TX descriptors.
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*/
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#define INTEL_NUM_TX_DESC 16
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/** Transmit descriptor ring maximum fill level */
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#define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
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/** Receive/Transmit Descriptor Base Address Low (offset) */
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#define INTEL_xDBAL 0x00
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/** Receive/Transmit Descriptor Base Address High (offset) */
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#define INTEL_xDBAH 0x04
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/** Receive/Transmit Descriptor Length (offset) */
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#define INTEL_xDLEN 0x08
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/** Receive/Transmit Descriptor Head (offset) */
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#define INTEL_xDH 0x10
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/** Receive/Transmit Descriptor Tail (offset) */
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#define INTEL_xDT 0x18
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/** Receive/Transmit Descriptor Control (offset) */
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#define INTEL_xDCTL 0x28
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#define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */
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/** Receive Address Low */
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#define INTEL_RAL0 0x05400UL
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/** Receive Address High */
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#define INTEL_RAH0 0x05404UL
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#define INTEL_RAH0_AV 0x80000000UL /**< Address valid */
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/** Receive address */
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union intel_receive_address {
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struct {
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uint32_t low;
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uint32_t high;
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} __attribute__ (( packed )) reg;
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uint8_t raw[ETH_ALEN];
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};
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/** An Intel descriptor ring */
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struct intel_ring {
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/** Descriptors */
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struct intel_descriptor *desc;
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/** Producer index */
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unsigned int prod;
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/** Consumer index */
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unsigned int cons;
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/** Register block */
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unsigned int reg;
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/** Length (in bytes) */
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size_t len;
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};
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/**
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* Initialise descriptor ring
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*
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* @v ring Descriptor ring
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* @v count Number of descriptors
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* @v reg Descriptor register block
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*/
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static inline __attribute__ (( always_inline)) void
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intel_init_ring ( struct intel_ring *ring, unsigned int count,
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unsigned int reg ) {
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ring->len = ( count * sizeof ( ring->desc[0] ) );
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ring->reg = reg;
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}
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/** An Intel network card */
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struct intel_nic {
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/** Registers */
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void *regs;
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/** Port number (for multi-port devices) */
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unsigned int port;
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/** Flags */
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unsigned int flags;
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/** EEPROM */
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struct nvs_device eeprom;
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/** EEPROM done flag */
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uint32_t eerd_done;
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/** EEPROM address shift */
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unsigned int eerd_addr_shift;
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/** Transmit descriptor ring */
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struct intel_ring tx;
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/** Receive descriptor ring */
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struct intel_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[INTEL_NUM_RX_DESC];
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};
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/** Driver flags */
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enum intel_flags {
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/** PBS/PBA errata workaround required */
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INTEL_PBS_ERRATA = 0x0001,
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};
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extern int intel_create_ring ( struct intel_nic *intel,
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struct intel_ring *ring );
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extern void intel_destroy_ring ( struct intel_nic *intel,
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struct intel_ring *ring );
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extern void intel_refill_rx ( struct intel_nic *intel );
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extern void intel_empty_rx ( struct intel_nic *intel );
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extern int intel_transmit ( struct net_device *netdev,
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struct io_buffer *iobuf );
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extern void intel_poll_tx ( struct net_device *netdev );
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extern void intel_poll_rx ( struct net_device *netdev );
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#endif /* _INTEL_H */
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