303 lines
10 KiB
C
303 lines
10 KiB
C
/*
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* Copyright (C) 2015 Mellanox Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include "../../mlx_lib/mlx_nvconfig/mlx_nvconfig.h"
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#include "../../include/public/mlx_memory.h"
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#include "../../include/public/mlx_bail.h"
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#define TlvMappingEntry( _tlv_type, _real_tlv_type, _class_code, _fw_reset_needed) { \
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.tlv_type = _tlv_type, \
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.real_tlv_type = _real_tlv_type, \
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.class_code = _class_code, \
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.fw_reset_needed = _fw_reset_needed, \
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}
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struct nvconfig_tlv_mapping nvconfig_tlv_mapping[] = {
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TlvMappingEntry(0x10, 0x10, NVRAM_TLV_CLASS_HOST, TRUE),
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TlvMappingEntry(0x12, 0x12, NVRAM_TLV_CLASS_PHYSICAL_PORT, TRUE),
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TlvMappingEntry(0x80, 0x80, NVRAM_TLV_CLASS_GLOBAL, TRUE),
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TlvMappingEntry(0x81, 0x81, NVRAM_TLV_CLASS_GLOBAL, TRUE),
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TlvMappingEntry(0x100, 0x100, NVRAM_TLV_CLASS_GLOBAL, TRUE),
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TlvMappingEntry(0x2001, 0x195, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2010, 0x210, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2011, 0x211, NVRAM_TLV_CLASS_GLOBAL, FALSE),
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TlvMappingEntry(0x2020, 0x2020, NVRAM_TLV_CLASS_PHYSICAL_PORT, FALSE),
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TlvMappingEntry(0x2021, 0x221, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2023, 0x223, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2006, 0x206, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2100, 0x230, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2101, 0x231, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2102, 0x232, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2103, 0x233, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2104, 0x234, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2105, 0x235, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2106, 0x236, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2107, 0x237, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2108, 0x238, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2109, 0x239, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x210A, 0x23A, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2022, 0x222, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2200, 0x240, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2201, 0x241, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2202, 0x242, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2203, 0x243, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2204, 0x244, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2205, 0x245, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2207, 0x247, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2002, 0x202, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x2004, 0x204, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x110, 0x110, NVRAM_TLV_CLASS_HOST, FALSE),
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TlvMappingEntry(0x192, 0x192, NVRAM_TLV_CLASS_GLOBAL, FALSE),
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TlvMappingEntry(0x101, 0x101, NVRAM_TLV_CLASS_GLOBAL, TRUE),
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TlvMappingEntry(0, 0, 0, 0),
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};
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static
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mlx_status
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nvconfig_set_fw_reset_level(
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IN mlx_utils *utils,
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IN mlx_uint16 tlv_type
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)
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{
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#define WARM_REBOOT_RESET ((mlx_uint64)0x1 << 38)
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mlx_status status = MLX_SUCCESS;
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mlx_uint32 reg_status;
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mlx_uint64 mfrl = WARM_REBOOT_RESET ;
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mlx_uint8 index = 0;
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mlx_boolean reset_needed = FALSE;
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for (index = 0 ; nvconfig_tlv_mapping[index].tlv_type != 0 ; index++) {
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if (nvconfig_tlv_mapping[index].tlv_type == tlv_type) {
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reset_needed = nvconfig_tlv_mapping[index].fw_reset_needed;
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}
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}
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if (reset_needed == FALSE) {
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goto no_fw_reset_needed;
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}
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status = mlx_reg_access(utils, REG_ID_MFRL, REG_ACCESS_WRITE, &mfrl, sizeof(mfrl),
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®_status);
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MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
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if (reg_status != 0) {
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MLX_DEBUG_ERROR(utils,"nvconfig_set_fw_reset_level failed with status = %d\n", reg_status);
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status = MLX_FAILED;
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goto reg_err;
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}
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reg_err:
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no_fw_reset_needed:
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return status;
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}
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static
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mlx_status
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nvconfig_get_tlv_type_and_class(
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IN mlx_uint16 tlv_type,
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OUT mlx_uint16 *real_tlv_type,
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OUT NVRAM_CLASS_CODE *class_code
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)
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{
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mlx_uint8 index = 0;
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for ( ; nvconfig_tlv_mapping[index].tlv_type != 0 ; index ++) {
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if ( nvconfig_tlv_mapping[index].tlv_type == tlv_type) {
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*real_tlv_type = nvconfig_tlv_mapping[index].real_tlv_type;
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*class_code = nvconfig_tlv_mapping[index].class_code;
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return MLX_SUCCESS;
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}
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}
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return MLX_NOT_FOUND;
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}
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static
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void
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nvconfig_fill_tlv_type(
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IN mlx_uint8 port,
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IN NVRAM_CLASS_CODE class_code,
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IN mlx_uint16 tlv_type,
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OUT union nvconfig_tlv_type *nvconfig_tlv_type
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)
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{
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switch (class_code) {
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case NVRAM_TLV_CLASS_GLOBAL:
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nvconfig_tlv_type->global.param_class = NVRAM_TLV_CLASS_GLOBAL;
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nvconfig_tlv_type->global.param_idx = tlv_type;
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break;
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case NVRAM_TLV_CLASS_HOST:
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nvconfig_tlv_type->per_host.param_class = NVRAM_TLV_CLASS_HOST;
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nvconfig_tlv_type->per_host.param_idx = tlv_type;
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break;
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case NVRAM_TLV_CLASS_PHYSICAL_PORT:
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nvconfig_tlv_type->per_port.param_class = NVRAM_TLV_CLASS_PHYSICAL_PORT;
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nvconfig_tlv_type->per_port.param_idx = tlv_type;
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nvconfig_tlv_type->per_port.port = port;
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break;
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}
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}
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mlx_status
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nvconfig_query_capability(
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IN mlx_utils *utils,
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IN mlx_uint8 port,
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IN mlx_uint16 tlv_type,
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OUT mlx_boolean *read_supported,
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OUT mlx_boolean *write_supported
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)
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{
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mlx_status status = MLX_SUCCESS;
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struct nvconfig_nvqc nvqc;
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mlx_uint32 reg_status;
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NVRAM_CLASS_CODE class_code;
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mlx_uint16 real_tlv_type;
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if (utils == NULL || read_supported == NULL || write_supported == NULL) {
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status = MLX_INVALID_PARAMETER;
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goto bad_param;
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}
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status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
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MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
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mlx_memory_set(utils, &nvqc, 0, sizeof(nvqc));
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nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nvqc.tlv_type);
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status = mlx_reg_access(utils, REG_ID_NVQC, REG_ACCESS_READ, &nvqc, sizeof(nvqc),
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®_status);
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MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
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if (reg_status != 0) {
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MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
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status = MLX_FAILED;
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goto reg_err;
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}
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*read_supported = nvqc.support_rd;
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*write_supported = nvqc.support_wr;
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reg_err:
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tlv_not_supported:
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bad_param:
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return status;
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}
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mlx_status
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nvconfig_nvdata_invalidate(
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IN mlx_utils *utils,
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IN mlx_uint8 port,
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IN mlx_uint16 tlv_type
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)
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{
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mlx_status status = MLX_SUCCESS;
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struct nvconfig_header nv_header;
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mlx_uint32 reg_status;
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NVRAM_CLASS_CODE class_code;
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mlx_uint16 real_tlv_type;
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if (utils == NULL) {
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status = MLX_INVALID_PARAMETER;
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goto bad_param;
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}
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status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
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MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
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mlx_memory_set(utils, &nv_header, 0, sizeof(nv_header));
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nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nv_header.tlv_type);
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status = mlx_reg_access(utils, REG_ID_NVDI, REG_ACCESS_WRITE, &nv_header, sizeof(nv_header),
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®_status);
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MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
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if (reg_status != 0) {
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MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
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status = MLX_FAILED;
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goto reg_err;
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}
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reg_err:
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tlv_not_supported:
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bad_param:
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return status;
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}
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mlx_status
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nvconfig_nvdata_access(
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IN mlx_utils *utils,
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IN mlx_uint8 port,
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IN mlx_uint16 tlv_type,
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IN REG_ACCESS_OPT opt,
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IN mlx_size data_size,
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IN NV_DEFAULT_OPT def_en,
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IN OUT mlx_uint8 *version,
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IN OUT mlx_void *data
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)
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{
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mlx_status status = MLX_SUCCESS;
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struct nvconfig_nvda nvda;
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mlx_uint32 reg_status;
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mlx_uint32 real_size_to_read;
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mlx_uint32 index;
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NVRAM_CLASS_CODE class_code;
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mlx_uint16 real_tlv_type;
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mlx_size data_size_align_to_dword;
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if (utils == NULL || data == NULL || data_size > NVCONFIG_MAX_TLV_SIZE) {
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status = MLX_INVALID_PARAMETER;
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goto bad_param;
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}
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status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
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MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
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data_size_align_to_dword = ((data_size + 3) / sizeof(mlx_uint32)) * sizeof(mlx_uint32);
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mlx_memory_set(utils, &nvda, 0, sizeof(nvda));
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nvda.nv_header.length = data_size_align_to_dword;
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nvda.nv_header.rd_en = 0;
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nvda.nv_header.def_en = def_en;
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nvda.nv_header.over_en = 1;
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nvda.nv_header.version = *version;
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nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nvda.nv_header.tlv_type);
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mlx_memory_cpy(utils, nvda.data, data, data_size);
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for (index = 0 ; index * 4 < NVCONFIG_MAX_TLV_SIZE ; index++) {
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mlx_memory_be32_to_cpu(utils,(((mlx_uint32 *)nvda.data)[index]), ((mlx_uint32 *)nvda.data) + index);
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}
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status = mlx_reg_access(utils, REG_ID_NVDA, opt, &nvda,
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data_size_align_to_dword + sizeof(nvda.nv_header), ®_status);
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MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
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if (reg_status != 0) {
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MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
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status = MLX_FAILED;
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goto reg_err;
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}
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for (index = 0 ; index * 4 < NVCONFIG_MAX_TLV_SIZE ; index++) {
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mlx_memory_cpu_to_be32(utils,(((mlx_uint32 *)nvda.data)[index]), ((mlx_uint32 *)nvda.data) + index);
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}
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if (opt == REG_ACCESS_READ) {
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real_size_to_read = (nvda.nv_header.length > data_size) ? data_size :
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nvda.nv_header.length;
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mlx_memory_cpy(utils, data, nvda.data, real_size_to_read);
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*version = nvda.nv_header.version;
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} else {
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nvconfig_set_fw_reset_level(utils, tlv_type);
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}
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reg_err:
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tlv_not_supported:
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bad_param:
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return status;
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}
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