151 lines
5.2 KiB
C
151 lines
5.2 KiB
C
#ifndef MLX_LINK_SPEED_H_
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#define MLX_LINK_SPEED_H_
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/*
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* Copyright (C) 2015 Mellanox Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include "../../mlx_lib/mlx_reg_access/mlx_reg_access.h"
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#include "../../include/public/mlx_utils.h"
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#define LINK_SPEED_100GB_MASK (ETH_SPEED_ENABLE_MASK_100GBASECR4 | ETH_SPEED_ENABLE_MASK_100GBASESR4 | ETH_SPEED_ENABLE_MASK_100GBASEKR4 | ETH_SPEED_ENABLE_MASK_100GBASELR4)
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#define LINK_SPEED_56GB_MASK (ETH_SPEED_ENABLE_MASK_56GBASER4)
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#define LINK_SPEED_50GB_MASK (ETH_SPEED_ENABLE_MASK_50GBASECR2 | ETH_SPEED_ENABLE_MASK_50GBASEKR2)
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#define LINK_SPEED_40GB_MASK (ETH_SPEED_ENABLE_MASK_40GBASECR4 | ETH_SPEED_ENABLE_MASK_40GBASEKR4 | ETH_SPEED_ENABLE_MASK_40GBASESR4 | ETH_SPEED_ENABLE_MASK_40GBASELR4)
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#define LINK_SPEED_25GB_MASK (ETH_SPEED_ENABLE_MASK_25GBASECR | ETH_SPEED_ENABLE_MASK_25GBASEKR | ETH_SPEED_ENABLE_MASK_25GBASESR)
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#define LINK_SPEED_20GB_MASK (ETH_SPEED_ENABLE_MASK_20GBASER2)
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#define LINK_SPEED_10GB_MASK (ETH_SPEED_ENABLE_MASK_10GBASECR | ETH_SPEED_ENABLE_MASK_10GBASESR | ETH_SPEED_ENABLE_MASK_10GBASELR | ETH_SPEED_ENABLE_MASK_10GBASEKR)
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#define LINK_SPEED_1GB_MASK (ETH_SPEED_ENABLE_MASK_1000BASECX | ETH_SPEED_ENABLE_MASK_1000BASEKX | ETH_SPEED_ENABLE_MASK_100BaseTX | ETH_SPEED_ENABLE_MASK_1000BASET)
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#define LINK_SPEED_SDR_MASK 0x1
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#define LINK_SPEED_DDR_MASK 0x2
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#define LINK_SPEED_QDR_MASK 0xC
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#define LINK_SPEED_FDR_MASK 0x10
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#define LINK_SPEED_EDR20_MASK 0x200
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#define LINK_SPEED_EDR_MASK 0x20
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#define LINK_SPEED_WITDH_1_MASK 0x1
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#define LINK_SPEED_WITDH_2_MASK 0x2
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#define LINK_SPEED_WITDH_4_MASK 0x4
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#define LINK_SPEED_WITDH_8_MASK 0x8
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#define LINK_SPEED_WITDH_12_MASK 0x10
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#define GIGA_TO_BIT 0x40000000
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enum {
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ETH_SPEED_ENABLE_MASK_1000BASECX = 0x0001,
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ETH_SPEED_ENABLE_MASK_1000BASEKX = 0x0002,
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ETH_SPEED_ENABLE_MASK_10GBASECX4 = 0x0004,
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ETH_SPEED_ENABLE_MASK_10GBASEKX4 = 0x0008,
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ETH_SPEED_ENABLE_MASK_10GBASEKR = 0x0010,
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ETH_SPEED_ENABLE_MASK_20GBASER2 = 0x0020,
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ETH_SPEED_ENABLE_MASK_40GBASECR4 = 0x0040,
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ETH_SPEED_ENABLE_MASK_40GBASEKR4 = 0x0080,
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ETH_SPEED_ENABLE_MASK_56GBASER4 = 0x0100,
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ETH_SPEED_ENABLE_MASK_10GBASECR = 0x1000,
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ETH_SPEED_ENABLE_MASK_10GBASESR = 0x2000,
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ETH_SPEED_ENABLE_MASK_10GBASELR = 0x4000,
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ETH_SPEED_ENABLE_MASK_40GBASESR4 = 0x8000,
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ETH_SPEED_ENABLE_MASK_40GBASELR4 = 0x10000,
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ETH_SPEED_ENABLE_MASK_50GBASEKR4 = 0x80000,
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ETH_SPEED_ENABLE_MASK_100GBASECR4 = 0x100000,
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ETH_SPEED_ENABLE_MASK_100GBASESR4 = 0x200000,
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ETH_SPEED_ENABLE_MASK_100GBASEKR4 = 0x400000,
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ETH_SPEED_ENABLE_MASK_100GBASELR4 = 0x800000,
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ETH_SPEED_ENABLE_MASK_100BaseTX = 0x1000000,
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ETH_SPEED_ENABLE_MASK_1000BASET = 0x2000000,
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ETH_SPEED_ENABLE_MASK_10GBASET = 0x4000000,
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ETH_SPEED_ENABLE_MASK_25GBASECR = 0x8000000,
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ETH_SPEED_ENABLE_MASK_25GBASEKR = 0x10000000,
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ETH_SPEED_ENABLE_MASK_25GBASESR = 0x20000000,
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ETH_SPEED_ENABLE_MASK_50GBASECR2 = 0x40000000,
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ETH_SPEED_ENABLE_MASK_50GBASEKR2 = 0x80000000,
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ETH_SPEED_ENABLE_MASK_BAD = 0xffff,
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};
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typedef enum {
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LINK_SPEED_IB = 0,
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LINK_SPEED_FC,
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LINK_SPEED_ETH,
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} LINK_SPEED_TYPE;
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typedef enum {
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LINK_SPEED_1GB = 0,
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LINK_SPEED_10GB,
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LINK_SPEED_40GB,
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LINK_SPEED_100GB,
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LINK_SPEED_SDR,
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LINK_SPEED_DEFAULT,
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} LINK_SPEED;
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struct mlx_link_speed {
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mlx_uint32 proto_mask :3;
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mlx_uint32 reserved1 :13;
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mlx_uint32 loacl_port :8;
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mlx_uint32 reserved2 :8;
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/* -------------- */
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mlx_uint32 reserved3 :32;
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/* -------------- */
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mlx_uint32 reserved4 :32;
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/* -------------- */
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mlx_uint32 eth_proto_capability :32;
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/* -------------- */
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mlx_uint32 ib_proto_capability :16;
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mlx_uint32 ib_link_width_capability :16;
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/* -------------- */
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mlx_uint32 reserved5 :32;
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/* -------------- */
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mlx_uint32 eth_proto_admin :32;
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/* -------------- */
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mlx_uint32 ib_proto_admin :16;
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mlx_uint32 ib_link_width_admin :16;
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/* -------------- */
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mlx_uint32 reserved6 :32;
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/* -------------- */
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mlx_uint32 eth_proto_oper :32;
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/* -------------- */
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mlx_uint32 ib_proto_oper :16;
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mlx_uint32 ib_link_width_oper :16;
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/* -------------- */
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mlx_uint32 reserved7 :32;
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/* -------------- */
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mlx_uint32 eth_proto_lp_advertise :32;
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mlx_uint32 reserved[3];
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};
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mlx_status
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mlx_set_link_speed(
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IN mlx_utils *utils,
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IN mlx_uint8 port_num,
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IN LINK_SPEED_TYPE type,
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IN LINK_SPEED speed
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);
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mlx_status
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mlx_get_max_speed(
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IN mlx_utils *utils,
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IN mlx_uint8 port_num,
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IN LINK_SPEED_TYPE type,
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OUT mlx_uint64 *speed
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);
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#endif /* MLX_LINK_SPEED_H_ */
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