345 lines
9.2 KiB
C
Executable File
345 lines
9.2 KiB
C
Executable File
#ifndef _GOLAN_H_
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#define _GOLAN_H_
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/*
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* Copyright (C) 2013-2015 Mellanox Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <ipxe/pci.h>
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#include <ipxe/pcibackup.h>
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#include <byteswap.h>
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#include <errno.h>
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#include <ipxe/io.h>
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#include <stdio.h>
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#include <unistd.h>
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#include "CIB_PRM.h"
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#include "mlx_utils/include/public/mlx_utils.h"
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#define GOLAN_PCI_CONFIG_BAR_SIZE 0x100000//HERMON_PCI_CONFIG_BAR_SIZE //TODO: What is the BAR size?
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#define GOLAN_PAS_SIZE sizeof(uint64_t)
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#define GOLAN_INVALID_LKEY 0x00000100UL
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#define GOLAN_MAX_PORTS 2
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#define GOLAN_PORT_BASE 1
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#define MELLANOX_VID 0x15b3
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#define GOLAN_HCA_BAR PCI_BASE_ADDRESS_0 //BAR 0
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#define GOLAN_HCR_MAX_WAIT_MS 10000
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#define min(a,b) ((a)<(b)?(a):(b))
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#define GOLAN_PAGE_SHIFT 12
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#define GOLAN_PAGE_SIZE (1 << GOLAN_PAGE_SHIFT)
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#define GOLAN_PAGE_MASK (GOLAN_PAGE_SIZE - 1)
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#define MAX_MBOX ( GOLAN_PAGE_SIZE / MAILBOX_STRIDE )
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#define DEF_CMD_IDX 1
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#define MEM_CMD_IDX 0
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#define NO_MBOX 0xffff
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#define MEM_MBOX MEM_CMD_IDX
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#define GEN_MBOX DEF_CMD_IDX
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#define CMD_IF_REV 4
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#define MAX_PASE_MBOX ((GOLAN_CMD_PAS_CNT) - 2)
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#define CMD_STATUS( golan , idx ) ((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->status
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#define CMD_SYND( golan , idx ) ((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->syndrome
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#define QRY_PAGES_OUT( golan, idx ) ((struct golan_query_pages_outbox *)(get_cmd( (golan) , (idx) )->out))
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#define VIRT_2_BE64_BUS( addr ) cpu_to_be64(((unsigned long long )virt_to_bus(addr)))
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#define BE64_BUS_2_VIRT( addr ) bus_to_virt(be64_to_cpu(addr))
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#define USR_2_BE64_BUS( addr ) cpu_to_be64(((unsigned long long )user_to_phys(addr, 0)))
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#define BE64_BUS_2_USR( addr ) be64_to_cpu(phys_to_user(addr))
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#define GET_INBOX(golan, idx) (&(((struct mbox *)(golan->mboxes.inbox))[idx]))
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#define GET_OUTBOX(golan, idx) (&(((struct mbox *)(golan->mboxes.outbox))[idx]))
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#define GOLAN_MBOX_IN( cmd_ptr, in_ptr ) ( { \
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union { \
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__be32 raw[4]; \
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typeof ( *(in_ptr) ) cooked; \
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} *u = container_of ( &(cmd_ptr)->in[0], typeof ( *u ), raw[0] ); \
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&u->cooked; } )
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#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
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/* Fw status fields */
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typedef enum {
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NO_ERRORS = 0x0,
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SIGNATURE_ERROR = 0x1,
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TOKEN_ERROR = 0x2,
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BAD_BLOCK_NUMBER = 0x3,
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BAD_OUTPUT_POINTER = 0x4, // pointer not align to mailbox size
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BAD_INPUT_POINTER = 0x5, // pointer not align to mailbox size
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INTERNAL_ERROR = 0x6,
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INPUT_LEN_ERROR = 0x7, // input length less than 0x8.
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OUTPUT_LEN_ERROR = 0x8, // output length less than 0x8.
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RESERVE_NOT_ZERO = 0x9,
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BAD_CMD_TYPE = 0x10,
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} return_hdr_t;
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struct golan_cmdq_md {
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void *addr;
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u16 log_stride;
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u16 size;
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};
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struct golan_uar {
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uint32_t index;
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void *virt;
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unsigned long phys;
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};
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struct golan_firmware_area {
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/* length of area in pages */
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uint32_t npages;
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/** Firmware area in external memory
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*
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* This is allocated when first needed, and freed only on
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* final teardown, in order to avoid memory map changes at
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* runtime.
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*/
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userptr_t area;
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};
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/* Queue Pair */
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#define GOLAN_SEND_WQE_BB_SIZE 64
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#define GOLAN_SEND_UD_WQE_SIZE sizeof(struct golan_send_wqe_ud)
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#define GOLAN_RECV_WQE_SIZE sizeof(struct golan_recv_wqe_ud)
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#define GOLAN_WQEBBS_PER_SEND_UD_WQE DIV_ROUND_UP(GOLAN_SEND_UD_WQE_SIZE, GOLAN_SEND_WQE_BB_SIZE)
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#define GOLAN_SEND_OPCODE 0x0a
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#define GOLAN_WQE_CTRL_WQE_IDX_BIT 8
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enum golan_ib_qp_state {
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GOLAN_IB_QPS_RESET,
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GOLAN_IB_QPS_INIT,
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GOLAN_IB_QPS_RTR,
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GOLAN_IB_QPS_RTS,
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GOLAN_IB_QPS_SQD,
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GOLAN_IB_QPS_SQE,
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GOLAN_IB_QPS_ERR
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};
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struct golan_send_wqe_ud {
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struct golan_wqe_ctrl_seg ctrl;
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struct golan_av datagram;
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struct golan_wqe_data_seg data;
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};
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union golan_send_wqe {
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struct golan_send_wqe_ud ud;
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uint8_t pad[GOLAN_WQEBBS_PER_SEND_UD_WQE * GOLAN_SEND_WQE_BB_SIZE];
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};
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struct golan_recv_wqe_ud {
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struct golan_wqe_data_seg data[2];
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};
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struct golan_recv_wq {
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struct golan_recv_wqe_ud *wqes;
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/* WQ size in bytes */
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int size;
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/* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
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u16 next_idx;
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/** GRH buffers (if applicable) */
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struct ib_global_route_header *grh;
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/** Size of GRH buffers */
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size_t grh_size;
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};
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struct golan_send_wq {
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union golan_send_wqe *wqes;
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/* WQ size in bytes */
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int size;
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/* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
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u16 next_idx;
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};
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struct golan_queue_pair {
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void *wqes;
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int size;
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struct golan_recv_wq rq;
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struct golan_send_wq sq;
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struct golan_qp_db *doorbell_record;
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u32 doorbell_qpn;
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enum golan_ib_qp_state state;
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};
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/* Completion Queue */
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#define GOLAN_CQE_OPCODE_NOT_VALID 0x0f
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#define GOLAN_CQE_OPCODE_BIT 4
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#define GOLAN_CQ_DB_RECORD_SIZE sizeof(uint64_t)
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#define GOLAN_CQE_OWNER_MASK 1
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#define MANAGE_PAGES_PSA_OFFSET 0
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#define PXE_CMDIF_REF 5
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enum {
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GOLAN_CQE_SW_OWNERSHIP = 0x0,
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GOLAN_CQE_HW_OWNERSHIP = 0x1
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};
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enum {
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GOLAN_CQE_SIZE_64 = 0,
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GOLAN_CQE_SIZE_128 = 1
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};
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struct golan_completion_queue {
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struct golan_cqe64 *cqes;
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int size;
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__be64 *doorbell_record;
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};
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/* Event Queue */
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#define GOLAN_EQE_SIZE sizeof(struct golan_eqe)
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#define GOLAN_NUM_EQES 8
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#define GOLAN_EQ_DOORBELL_OFFSET 0x40
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#define DB_BUFFER0_EVEN_OFFSET 0x800
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#define DB_BUFFER0_ODD_OFFSET 0x900
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#define GOLAN_EQ_MAP_ALL_EVENTS \
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((1 << GOLAN_EVENT_TYPE_PATH_MIG )| \
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(1 << GOLAN_EVENT_TYPE_COMM_EST )| \
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(1 << GOLAN_EVENT_TYPE_SQ_DRAINED )| \
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(1 << GOLAN_EVENT_TYPE_SRQ_LAST_WQE )| \
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(1 << GOLAN_EVENT_TYPE_SRQ_RQ_LIMIT )| \
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(1 << GOLAN_EVENT_TYPE_CQ_ERROR )| \
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(1 << GOLAN_EVENT_TYPE_WQ_CATAS_ERROR )| \
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(1 << GOLAN_EVENT_TYPE_PATH_MIG_FAILED )| \
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(1 << GOLAN_EVENT_TYPE_WQ_INVAL_REQ_ERROR )| \
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(1 << GOLAN_EVENT_TYPE_WQ_ACCESS_ERROR )| \
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(1 << GOLAN_EVENT_TYPE_SRQ_CATAS_ERROR )| \
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(1 << GOLAN_EVENT_TYPE_INTERNAL_ERROR )| \
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(1 << GOLAN_EVENT_TYPE_PORT_CHANGE )| \
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(1 << GOLAN_EVENT_TYPE_GPIO_EVENT )| \
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(1 << GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER )| \
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(1 << GOLAN_EVENT_TYPE_REMOTE_CONFIG )| \
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(1 << GOLAN_EVENT_TYPE_DB_BF_CONGESTION )| \
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(1 << GOLAN_EVENT_TYPE_STALL_EVENT )| \
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(1 << GOLAN_EVENT_TYPE_PACKET_DROPPED )| \
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(1 << GOLAN_EVENT_TYPE_CMD )| \
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(1 << GOLAN_EVENT_TYPE_PAGE_REQUEST ))
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enum golan_event {
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GOLAN_EVENT_TYPE_COMP = 0x0,
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GOLAN_EVENT_TYPE_PATH_MIG = 0x01,
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GOLAN_EVENT_TYPE_COMM_EST = 0x02,
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GOLAN_EVENT_TYPE_SQ_DRAINED = 0x03,
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GOLAN_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
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GOLAN_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
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GOLAN_EVENT_TYPE_CQ_ERROR = 0x04,
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GOLAN_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
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GOLAN_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
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GOLAN_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
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GOLAN_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
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GOLAN_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
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GOLAN_EVENT_TYPE_INTERNAL_ERROR = 0x08,
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GOLAN_EVENT_TYPE_PORT_CHANGE = 0x09,
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GOLAN_EVENT_TYPE_GPIO_EVENT = 0x15,
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// GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER = 0x16,
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GOLAN_EVENT_TYPE_REMOTE_CONFIG = 0x19,
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GOLAN_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
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GOLAN_EVENT_TYPE_STALL_EVENT = 0x1b,
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GOLAN_EVENT_TYPE_PACKET_DROPPED = 0x1f,
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GOLAN_EVENT_TYPE_CMD = 0x0a,
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GOLAN_EVENT_TYPE_PAGE_REQUEST = 0x0b,
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GOLAN_EVENT_TYPE_PAGE_FAULT = 0x0C,
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};
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enum golan_port_sub_event {
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GOLAN_PORT_CHANGE_SUBTYPE_DOWN = 1,
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GOLAN_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
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GOLAN_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
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GOLAN_PORT_CHANGE_SUBTYPE_LID = 6,
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GOLAN_PORT_CHANGE_SUBTYPE_PKEY = 7,
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GOLAN_PORT_CHANGE_SUBTYPE_GUID = 8,
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GOLAN_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9
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};
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enum {
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GOLAN_EQE_SW_OWNERSHIP = 0x0,
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GOLAN_EQE_HW_OWNERSHIP = 0x1
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};
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enum {
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GOLAN_EQ_UNARMED = 0,
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GOLAN_EQ_ARMED = 1,
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};
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struct golan_event_queue {
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uint8_t eqn;
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uint64_t mask;
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struct golan_eqe *eqes;
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int size;
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__be32 *doorbell;
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uint32_t cons_index;
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};
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struct golan_port {
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/** Infiniband device */
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struct ib_device *ibdev;
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/** Network device */
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struct net_device *netdev;
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/** VEP number */
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u8 vep_number;
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};
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struct golan_mboxes {
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void *inbox;
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void *outbox;
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};
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#define GOLAN_OPEN 0x1
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struct golan {
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struct pci_device *pci;
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struct golan_hca_init_seg *iseg;
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struct golan_cmdq_md cmd;
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struct golan_hca_cap caps; /* stored as big indian*/
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struct golan_mboxes mboxes;
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struct list_head pages;
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uint32_t cmd_bm;
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uint32_t total_dma_pages;
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struct golan_uar uar;
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struct golan_event_queue eq;
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uint32_t pdn;
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u32 mkey;
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u32 flags;
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mlx_utils *utils;
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struct golan_port ports[GOLAN_MAX_PORTS];
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#define GOLAN_FW_AREAS_NUM 2
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struct golan_firmware_area fw_areas[GOLAN_FW_AREAS_NUM];
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};
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#endif /* _GOLAN_H_*/
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