349 lines
9.7 KiB
C
349 lines
9.7 KiB
C
#ifndef _INTEL_H
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#define _INTEL_H
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/** @file
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*
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* Intel 10/100/1000 network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/nvs.h>
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/** Intel BAR size */
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#define INTEL_BAR_SIZE ( 128 * 1024 )
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/** A packet descriptor */
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struct intel_descriptor {
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/** Buffer address */
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uint64_t address;
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/** Length */
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uint16_t length;
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/** Flags */
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uint8_t flags;
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/** Command */
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uint8_t command;
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/** Status */
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uint32_t status;
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} __attribute__ (( packed ));
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/** Descriptor type */
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#define INTEL_DESC_FL_DTYP( dtyp ) ( (dtyp) << 4 )
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#define INTEL_DESC_FL_DTYP_DATA INTEL_DESC_FL_DTYP ( 0x03 )
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/** Descriptor extension */
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#define INTEL_DESC_CMD_DEXT 0x20
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/** Report status */
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#define INTEL_DESC_CMD_RS 0x08
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/** Insert frame checksum (CRC) */
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#define INTEL_DESC_CMD_IFCS 0x02
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/** End of packet */
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#define INTEL_DESC_CMD_EOP 0x01
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/** Descriptor done */
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#define INTEL_DESC_STATUS_DD 0x00000001UL
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/** Receive error */
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#define INTEL_DESC_STATUS_RXE 0x00000100UL
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/** Payload length */
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#define INTEL_DESC_STATUS_PAYLEN( len ) ( (len) << 14 )
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/** Device Control Register */
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#define INTEL_CTRL 0x00000UL
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#define INTEL_CTRL_LRST 0x00000008UL /**< Link reset */
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#define INTEL_CTRL_ASDE 0x00000020UL /**< Auto-speed detection */
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#define INTEL_CTRL_SLU 0x00000040UL /**< Set link up */
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#define INTEL_CTRL_FRCSPD 0x00000800UL /**< Force speed */
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#define INTEL_CTRL_FRCDPLX 0x00001000UL /**< Force duplex */
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#define INTEL_CTRL_RST 0x04000000UL /**< Device reset */
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#define INTEL_CTRL_PHY_RST 0x80000000UL /**< PHY reset */
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/** Time to delay for device reset, in milliseconds */
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#define INTEL_RESET_DELAY_MS 20
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/** Device Status Register */
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#define INTEL_STATUS 0x00008UL
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#define INTEL_STATUS_LU 0x00000002UL /**< Link up */
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/** EEPROM Read Register */
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#define INTEL_EERD 0x00014UL
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#define INTEL_EERD_START 0x00000001UL /**< Start read */
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#define INTEL_EERD_DONE_SMALL 0x00000010UL /**< Read done (small EERD) */
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#define INTEL_EERD_DONE_LARGE 0x00000002UL /**< Read done (large EERD) */
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#define INTEL_EERD_ADDR_SHIFT_SMALL 8 /**< Address shift (small) */
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#define INTEL_EERD_ADDR_SHIFT_LARGE 2 /**< Address shift (large) */
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#define INTEL_EERD_DATA(value) ( (value) >> 16 ) /**< Read data */
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/** Maximum time to wait for EEPROM read, in milliseconds */
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#define INTEL_EEPROM_MAX_WAIT_MS 100
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/** EEPROM word length */
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#define INTEL_EEPROM_WORD_LEN_LOG2 1
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/** Minimum EEPROM size, in words */
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#define INTEL_EEPROM_MIN_SIZE_WORDS 64
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/** Offset of MAC address within EEPROM */
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#define INTEL_EEPROM_MAC 0x00
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/** Interrupt Cause Read Register */
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#define INTEL_ICR 0x000c0UL
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#define INTEL_IRQ_TXDW 0x00000001UL /**< Transmit descriptor done */
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#define INTEL_IRQ_TXQE 0x00000002UL /**< Transmit queue empty */
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#define INTEL_IRQ_LSC 0x00000004UL /**< Link status change */
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#define INTEL_IRQ_RXDMT0 0x00000010UL /**< Receive queue low */
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#define INTEL_IRQ_RXO 0x00000040UL /**< Receive overrun */
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#define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
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/** Interrupt Mask Set/Read Register */
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#define INTEL_IMS 0x000d0UL
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/** Interrupt Mask Clear Register */
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#define INTEL_IMC 0x000d8UL
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/** Receive Control Register */
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#define INTEL_RCTL 0x00100UL
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#define INTEL_RCTL_EN 0x00000002UL /**< Receive enable */
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#define INTEL_RCTL_UPE 0x00000008UL /**< Unicast promiscuous mode */
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#define INTEL_RCTL_MPE 0x00000010UL /**< Multicast promiscuous */
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#define INTEL_RCTL_BAM 0x00008000UL /**< Broadcast accept mode */
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#define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
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( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
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#define INTEL_RCTL_BSIZE_2048 INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
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#define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
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#define INTEL_RCTL_SECRC 0x04000000UL /**< Strip CRC */
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/** Transmit Control Register */
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#define INTEL_TCTL 0x00400UL
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#define INTEL_TCTL_EN 0x00000002UL /**< Transmit enable */
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#define INTEL_TCTL_PSP 0x00000008UL /**< Pad short packets */
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#define INTEL_TCTL_CT(x) ( (x) << 4 ) /**< Collision threshold */
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#define INTEL_TCTL_CT_DEFAULT INTEL_TCTL_CT ( 0x0f )
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#define INTEL_TCTL_CT_MASK INTEL_TCTL_CT ( 0xff )
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#define INTEL_TCTL_COLD(x) ( (x) << 12 ) /**< Collision distance */
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#define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
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#define INTEL_TCTL_COLD_MASK INTEL_TCTL_COLD ( 0x3ff )
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/** Packet Buffer Allocation */
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#define INTEL_PBA 0x01000UL
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/** Packet Buffer Size */
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#define INTEL_PBS 0x01008UL
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/** Receive Descriptor register block */
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#define INTEL_RD 0x02800UL
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/** Number of receive descriptors
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*
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* Minimum value is 8, since the descriptor ring length must be a
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* multiple of 128.
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*/
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#define INTEL_NUM_RX_DESC 16
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/** Receive descriptor ring fill level */
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#define INTEL_RX_FILL 8
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/** Receive buffer length */
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#define INTEL_RX_MAX_LEN 2048
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/** Transmit Descriptor register block */
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#define INTEL_TD 0x03800UL
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/** Number of transmit descriptors
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*
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* Descriptor ring length must be a multiple of 16. ICH8/9/10
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* requires a minimum of 16 TX descriptors.
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*/
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#define INTEL_NUM_TX_DESC 16
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/** Transmit descriptor ring maximum fill level */
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#define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
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/** Receive/Transmit Descriptor Base Address Low (offset) */
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#define INTEL_xDBAL 0x00
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/** Receive/Transmit Descriptor Base Address High (offset) */
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#define INTEL_xDBAH 0x04
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/** Receive/Transmit Descriptor Length (offset) */
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#define INTEL_xDLEN 0x08
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/** Receive/Transmit Descriptor Head (offset) */
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#define INTEL_xDH 0x10
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/** Receive/Transmit Descriptor Tail (offset) */
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#define INTEL_xDT 0x18
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/** Receive/Transmit Descriptor Control (offset) */
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#define INTEL_xDCTL 0x28
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#define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */
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/** Maximum time to wait for queue disable, in milliseconds */
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#define INTEL_DISABLE_MAX_WAIT_MS 100
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/** Receive Address Low */
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#define INTEL_RAL0 0x05400UL
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/** Receive Address High */
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#define INTEL_RAH0 0x05404UL
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#define INTEL_RAH0_AV 0x80000000UL /**< Address valid */
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/** Receive address */
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union intel_receive_address {
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struct {
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uint32_t low;
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uint32_t high;
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} __attribute__ (( packed )) reg;
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uint8_t raw[ETH_ALEN];
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};
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/** An Intel descriptor ring */
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struct intel_ring {
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/** Descriptors */
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struct intel_descriptor *desc;
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/** Producer index */
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unsigned int prod;
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/** Consumer index */
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unsigned int cons;
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/** Register block */
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unsigned int reg;
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/** Length (in bytes) */
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size_t len;
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/** Populate descriptor
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*
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* @v desc Descriptor
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* @v addr Data buffer address
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* @v len Length of data
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*/
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void ( * describe ) ( struct intel_descriptor *desc, physaddr_t addr,
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size_t len );
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};
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/**
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* Initialise descriptor ring
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*
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* @v ring Descriptor ring
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* @v count Number of descriptors
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* @v reg Descriptor register block
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* @v describe Method to populate descriptor
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*/
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static inline __attribute__ (( always_inline)) void
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intel_init_ring ( struct intel_ring *ring, unsigned int count, unsigned int reg,
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void ( * describe ) ( struct intel_descriptor *desc,
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physaddr_t addr, size_t len ) ) {
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ring->len = ( count * sizeof ( ring->desc[0] ) );
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ring->reg = reg;
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ring->describe = describe;
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}
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/** An Intel virtual function mailbox */
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struct intel_mailbox {
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/** Mailbox control register */
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unsigned int ctrl;
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/** Mailbox memory base */
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unsigned int mem;
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};
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/**
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* Initialise mailbox
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*
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* @v mbox Mailbox
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* @v ctrl Mailbox control register
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* @v mem Mailbox memory register base
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*/
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static inline __attribute__ (( always_inline )) void
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intel_init_mbox ( struct intel_mailbox *mbox, unsigned int ctrl,
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unsigned int mem ) {
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mbox->ctrl = ctrl;
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mbox->mem = mem;
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}
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/** An Intel network card */
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struct intel_nic {
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/** Registers */
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void *regs;
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/** Port number (for multi-port devices) */
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unsigned int port;
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/** Flags */
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unsigned int flags;
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/** Forced interrupts */
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unsigned int force_icr;
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/** EEPROM */
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struct nvs_device eeprom;
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/** EEPROM done flag */
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uint32_t eerd_done;
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/** EEPROM address shift */
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unsigned int eerd_addr_shift;
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/** Mailbox */
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struct intel_mailbox mbox;
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/** Transmit descriptor ring */
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struct intel_ring tx;
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/** Receive descriptor ring */
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struct intel_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[INTEL_NUM_RX_DESC];
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};
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/** Driver flags */
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enum intel_flags {
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/** PBS/PBA errata workaround required */
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INTEL_PBS_ERRATA = 0x0001,
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/** VMware missing interrupt workaround required */
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INTEL_VMWARE = 0x0002,
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/** PHY reset is broken */
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INTEL_NO_PHY_RST = 0x0004,
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};
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/**
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* Dump diagnostic information
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*
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* @v intel Intel device
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*/
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static inline void intel_diag ( struct intel_nic *intel ) {
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DBGC ( intel, "INTEL %p TX %04x(%02x)/%04x(%02x) "
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"RX %04x(%02x)/%04x(%02x)\n", intel,
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( intel->tx.cons & 0xffff ),
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readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
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( intel->tx.prod & 0xffff ),
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readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
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( intel->rx.cons & 0xffff ),
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readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
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( intel->rx.prod & 0xffff ),
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readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
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}
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extern void intel_describe_tx ( struct intel_descriptor *tx,
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physaddr_t addr, size_t len );
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extern void intel_describe_tx_adv ( struct intel_descriptor *tx,
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physaddr_t addr, size_t len );
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extern void intel_describe_rx ( struct intel_descriptor *rx,
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physaddr_t addr, size_t len );
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extern void intel_reset_ring ( struct intel_nic *intel, unsigned int reg );
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extern int intel_create_ring ( struct intel_nic *intel,
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struct intel_ring *ring );
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extern void intel_destroy_ring ( struct intel_nic *intel,
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struct intel_ring *ring );
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extern void intel_refill_rx ( struct intel_nic *intel );
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extern void intel_empty_rx ( struct intel_nic *intel );
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extern int intel_transmit ( struct net_device *netdev,
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struct io_buffer *iobuf );
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extern void intel_poll_tx ( struct net_device *netdev );
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extern void intel_poll_rx ( struct net_device *netdev );
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#endif /* _INTEL_H */
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