333 lines
15 KiB
C
333 lines
15 KiB
C
/******************************************************************************
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* include/public/trace.h
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Mark Williamson, (C) 2004 Intel Research Cambridge
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* Copyright (C) 2005 Bin Ren
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*/
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#ifndef __XEN_PUBLIC_TRACE_H__
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#define __XEN_PUBLIC_TRACE_H__
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FILE_LICENCE ( MIT );
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#define TRACE_EXTRA_MAX 7
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#define TRACE_EXTRA_SHIFT 28
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/* Trace classes */
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#define TRC_CLS_SHIFT 16
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#define TRC_GEN 0x0001f000 /* General trace */
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#define TRC_SCHED 0x0002f000 /* Xen Scheduler trace */
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#define TRC_DOM0OP 0x0004f000 /* Xen DOM0 operation trace */
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#define TRC_HVM 0x0008f000 /* Xen HVM trace */
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#define TRC_MEM 0x0010f000 /* Xen memory trace */
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#define TRC_PV 0x0020f000 /* Xen PV traces */
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#define TRC_SHADOW 0x0040f000 /* Xen shadow tracing */
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#define TRC_HW 0x0080f000 /* Xen hardware-related traces */
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#define TRC_GUEST 0x0800f000 /* Guest-generated traces */
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#define TRC_ALL 0x0ffff000
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#define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff)
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#define TRC_HD_CYCLE_FLAG (1UL<<31)
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#define TRC_HD_INCLUDES_CYCLE_COUNT(x) ( !!( (x) & TRC_HD_CYCLE_FLAG ) )
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#define TRC_HD_EXTRA(x) (((x)>>TRACE_EXTRA_SHIFT)&TRACE_EXTRA_MAX)
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/* Trace subclasses */
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#define TRC_SUBCLS_SHIFT 12
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/* trace subclasses for SVM */
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#define TRC_HVM_ENTRYEXIT 0x00081000 /* VMENTRY and #VMEXIT */
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#define TRC_HVM_HANDLER 0x00082000 /* various HVM handlers */
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#define TRC_HVM_EMUL 0x00084000 /* emulated devices */
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#define TRC_SCHED_MIN 0x00021000 /* Just runstate changes */
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#define TRC_SCHED_CLASS 0x00022000 /* Scheduler-specific */
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#define TRC_SCHED_VERBOSE 0x00028000 /* More inclusive scheduling */
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/*
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* The highest 3 bits of the last 12 bits of TRC_SCHED_CLASS above are
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* reserved for encoding what scheduler produced the information. The
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* actual event is encoded in the last 9 bits.
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*
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* This means we have 8 scheduling IDs available (which means at most 8
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* schedulers generating events) and, in each scheduler, up to 512
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* different events.
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*/
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#define TRC_SCHED_ID_BITS 3
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#define TRC_SCHED_ID_SHIFT (TRC_SUBCLS_SHIFT - TRC_SCHED_ID_BITS)
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#define TRC_SCHED_ID_MASK (((1UL<<TRC_SCHED_ID_BITS) - 1) << TRC_SCHED_ID_SHIFT)
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#define TRC_SCHED_EVT_MASK (~(TRC_SCHED_ID_MASK))
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/* Per-scheduler IDs, to identify scheduler specific events */
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#define TRC_SCHED_CSCHED 0
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#define TRC_SCHED_CSCHED2 1
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#define TRC_SCHED_SEDF 2
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#define TRC_SCHED_ARINC653 3
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/* Per-scheduler tracing */
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#define TRC_SCHED_CLASS_EVT(_c, _e) \
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( ( TRC_SCHED_CLASS | \
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((TRC_SCHED_##_c << TRC_SCHED_ID_SHIFT) & TRC_SCHED_ID_MASK) ) + \
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(_e & TRC_SCHED_EVT_MASK) )
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/* Trace classes for Hardware */
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#define TRC_HW_PM 0x00801000 /* Power management traces */
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#define TRC_HW_IRQ 0x00802000 /* Traces relating to the handling of IRQs */
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/* Trace events per class */
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#define TRC_LOST_RECORDS (TRC_GEN + 1)
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#define TRC_TRACE_WRAP_BUFFER (TRC_GEN + 2)
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#define TRC_TRACE_CPU_CHANGE (TRC_GEN + 3)
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#define TRC_SCHED_RUNSTATE_CHANGE (TRC_SCHED_MIN + 1)
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#define TRC_SCHED_CONTINUE_RUNNING (TRC_SCHED_MIN + 2)
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#define TRC_SCHED_DOM_ADD (TRC_SCHED_VERBOSE + 1)
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#define TRC_SCHED_DOM_REM (TRC_SCHED_VERBOSE + 2)
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#define TRC_SCHED_SLEEP (TRC_SCHED_VERBOSE + 3)
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#define TRC_SCHED_WAKE (TRC_SCHED_VERBOSE + 4)
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#define TRC_SCHED_YIELD (TRC_SCHED_VERBOSE + 5)
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#define TRC_SCHED_BLOCK (TRC_SCHED_VERBOSE + 6)
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#define TRC_SCHED_SHUTDOWN (TRC_SCHED_VERBOSE + 7)
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#define TRC_SCHED_CTL (TRC_SCHED_VERBOSE + 8)
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#define TRC_SCHED_ADJDOM (TRC_SCHED_VERBOSE + 9)
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#define TRC_SCHED_SWITCH (TRC_SCHED_VERBOSE + 10)
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#define TRC_SCHED_S_TIMER_FN (TRC_SCHED_VERBOSE + 11)
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#define TRC_SCHED_T_TIMER_FN (TRC_SCHED_VERBOSE + 12)
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#define TRC_SCHED_DOM_TIMER_FN (TRC_SCHED_VERBOSE + 13)
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#define TRC_SCHED_SWITCH_INFPREV (TRC_SCHED_VERBOSE + 14)
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#define TRC_SCHED_SWITCH_INFNEXT (TRC_SCHED_VERBOSE + 15)
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#define TRC_SCHED_SHUTDOWN_CODE (TRC_SCHED_VERBOSE + 16)
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#define TRC_MEM_PAGE_GRANT_MAP (TRC_MEM + 1)
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#define TRC_MEM_PAGE_GRANT_UNMAP (TRC_MEM + 2)
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#define TRC_MEM_PAGE_GRANT_TRANSFER (TRC_MEM + 3)
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#define TRC_MEM_SET_P2M_ENTRY (TRC_MEM + 4)
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#define TRC_MEM_DECREASE_RESERVATION (TRC_MEM + 5)
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#define TRC_MEM_POD_POPULATE (TRC_MEM + 16)
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#define TRC_MEM_POD_ZERO_RECLAIM (TRC_MEM + 17)
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#define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18)
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#define TRC_PV_ENTRY 0x00201000 /* Hypervisor entry points for PV guests. */
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#define TRC_PV_SUBCALL 0x00202000 /* Sub-call in a multicall hypercall */
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#define TRC_PV_HYPERCALL (TRC_PV_ENTRY + 1)
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#define TRC_PV_TRAP (TRC_PV_ENTRY + 3)
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#define TRC_PV_PAGE_FAULT (TRC_PV_ENTRY + 4)
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#define TRC_PV_FORCED_INVALID_OP (TRC_PV_ENTRY + 5)
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#define TRC_PV_EMULATE_PRIVOP (TRC_PV_ENTRY + 6)
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#define TRC_PV_EMULATE_4GB (TRC_PV_ENTRY + 7)
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#define TRC_PV_MATH_STATE_RESTORE (TRC_PV_ENTRY + 8)
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#define TRC_PV_PAGING_FIXUP (TRC_PV_ENTRY + 9)
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#define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV_ENTRY + 10)
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#define TRC_PV_PTWR_EMULATION (TRC_PV_ENTRY + 11)
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#define TRC_PV_PTWR_EMULATION_PAE (TRC_PV_ENTRY + 12)
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#define TRC_PV_HYPERCALL_V2 (TRC_PV_ENTRY + 13)
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#define TRC_PV_HYPERCALL_SUBCALL (TRC_PV_SUBCALL + 14)
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/*
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* TRC_PV_HYPERCALL_V2 format
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*
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* Only some of the hypercall argument are recorded. Bit fields A0 to
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* A5 in the first extra word are set if the argument is present and
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* the arguments themselves are packed sequentially in the following
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* words.
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*
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* The TRC_64_FLAG bit is not set for these events (even if there are
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* 64-bit arguments in the record).
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*
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* Word
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* 0 bit 31 30|29 28|27 26|25 24|23 22|21 20|19 ... 0
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* A5 |A4 |A3 |A2 |A1 |A0 |Hypercall op
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* 1 First 32 bit (or low word of first 64 bit) arg in record
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* 2 Second 32 bit (or high word of first 64 bit) arg in record
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* ...
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*
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* A0-A5 bitfield values:
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*
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* 00b Argument not present
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* 01b 32-bit argument present
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* 10b 64-bit argument present
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* 11b Reserved
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*/
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#define TRC_PV_HYPERCALL_V2_ARG_32(i) (0x1 << (20 + 2*(i)))
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#define TRC_PV_HYPERCALL_V2_ARG_64(i) (0x2 << (20 + 2*(i)))
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#define TRC_PV_HYPERCALL_V2_ARG_MASK (0xfff00000)
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#define TRC_SHADOW_NOT_SHADOW (TRC_SHADOW + 1)
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#define TRC_SHADOW_FAST_PROPAGATE (TRC_SHADOW + 2)
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#define TRC_SHADOW_FAST_MMIO (TRC_SHADOW + 3)
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#define TRC_SHADOW_FALSE_FAST_PATH (TRC_SHADOW + 4)
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#define TRC_SHADOW_MMIO (TRC_SHADOW + 5)
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#define TRC_SHADOW_FIXUP (TRC_SHADOW + 6)
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#define TRC_SHADOW_DOMF_DYING (TRC_SHADOW + 7)
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#define TRC_SHADOW_EMULATE (TRC_SHADOW + 8)
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#define TRC_SHADOW_EMULATE_UNSHADOW_USER (TRC_SHADOW + 9)
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#define TRC_SHADOW_EMULATE_UNSHADOW_EVTINJ (TRC_SHADOW + 10)
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#define TRC_SHADOW_EMULATE_UNSHADOW_UNHANDLED (TRC_SHADOW + 11)
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#define TRC_SHADOW_WRMAP_BF (TRC_SHADOW + 12)
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#define TRC_SHADOW_PREALLOC_UNPIN (TRC_SHADOW + 13)
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#define TRC_SHADOW_RESYNC_FULL (TRC_SHADOW + 14)
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#define TRC_SHADOW_RESYNC_ONLY (TRC_SHADOW + 15)
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/* trace events per subclass */
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#define TRC_HVM_NESTEDFLAG (0x400)
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#define TRC_HVM_VMENTRY (TRC_HVM_ENTRYEXIT + 0x01)
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#define TRC_HVM_VMEXIT (TRC_HVM_ENTRYEXIT + 0x02)
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#define TRC_HVM_VMEXIT64 (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02)
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#define TRC_HVM_PF_XEN (TRC_HVM_HANDLER + 0x01)
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#define TRC_HVM_PF_XEN64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01)
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#define TRC_HVM_PF_INJECT (TRC_HVM_HANDLER + 0x02)
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#define TRC_HVM_PF_INJECT64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02)
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#define TRC_HVM_INJ_EXC (TRC_HVM_HANDLER + 0x03)
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#define TRC_HVM_INJ_VIRQ (TRC_HVM_HANDLER + 0x04)
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#define TRC_HVM_REINJ_VIRQ (TRC_HVM_HANDLER + 0x05)
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#define TRC_HVM_IO_READ (TRC_HVM_HANDLER + 0x06)
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#define TRC_HVM_IO_WRITE (TRC_HVM_HANDLER + 0x07)
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#define TRC_HVM_CR_READ (TRC_HVM_HANDLER + 0x08)
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#define TRC_HVM_CR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08)
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#define TRC_HVM_CR_WRITE (TRC_HVM_HANDLER + 0x09)
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#define TRC_HVM_CR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09)
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#define TRC_HVM_DR_READ (TRC_HVM_HANDLER + 0x0A)
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#define TRC_HVM_DR_WRITE (TRC_HVM_HANDLER + 0x0B)
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#define TRC_HVM_MSR_READ (TRC_HVM_HANDLER + 0x0C)
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#define TRC_HVM_MSR_WRITE (TRC_HVM_HANDLER + 0x0D)
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#define TRC_HVM_CPUID (TRC_HVM_HANDLER + 0x0E)
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#define TRC_HVM_INTR (TRC_HVM_HANDLER + 0x0F)
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#define TRC_HVM_NMI (TRC_HVM_HANDLER + 0x10)
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#define TRC_HVM_SMI (TRC_HVM_HANDLER + 0x11)
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#define TRC_HVM_VMMCALL (TRC_HVM_HANDLER + 0x12)
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#define TRC_HVM_HLT (TRC_HVM_HANDLER + 0x13)
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#define TRC_HVM_INVLPG (TRC_HVM_HANDLER + 0x14)
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#define TRC_HVM_INVLPG64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14)
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#define TRC_HVM_MCE (TRC_HVM_HANDLER + 0x15)
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#define TRC_HVM_IOPORT_READ (TRC_HVM_HANDLER + 0x16)
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#define TRC_HVM_IOMEM_READ (TRC_HVM_HANDLER + 0x17)
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#define TRC_HVM_CLTS (TRC_HVM_HANDLER + 0x18)
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#define TRC_HVM_LMSW (TRC_HVM_HANDLER + 0x19)
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#define TRC_HVM_LMSW64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19)
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#define TRC_HVM_RDTSC (TRC_HVM_HANDLER + 0x1a)
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#define TRC_HVM_INTR_WINDOW (TRC_HVM_HANDLER + 0x20)
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#define TRC_HVM_NPF (TRC_HVM_HANDLER + 0x21)
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#define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22)
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#define TRC_HVM_TRAP (TRC_HVM_HANDLER + 0x23)
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#define TRC_HVM_TRAP_DEBUG (TRC_HVM_HANDLER + 0x24)
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#define TRC_HVM_VLAPIC (TRC_HVM_HANDLER + 0x25)
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#define TRC_HVM_IOPORT_WRITE (TRC_HVM_HANDLER + 0x216)
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#define TRC_HVM_IOMEM_WRITE (TRC_HVM_HANDLER + 0x217)
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/* Trace events for emulated devices */
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#define TRC_HVM_EMUL_HPET_START_TIMER (TRC_HVM_EMUL + 0x1)
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#define TRC_HVM_EMUL_PIT_START_TIMER (TRC_HVM_EMUL + 0x2)
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#define TRC_HVM_EMUL_RTC_START_TIMER (TRC_HVM_EMUL + 0x3)
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#define TRC_HVM_EMUL_LAPIC_START_TIMER (TRC_HVM_EMUL + 0x4)
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#define TRC_HVM_EMUL_HPET_STOP_TIMER (TRC_HVM_EMUL + 0x5)
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#define TRC_HVM_EMUL_PIT_STOP_TIMER (TRC_HVM_EMUL + 0x6)
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#define TRC_HVM_EMUL_RTC_STOP_TIMER (TRC_HVM_EMUL + 0x7)
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#define TRC_HVM_EMUL_LAPIC_STOP_TIMER (TRC_HVM_EMUL + 0x8)
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#define TRC_HVM_EMUL_PIT_TIMER_CB (TRC_HVM_EMUL + 0x9)
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#define TRC_HVM_EMUL_LAPIC_TIMER_CB (TRC_HVM_EMUL + 0xA)
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#define TRC_HVM_EMUL_PIC_INT_OUTPUT (TRC_HVM_EMUL + 0xB)
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#define TRC_HVM_EMUL_PIC_KICK (TRC_HVM_EMUL + 0xC)
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#define TRC_HVM_EMUL_PIC_INTACK (TRC_HVM_EMUL + 0xD)
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#define TRC_HVM_EMUL_PIC_POSEDGE (TRC_HVM_EMUL + 0xE)
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#define TRC_HVM_EMUL_PIC_NEGEDGE (TRC_HVM_EMUL + 0xF)
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#define TRC_HVM_EMUL_PIC_PEND_IRQ_CALL (TRC_HVM_EMUL + 0x10)
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#define TRC_HVM_EMUL_LAPIC_PIC_INTR (TRC_HVM_EMUL + 0x11)
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/* trace events for per class */
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#define TRC_PM_FREQ_CHANGE (TRC_HW_PM + 0x01)
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#define TRC_PM_IDLE_ENTRY (TRC_HW_PM + 0x02)
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#define TRC_PM_IDLE_EXIT (TRC_HW_PM + 0x03)
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/* Trace events for IRQs */
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#define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1)
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#define TRC_HW_IRQ_MOVE_CLEANUP (TRC_HW_IRQ + 0x2)
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#define TRC_HW_IRQ_BIND_VECTOR (TRC_HW_IRQ + 0x3)
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#define TRC_HW_IRQ_CLEAR_VECTOR (TRC_HW_IRQ + 0x4)
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#define TRC_HW_IRQ_MOVE_FINISH (TRC_HW_IRQ + 0x5)
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#define TRC_HW_IRQ_ASSIGN_VECTOR (TRC_HW_IRQ + 0x6)
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#define TRC_HW_IRQ_UNMAPPED_VECTOR (TRC_HW_IRQ + 0x7)
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#define TRC_HW_IRQ_HANDLED (TRC_HW_IRQ + 0x8)
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/*
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* Event Flags
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*
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* Some events (e.g, TRC_PV_TRAP and TRC_HVM_IOMEM_READ) have multiple
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* record formats. These event flags distinguish between the
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* different formats.
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*/
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#define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */
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/* This structure represents a single trace buffer record. */
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struct t_rec {
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uint32_t event:28;
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uint32_t extra_u32:3; /* # entries in trailing extra_u32[] array */
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uint32_t cycles_included:1; /* u.cycles or u.no_cycles? */
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union {
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struct {
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uint32_t cycles_lo, cycles_hi; /* cycle counter timestamp */
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uint32_t extra_u32[7]; /* event data items */
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} cycles;
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struct {
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uint32_t extra_u32[7]; /* event data items */
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} nocycles;
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} u;
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};
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/*
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* This structure contains the metadata for a single trace buffer. The head
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* field, indexes into an array of struct t_rec's.
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*/
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struct t_buf {
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/* Assume the data buffer size is X. X is generally not a power of 2.
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* CONS and PROD are incremented modulo (2*X):
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* 0 <= cons < 2*X
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* 0 <= prod < 2*X
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* This is done because addition modulo X breaks at 2^32 when X is not a
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* power of 2:
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* (((2^32 - 1) % X) + 1) % X != (2^32) % X
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*/
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uint32_t cons; /* Offset of next item to be consumed by control tools. */
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uint32_t prod; /* Offset of next item to be produced by Xen. */
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/* Records follow immediately after the meta-data header. */
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};
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/* Structure used to pass MFNs to the trace buffers back to trace consumers.
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* Offset is an offset into the mapped structure where the mfn list will be held.
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* MFNs will be at ((unsigned long *)(t_info))+(t_info->cpu_offset[cpu]).
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*/
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struct t_info {
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uint16_t tbuf_size; /* Size in pages of each trace buffer */
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uint16_t mfn_offset[]; /* Offset within t_info structure of the page list per cpu */
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/* MFN lists immediately after the header */
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};
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#endif /* __XEN_PUBLIC_TRACE_H__ */
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* tab-width: 4
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* indent-tabs-mode: nil
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* End:
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*/
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