1151 lines
27 KiB
C
1151 lines
27 KiB
C
#ifndef _IPXE_XHCI_H
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#define _IPXE_XHCI_H
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/** @file
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*
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* USB eXtensible Host Controller Interface (xHCI) driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <assert.h>
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#include <ipxe/pci.h>
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#include <ipxe/uaccess.h>
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#include <ipxe/usb.h>
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/** Minimum alignment required for data structures
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*
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* With the exception of the scratchpad buffer pages (which are
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* page-aligned), data structures used by xHCI generally require from
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* 16 to 64 byte alignment and must not cross an (xHCI) page boundary.
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* We simplify this requirement by aligning each structure on its own
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* size, with a minimum of a 64 byte alignment.
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*/
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#define XHCI_MIN_ALIGN 64
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/** Maximum transfer size */
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#define XHCI_MTU 65536
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/** xHCI PCI BAR */
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#define XHCI_BAR PCI_BASE_ADDRESS_0
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/** Capability register length */
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#define XHCI_CAP_CAPLENGTH 0x00
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/** Host controller interface version number */
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#define XHCI_CAP_HCIVERSION 0x02
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/** Structural parameters 1 */
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#define XHCI_CAP_HCSPARAMS1 0x04
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/** Number of device slots */
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#define XHCI_HCSPARAMS1_SLOTS(params) ( ( (params) >> 0 ) & 0xff )
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/** Number of interrupters */
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#define XHCI_HCSPARAMS1_INTRS(params) ( ( (params) >> 8 ) & 0x3ff )
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/** Number of ports */
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#define XHCI_HCSPARAMS1_PORTS(params) ( ( (params) >> 24 ) & 0xff )
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/** Structural parameters 2 */
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#define XHCI_CAP_HCSPARAMS2 0x08
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/** Number of page-sized scratchpad buffers */
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#define XHCI_HCSPARAMS2_SCRATCHPADS(params) \
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( ( ( (params) >> 16 ) & 0x3e0 ) | ( ( (params) >> 27 ) & 0x1f ) )
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/** Capability parameters */
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#define XHCI_CAP_HCCPARAMS1 0x10
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/** 64-bit addressing capability */
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#define XHCI_HCCPARAMS1_ADDR64(params) ( ( (params) >> 0 ) & 0x1 )
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/** Context size shift */
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#define XHCI_HCCPARAMS1_CSZ_SHIFT(params) ( 5 + ( ( (params) >> 2 ) & 0x1 ) )
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/** xHCI extended capabilities pointer */
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#define XHCI_HCCPARAMS1_XECP(params) ( ( ( (params) >> 16 ) & 0xffff ) << 2 )
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/** Doorbell offset */
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#define XHCI_CAP_DBOFF 0x14
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/** Runtime register space offset */
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#define XHCI_CAP_RTSOFF 0x18
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/** xHCI extended capability ID */
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#define XHCI_XECP_ID(xecp) ( ( (xecp) >> 0 ) & 0xff )
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/** Next xHCI extended capability pointer */
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#define XHCI_XECP_NEXT(xecp) ( ( ( (xecp) >> 8 ) & 0xff ) << 2 )
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/** USB legacy support extended capability */
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#define XHCI_XECP_ID_LEGACY 1
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/** USB legacy support BIOS owned semaphore */
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#define XHCI_USBLEGSUP_BIOS 0x02
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/** USB legacy support BIOS ownership flag */
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#define XHCI_USBLEGSUP_BIOS_OWNED 0x01
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/** USB legacy support OS owned semaphore */
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#define XHCI_USBLEGSUP_OS 0x03
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/** USB legacy support OS ownership flag */
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#define XHCI_USBLEGSUP_OS_OWNED 0x01
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/** USB legacy support control/status */
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#define XHCI_USBLEGSUP_CTLSTS 0x04
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/** Supported protocol extended capability */
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#define XHCI_XECP_ID_SUPPORTED 2
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/** Supported protocol revision */
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#define XHCI_SUPPORTED_REVISION 0x00
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/** Supported protocol minor revision */
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#define XHCI_SUPPORTED_REVISION_VER(revision) ( ( (revision) >> 16 ) & 0xffff )
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/** Supported protocol name */
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#define XHCI_SUPPORTED_NAME 0x04
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/** Supported protocol ports */
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#define XHCI_SUPPORTED_PORTS 0x08
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/** Supported protocol port offset */
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#define XHCI_SUPPORTED_PORTS_OFFSET(ports) ( ( (ports) >> 0 ) & 0xff )
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/** Supported protocol port count */
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#define XHCI_SUPPORTED_PORTS_COUNT(ports) ( ( (ports) >> 8 ) & 0xff )
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/** Supported protocol PSI count */
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#define XHCI_SUPPORTED_PORTS_PSIC(ports) ( ( (ports) >> 28 ) & 0x0f )
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/** Supported protocol slot */
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#define XHCI_SUPPORTED_SLOT 0x0c
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/** Supported protocol slot type */
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#define XHCI_SUPPORTED_SLOT_TYPE(slot) ( ( (slot) >> 0 ) & 0x1f )
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/** Supported protocol PSI */
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#define XHCI_SUPPORTED_PSI(index) ( 0x10 + ( (index) * 4 ) )
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/** Supported protocol PSI value */
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#define XHCI_SUPPORTED_PSI_VALUE(psi) ( ( (psi) >> 0 ) & 0x0f )
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/** Supported protocol PSI mantissa */
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#define XHCI_SUPPORTED_PSI_MANTISSA(psi) ( ( (psi) >> 16 ) & 0xffff )
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/** Supported protocol PSI exponent */
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#define XHCI_SUPPORTED_PSI_EXPONENT(psi) ( ( (psi) >> 4 ) & 0x03 )
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/** Default PSI values */
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enum xhci_default_psi_value {
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/** Full speed (12Mbps) */
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XHCI_SPEED_FULL = 1,
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/** Low speed (1.5Mbps) */
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XHCI_SPEED_LOW = 2,
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/** High speed (480Mbps) */
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XHCI_SPEED_HIGH = 3,
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/** Super speed */
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XHCI_SPEED_SUPER = 4,
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};
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/** USB command register */
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#define XHCI_OP_USBCMD 0x00
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/** Run/stop */
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#define XHCI_USBCMD_RUN 0x00000001UL
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/** Host controller reset */
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#define XHCI_USBCMD_HCRST 0x00000002UL
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/** USB status register */
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#define XHCI_OP_USBSTS 0x04
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/** Host controller halted */
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#define XHCI_USBSTS_HCH 0x00000001UL
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/** Page size register */
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#define XHCI_OP_PAGESIZE 0x08
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/** Page size */
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#define XHCI_PAGESIZE(pagesize) ( (pagesize) << 12 )
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/** Device notifcation control register */
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#define XHCI_OP_DNCTRL 0x14
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/** Command ring control register */
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#define XHCI_OP_CRCR 0x18
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/** Command ring cycle state */
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#define XHCI_CRCR_RCS 0x00000001UL
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/** Command abort */
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#define XHCI_CRCR_CA 0x00000004UL
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/** Command ring running */
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#define XHCI_CRCR_CRR 0x00000008UL
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/** Device context base address array pointer */
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#define XHCI_OP_DCBAAP 0x30
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/** Configure register */
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#define XHCI_OP_CONFIG 0x38
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/** Maximum device slots enabled */
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#define XHCI_CONFIG_MAX_SLOTS_EN(slots) ( (slots) << 0 )
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/** Maximum device slots enabled mask */
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#define XHCI_CONFIG_MAX_SLOTS_EN_MASK \
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XHCI_CONFIG_MAX_SLOTS_EN ( 0xff )
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/** Port status and control register */
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#define XHCI_OP_PORTSC(port) ( 0x400 - 0x10 + ( (port) << 4 ) )
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/** Current connect status */
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#define XHCI_PORTSC_CCS 0x00000001UL
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/** Port enabled */
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#define XHCI_PORTSC_PED 0x00000002UL
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/** Port reset */
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#define XHCI_PORTSC_PR 0x00000010UL
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/** Port link state */
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#define XHCI_PORTSC_PLS(pls) ( (pls) << 5 )
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/** Disabled port link state */
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#define XHCI_PORTSC_PLS_DISABLED XHCI_PORTSC_PLS ( 4 )
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/** RxDetect port link state */
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#define XHCI_PORTSC_PLS_RXDETECT XHCI_PORTSC_PLS ( 5 )
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/** Port link state mask */
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#define XHCI_PORTSC_PLS_MASK XHCI_PORTSC_PLS ( 0xf )
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/** Port power */
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#define XHCI_PORTSC_PP 0x00000200UL
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/** Time to delay after enabling power to a port */
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#define XHCI_PORT_POWER_DELAY_MS 20
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/** Port speed ID value */
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#define XHCI_PORTSC_PSIV(portsc) ( ( (portsc) >> 10 ) & 0xf )
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/** Port indicator control */
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#define XHCI_PORTSC_PIC(indicators) ( (indicators) << 14 )
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/** Port indicator control mask */
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#define XHCI_PORTSC_PIC_MASK XHCI_PORTSC_PIC ( 3 )
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/** Port link state write strobe */
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#define XHCI_PORTSC_LWS 0x00010000UL
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/** Time to delay after writing the port link state */
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#define XHCI_LINK_STATE_DELAY_MS 20
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/** Connect status change */
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#define XHCI_PORTSC_CSC 0x00020000UL
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/** Port enabled/disabled change */
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#define XHCI_PORTSC_PEC 0x00040000UL
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/** Warm port reset change */
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#define XHCI_PORTSC_WRC 0x00080000UL
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/** Over-current change */
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#define XHCI_PORTSC_OCC 0x00100000UL
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/** Port reset change */
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#define XHCI_PORTSC_PRC 0x00200000UL
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/** Port link state change */
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#define XHCI_PORTSC_PLC 0x00400000UL
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/** Port config error change */
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#define XHCI_PORTSC_CEC 0x00800000UL
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/** Port status change mask */
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#define XHCI_PORTSC_CHANGE \
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( XHCI_PORTSC_CSC | XHCI_PORTSC_PEC | XHCI_PORTSC_WRC | \
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XHCI_PORTSC_OCC | XHCI_PORTSC_PRC | XHCI_PORTSC_PLC | \
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XHCI_PORTSC_CEC )
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/** Port status and control bits which should be preserved
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*
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* The port status and control register is a horrendous mix of
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* differing semantics. Some bits are written to only when a separate
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* write strobe bit is set. Some bits should be preserved when
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* modifying other bits. Some bits will be cleared if written back as
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* a one. Most excitingly, the "port enabled" bit has the semantics
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* that 1=enabled, 0=disabled, yet writing a 1 will disable the port.
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*/
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#define XHCI_PORTSC_PRESERVE ( XHCI_PORTSC_PP | XHCI_PORTSC_PIC_MASK )
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/** Port power management status and control register */
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#define XHCI_OP_PORTPMSC(port) ( 0x404 - 0x10 + ( (port) << 4 ) )
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/** Port link info register */
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#define XHCI_OP_PORTLI(port) ( 0x408 - 0x10 + ( (port) << 4 ) )
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/** Port hardware link power management control register */
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#define XHCI_OP_PORTHLPMC(port) ( 0x40c - 0x10 + ( (port) << 4 ) )
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/** Event ring segment table size register */
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#define XHCI_RUN_ERSTSZ(intr) ( 0x28 + ( (intr) << 5 ) )
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/** Event ring segment table base address register */
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#define XHCI_RUN_ERSTBA(intr) ( 0x30 + ( (intr) << 5 ) )
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/** Event ring dequeue pointer register */
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#define XHCI_RUN_ERDP(intr) ( 0x38 + ( (intr) << 5 ) )
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/** A transfer request block template */
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struct xhci_trb_template {
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/** Parameter */
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uint64_t parameter;
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/** Status */
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uint32_t status;
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/** Control */
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uint32_t control;
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};
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/** A transfer request block */
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struct xhci_trb_common {
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/** Reserved */
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uint64_t reserved_a;
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/** Reserved */
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uint32_t reserved_b;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Reserved */
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uint16_t reserved_c;
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} __attribute__ (( packed ));
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/** Transfer request block cycle bit flag */
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#define XHCI_TRB_C 0x01
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/** Transfer request block toggle cycle bit flag */
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#define XHCI_TRB_TC 0x02
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/** Transfer request block chain flag */
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#define XHCI_TRB_CH 0x10
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/** Transfer request block interrupt on completion flag */
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#define XHCI_TRB_IOC 0x20
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/** Transfer request block immediate data flag */
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#define XHCI_TRB_IDT 0x40
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/** Transfer request block type */
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#define XHCI_TRB_TYPE(type) ( (type) << 2 )
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/** Transfer request block type mask */
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#define XHCI_TRB_TYPE_MASK XHCI_TRB_TYPE ( 0x3f )
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/** A normal transfer request block */
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struct xhci_trb_normal {
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/** Data buffer */
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uint64_t data;
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/** Length */
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uint32_t len;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Reserved */
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uint16_t reserved;
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} __attribute__ (( packed ));
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/** A normal transfer request block */
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#define XHCI_TRB_NORMAL XHCI_TRB_TYPE ( 1 )
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/** Construct TD size field */
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#define XHCI_TD_SIZE(remaining) \
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( ( ( (remaining) <= 0xf ) ? remaining : 0xf ) << 17 )
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/** A setup stage transfer request block */
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struct xhci_trb_setup {
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/** Setup packet */
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struct usb_setup_packet packet;
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/** Length */
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uint32_t len;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Transfer direction */
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uint8_t direction;
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/** Reserved */
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uint8_t reserved;
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} __attribute__ (( packed ));
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/** A setup stage transfer request block */
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#define XHCI_TRB_SETUP XHCI_TRB_TYPE ( 2 )
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/** Setup stage input data direction */
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#define XHCI_SETUP_IN 3
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/** Setup stage output data direction */
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#define XHCI_SETUP_OUT 2
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/** A data stage transfer request block */
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struct xhci_trb_data {
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/** Data buffer */
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uint64_t data;
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/** Length */
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uint32_t len;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Transfer direction */
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uint8_t direction;
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/** Reserved */
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uint8_t reserved;
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} __attribute__ (( packed ));
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/** A data stage transfer request block */
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#define XHCI_TRB_DATA XHCI_TRB_TYPE ( 3 )
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/** Input data direction */
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#define XHCI_DATA_IN 0x01
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/** Output data direction */
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#define XHCI_DATA_OUT 0x00
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/** A status stage transfer request block */
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struct xhci_trb_status {
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/** Reserved */
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uint64_t reserved_a;
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/** Reserved */
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uint32_t reserved_b;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Direction */
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uint8_t direction;
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/** Reserved */
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uint8_t reserved_c;
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} __attribute__ (( packed ));
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/** A status stage transfer request block */
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#define XHCI_TRB_STATUS XHCI_TRB_TYPE ( 4 )
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/** Input status direction */
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#define XHCI_STATUS_IN 0x01
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/** Output status direction */
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#define XHCI_STATUS_OUT 0x00
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/** A link transfer request block */
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struct xhci_trb_link {
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/** Next ring segment */
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uint64_t next;
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/** Reserved */
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uint32_t reserved_a;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Reserved */
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uint16_t reserved_c;
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} __attribute__ (( packed ));
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/** A link transfer request block */
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#define XHCI_TRB_LINK XHCI_TRB_TYPE ( 6 )
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/** A no-op transfer request block */
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#define XHCI_TRB_NOP XHCI_TRB_TYPE ( 8 )
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/** An enable slot transfer request block */
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struct xhci_trb_enable_slot {
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/** Reserved */
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uint64_t reserved_a;
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/** Reserved */
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uint32_t reserved_b;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Slot type */
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uint8_t slot;
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/** Reserved */
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uint8_t reserved_c;
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} __attribute__ (( packed ));
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/** An enable slot transfer request block */
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#define XHCI_TRB_ENABLE_SLOT XHCI_TRB_TYPE ( 9 )
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/** A disable slot transfer request block */
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struct xhci_trb_disable_slot {
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/** Reserved */
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uint64_t reserved_a;
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/** Reserved */
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uint32_t reserved_b;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Reserved */
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uint8_t reserved_c;
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/** Slot ID */
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uint8_t slot;
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} __attribute__ (( packed ));
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/** A disable slot transfer request block */
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#define XHCI_TRB_DISABLE_SLOT XHCI_TRB_TYPE ( 10 )
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/** A context transfer request block */
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struct xhci_trb_context {
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/** Input context */
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uint64_t input;
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/** Reserved */
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uint32_t reserved_a;
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/** Flags */
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uint8_t flags;
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/** Type */
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uint8_t type;
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/** Reserved */
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uint8_t reserved_b;
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/** Slot ID */
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uint8_t slot;
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} __attribute__ (( packed ));
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/** An address device transfer request block */
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#define XHCI_TRB_ADDRESS_DEVICE XHCI_TRB_TYPE ( 11 )
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/** A configure endpoint transfer request block */
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#define XHCI_TRB_CONFIGURE_ENDPOINT XHCI_TRB_TYPE ( 12 )
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|
/** An evaluate context transfer request block */
|
|
#define XHCI_TRB_EVALUATE_CONTEXT XHCI_TRB_TYPE ( 13 )
|
|
|
|
/** A reset endpoint transfer request block */
|
|
struct xhci_trb_reset_endpoint {
|
|
/** Reserved */
|
|
uint64_t reserved_a;
|
|
/** Reserved */
|
|
uint32_t reserved_b;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Type */
|
|
uint8_t type;
|
|
/** Endpoint ID */
|
|
uint8_t endpoint;
|
|
/** Slot ID */
|
|
uint8_t slot;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A reset endpoint transfer request block */
|
|
#define XHCI_TRB_RESET_ENDPOINT XHCI_TRB_TYPE ( 14 )
|
|
|
|
/** A stop endpoint transfer request block */
|
|
struct xhci_trb_stop_endpoint {
|
|
/** Reserved */
|
|
uint64_t reserved_a;
|
|
/** Reserved */
|
|
uint32_t reserved_b;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Type */
|
|
uint8_t type;
|
|
/** Endpoint ID */
|
|
uint8_t endpoint;
|
|
/** Slot ID */
|
|
uint8_t slot;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A stop endpoint transfer request block */
|
|
#define XHCI_TRB_STOP_ENDPOINT XHCI_TRB_TYPE ( 15 )
|
|
|
|
/** A set transfer ring dequeue pointer transfer request block */
|
|
struct xhci_trb_set_tr_dequeue_pointer {
|
|
/** Dequeue pointer */
|
|
uint64_t dequeue;
|
|
/** Reserved */
|
|
uint32_t reserved;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Type */
|
|
uint8_t type;
|
|
/** Endpoint ID */
|
|
uint8_t endpoint;
|
|
/** Slot ID */
|
|
uint8_t slot;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A set transfer ring dequeue pointer transfer request block */
|
|
#define XHCI_TRB_SET_TR_DEQUEUE_POINTER XHCI_TRB_TYPE ( 16 )
|
|
|
|
/** A no-op command transfer request block */
|
|
#define XHCI_TRB_NOP_CMD XHCI_TRB_TYPE ( 23 )
|
|
|
|
/** A transfer event transfer request block */
|
|
struct xhci_trb_transfer {
|
|
/** Transfer TRB pointer */
|
|
uint64_t transfer;
|
|
/** Residual transfer length */
|
|
uint16_t residual;
|
|
/** Reserved */
|
|
uint8_t reserved;
|
|
/** Completion code */
|
|
uint8_t code;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Type */
|
|
uint8_t type;
|
|
/** Endpoint ID */
|
|
uint8_t endpoint;
|
|
/** Slot ID */
|
|
uint8_t slot;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A transfer event transfer request block */
|
|
#define XHCI_TRB_TRANSFER XHCI_TRB_TYPE ( 32 )
|
|
|
|
/** A command completion event transfer request block */
|
|
struct xhci_trb_complete {
|
|
/** Command TRB pointer */
|
|
uint64_t command;
|
|
/** Parameter */
|
|
uint8_t parameter[3];
|
|
/** Completion code */
|
|
uint8_t code;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Type */
|
|
uint8_t type;
|
|
/** Virtual function ID */
|
|
uint8_t vf;
|
|
/** Slot ID */
|
|
uint8_t slot;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A command completion event transfer request block */
|
|
#define XHCI_TRB_COMPLETE XHCI_TRB_TYPE ( 33 )
|
|
|
|
/** xHCI completion codes */
|
|
enum xhci_completion_code {
|
|
/** Success */
|
|
XHCI_CMPLT_SUCCESS = 1,
|
|
/** Short packet */
|
|
XHCI_CMPLT_SHORT = 13,
|
|
/** Command ring stopped */
|
|
XHCI_CMPLT_CMD_STOPPED = 24,
|
|
};
|
|
|
|
/** A port status change transfer request block */
|
|
struct xhci_trb_port_status {
|
|
/** Reserved */
|
|
uint8_t reserved_a[3];
|
|
/** Port ID */
|
|
uint8_t port;
|
|
/** Reserved */
|
|
uint8_t reserved_b[7];
|
|
/** Completion code */
|
|
uint8_t code;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Type */
|
|
uint8_t type;
|
|
/** Reserved */
|
|
uint16_t reserved_c;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A port status change transfer request block */
|
|
#define XHCI_TRB_PORT_STATUS XHCI_TRB_TYPE ( 34 )
|
|
|
|
/** A port status change transfer request block */
|
|
struct xhci_trb_host_controller {
|
|
/** Reserved */
|
|
uint64_t reserved_a;
|
|
/** Reserved */
|
|
uint8_t reserved_b[3];
|
|
/** Completion code */
|
|
uint8_t code;
|
|
/** Flags */
|
|
uint8_t flags;
|
|
/** Type */
|
|
uint8_t type;
|
|
/** Reserved */
|
|
uint16_t reserved_c;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A port status change transfer request block */
|
|
#define XHCI_TRB_HOST_CONTROLLER XHCI_TRB_TYPE ( 37 )
|
|
|
|
/** A transfer request block */
|
|
union xhci_trb {
|
|
/** Template */
|
|
struct xhci_trb_template template;
|
|
/** Common fields */
|
|
struct xhci_trb_common common;
|
|
/** Normal TRB */
|
|
struct xhci_trb_normal normal;
|
|
/** Setup stage TRB */
|
|
struct xhci_trb_setup setup;
|
|
/** Data stage TRB */
|
|
struct xhci_trb_data data;
|
|
/** Status stage TRB */
|
|
struct xhci_trb_status status;
|
|
/** Link TRB */
|
|
struct xhci_trb_link link;
|
|
/** Enable slot TRB */
|
|
struct xhci_trb_enable_slot enable;
|
|
/** Disable slot TRB */
|
|
struct xhci_trb_disable_slot disable;
|
|
/** Input context TRB */
|
|
struct xhci_trb_context context;
|
|
/** Reset endpoint TRB */
|
|
struct xhci_trb_reset_endpoint reset;
|
|
/** Stop endpoint TRB */
|
|
struct xhci_trb_stop_endpoint stop;
|
|
/** Set transfer ring dequeue pointer TRB */
|
|
struct xhci_trb_set_tr_dequeue_pointer dequeue;
|
|
/** Transfer event */
|
|
struct xhci_trb_transfer transfer;
|
|
/** Command completion event */
|
|
struct xhci_trb_complete complete;
|
|
/** Port status changed event */
|
|
struct xhci_trb_port_status port;
|
|
/** Host controller event */
|
|
struct xhci_trb_host_controller host;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** An input control context */
|
|
struct xhci_control_context {
|
|
/** Drop context flags */
|
|
uint32_t drop;
|
|
/** Add context flags */
|
|
uint32_t add;
|
|
/** Reserved */
|
|
uint32_t reserved_a[5];
|
|
/** Configuration value */
|
|
uint8_t config;
|
|
/** Interface number */
|
|
uint8_t intf;
|
|
/** Alternate setting */
|
|
uint8_t alt;
|
|
/** Reserved */
|
|
uint8_t reserved_b;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A slot context */
|
|
struct xhci_slot_context {
|
|
/** Device info */
|
|
uint32_t info;
|
|
/** Maximum exit latency */
|
|
uint16_t latency;
|
|
/** Root hub port number */
|
|
uint8_t port;
|
|
/** Number of downstream ports */
|
|
uint8_t ports;
|
|
/** TT hub slot ID */
|
|
uint8_t tt_id;
|
|
/** TT port number */
|
|
uint8_t tt_port;
|
|
/** Interrupter target */
|
|
uint16_t intr;
|
|
/** USB address */
|
|
uint8_t address;
|
|
/** Reserved */
|
|
uint16_t reserved_a;
|
|
/** Slot state */
|
|
uint8_t state;
|
|
/** Reserved */
|
|
uint32_t reserved_b[4];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Construct slot context device info */
|
|
#define XHCI_SLOT_INFO( entries, hub, speed, route ) \
|
|
( ( (entries) << 27 ) | ( (hub) << 26 ) | ( (speed) << 20 ) | (route) )
|
|
|
|
/** An endpoint context */
|
|
struct xhci_endpoint_context {
|
|
/** Endpoint state */
|
|
uint8_t state;
|
|
/** Stream configuration */
|
|
uint8_t stream;
|
|
/** Polling interval */
|
|
uint8_t interval;
|
|
/** Max ESIT payload high */
|
|
uint8_t esit_high;
|
|
/** Endpoint type */
|
|
uint8_t type;
|
|
/** Maximum burst size */
|
|
uint8_t burst;
|
|
/** Maximum packet size */
|
|
uint16_t mtu;
|
|
/** Transfer ring dequeue pointer */
|
|
uint64_t dequeue;
|
|
/** Average TRB length */
|
|
uint16_t trb_len;
|
|
/** Max ESIT payload low */
|
|
uint16_t esit_low;
|
|
/** Reserved */
|
|
uint32_t reserved[3];
|
|
} __attribute__ (( packed ));
|
|
|
|
/** Endpoint states */
|
|
enum xhci_endpoint_state {
|
|
/** Endpoint is disabled */
|
|
XHCI_ENDPOINT_DISABLED = 0,
|
|
/** Endpoint is running */
|
|
XHCI_ENDPOINT_RUNNING = 1,
|
|
/** Endpoint is halted due to a USB Halt condition */
|
|
XHCI_ENDPOINT_HALTED = 2,
|
|
/** Endpoint is stopped */
|
|
XHCI_ENDPOINT_STOPPED = 3,
|
|
/** Endpoint is halted due to a TRB error */
|
|
XHCI_ENDPOINT_ERROR = 4,
|
|
};
|
|
|
|
/** Endpoint state mask */
|
|
#define XHCI_ENDPOINT_STATE_MASK 0x07
|
|
|
|
/** Endpoint type */
|
|
#define XHCI_EP_TYPE(type) ( (type) << 3 )
|
|
|
|
/** Control endpoint type */
|
|
#define XHCI_EP_TYPE_CONTROL XHCI_EP_TYPE ( 4 )
|
|
|
|
/** Input endpoint type */
|
|
#define XHCI_EP_TYPE_IN XHCI_EP_TYPE ( 4 )
|
|
|
|
/** Periodic endpoint type */
|
|
#define XHCI_EP_TYPE_PERIODIC XHCI_EP_TYPE ( 1 )
|
|
|
|
/** Endpoint dequeue cycle state */
|
|
#define XHCI_EP_DCS 0x00000001UL
|
|
|
|
/** Control endpoint average TRB length */
|
|
#define XHCI_EP0_TRB_LEN 8
|
|
|
|
/** An event ring segment */
|
|
struct xhci_event_ring_segment {
|
|
/** Base address */
|
|
uint64_t base;
|
|
/** Number of TRBs */
|
|
uint32_t count;
|
|
/** Reserved */
|
|
uint32_t reserved;
|
|
} __attribute__ (( packed ));
|
|
|
|
/** A transfer request block command/transfer ring */
|
|
struct xhci_trb_ring {
|
|
/** Producer counter */
|
|
unsigned int prod;
|
|
/** Consumer counter */
|
|
unsigned int cons;
|
|
/** Ring size (log2) */
|
|
unsigned int shift;
|
|
/** Ring counter mask */
|
|
unsigned int mask;
|
|
|
|
/** I/O buffers */
|
|
struct io_buffer **iobuf;
|
|
|
|
/** Transfer request blocks */
|
|
union xhci_trb *trb;
|
|
/** Length of transfer request blocks */
|
|
size_t len;
|
|
/** Link TRB (if applicable) */
|
|
struct xhci_trb_link *link;
|
|
|
|
/** Doorbell register */
|
|
void *db;
|
|
/** Doorbell register value */
|
|
uint32_t dbval;
|
|
};
|
|
|
|
/** An event ring */
|
|
struct xhci_event_ring {
|
|
/** Consumer counter */
|
|
unsigned int cons;
|
|
/** Event ring segment table */
|
|
struct xhci_event_ring_segment *segment;
|
|
/** Transfer request blocks */
|
|
union xhci_trb *trb;
|
|
};
|
|
|
|
/**
|
|
* Calculate doorbell register value
|
|
*
|
|
* @v target Doorbell target
|
|
* @v stream Doorbell stream ID
|
|
* @ret dbval Doorbell register value
|
|
*/
|
|
#define XHCI_DBVAL( target, stream ) ( (target) | ( (stream) << 16 ) )
|
|
|
|
/**
|
|
* Calculate space used in TRB ring
|
|
*
|
|
* @v ring TRB ring
|
|
* @ret fill Number of entries used
|
|
*/
|
|
static inline __attribute__ (( always_inline )) unsigned int
|
|
xhci_ring_fill ( struct xhci_trb_ring *ring ) {
|
|
|
|
return ( ring->prod - ring->cons );
|
|
}
|
|
|
|
/**
|
|
* Calculate space remaining in TRB ring
|
|
*
|
|
* @v ring TRB ring
|
|
* @ret remaining Number of entries remaining
|
|
*
|
|
* xHCI does not allow us to completely fill a ring; there must be at
|
|
* least one free entry (excluding the Link TRB).
|
|
*/
|
|
static inline __attribute__ (( always_inline )) unsigned int
|
|
xhci_ring_remaining ( struct xhci_trb_ring *ring ) {
|
|
unsigned int fill = xhci_ring_fill ( ring );
|
|
|
|
/* We choose to utilise rings with ( 2^n + 1 ) entries, with
|
|
* the final entry being a Link TRB. The maximum fill level
|
|
* is therefore
|
|
*
|
|
* ( ( 2^n + 1 ) - 1 (Link TRB) - 1 (one slot always empty)
|
|
* == ( 2^n - 1 )
|
|
*
|
|
* which is therefore equal to the ring mask.
|
|
*/
|
|
assert ( fill <= ring->mask );
|
|
return ( ring->mask - fill );
|
|
}
|
|
|
|
/**
|
|
* Calculate physical address of most recently consumed TRB
|
|
*
|
|
* @v ring TRB ring
|
|
* @ret trb TRB physical address
|
|
*/
|
|
static inline __attribute__ (( always_inline )) physaddr_t
|
|
xhci_ring_consumed ( struct xhci_trb_ring *ring ) {
|
|
unsigned int index = ( ( ring->cons - 1 ) & ring->mask );
|
|
|
|
return virt_to_phys ( &ring->trb[index] );
|
|
}
|
|
|
|
/** Slot context index */
|
|
#define XHCI_CTX_SLOT 0
|
|
|
|
/** Calculate context index from USB endpoint address */
|
|
#define XHCI_CTX(address) \
|
|
( (address) ? ( ( ( (address) & 0x0f ) << 1 ) | \
|
|
( ( (address) & 0x80 ) >> 7 ) ) : 1 )
|
|
|
|
/** Endpoint zero context index */
|
|
#define XHCI_CTX_EP0 XHCI_CTX ( 0x00 )
|
|
|
|
/** End of contexts */
|
|
#define XHCI_CTX_END 32
|
|
|
|
/** Device context index */
|
|
#define XHCI_DCI(ctx) ( (ctx) + 0 )
|
|
|
|
/** Input context index */
|
|
#define XHCI_ICI(ctx) ( (ctx) + 1 )
|
|
|
|
/** Number of TRBs (excluding Link TRB) in the command ring
|
|
*
|
|
* This is a policy decision.
|
|
*/
|
|
#define XHCI_CMD_TRBS_LOG2 2
|
|
|
|
/** Number of TRBs in the event ring
|
|
*
|
|
* This is a policy decision.
|
|
*/
|
|
#define XHCI_EVENT_TRBS_LOG2 6
|
|
|
|
/** Number of TRBs in a transfer ring
|
|
*
|
|
* This is a policy decision.
|
|
*/
|
|
#define XHCI_TRANSFER_TRBS_LOG2 6
|
|
|
|
/** Maximum time to wait for BIOS to release ownership
|
|
*
|
|
* This is a policy decision.
|
|
*/
|
|
#define XHCI_USBLEGSUP_MAX_WAIT_MS 100
|
|
|
|
/** Maximum time to wait for host controller to stop
|
|
*
|
|
* This is a policy decision.
|
|
*/
|
|
#define XHCI_STOP_MAX_WAIT_MS 100
|
|
|
|
/** Maximum time to wait for reset to complete
|
|
*
|
|
* This is a policy decision.
|
|
*/
|
|
#define XHCI_RESET_MAX_WAIT_MS 500
|
|
|
|
/** Maximum time to wait for a command to complete
|
|
*
|
|
* The "address device" command involves waiting for a response to a
|
|
* USB control transaction, and so we must wait for up to the 5000ms
|
|
* that USB allows for devices to respond to control transactions.
|
|
*/
|
|
#define XHCI_COMMAND_MAX_WAIT_MS USB_CONTROL_MAX_WAIT_MS
|
|
|
|
/** Time to delay after aborting a command
|
|
*
|
|
* This is a policy decision
|
|
*/
|
|
#define XHCI_COMMAND_ABORT_DELAY_MS 500
|
|
|
|
/** Maximum time to wait for a port reset to complete
|
|
*
|
|
* This is a policy decision.
|
|
*/
|
|
#define XHCI_PORT_RESET_MAX_WAIT_MS 500
|
|
|
|
/** Intel PCH quirk */
|
|
struct xhci_pch {
|
|
/** USB2 port routing register original value */
|
|
uint32_t xusb2pr;
|
|
/** USB3 port SuperSpeed enable register original value */
|
|
uint32_t usb3pssen;
|
|
};
|
|
|
|
/** Intel PCH quirk flag */
|
|
#define XHCI_PCH 0x0001
|
|
|
|
/** Intel PCH USB2 port routing register */
|
|
#define XHCI_PCH_XUSB2PR 0xd0
|
|
|
|
/** Intel PCH USB2 port routing mask register */
|
|
#define XHCI_PCH_XUSB2PRM 0xd4
|
|
|
|
/** Intel PCH SuperSpeed enable register */
|
|
#define XHCI_PCH_USB3PSSEN 0xd8
|
|
|
|
/** Intel PCH USB3 port routing mask register */
|
|
#define XHCI_PCH_USB3PRM 0xdc
|
|
|
|
/** Invalid protocol speed ID values quirk */
|
|
#define XHCI_BAD_PSIV 0x0002
|
|
|
|
/** An xHCI device */
|
|
struct xhci_device {
|
|
/** Registers */
|
|
void *regs;
|
|
/** Name */
|
|
const char *name;
|
|
/** Quirks */
|
|
unsigned int quirks;
|
|
|
|
/** Capability registers */
|
|
void *cap;
|
|
/** Operational registers */
|
|
void *op;
|
|
/** Runtime registers */
|
|
void *run;
|
|
/** Doorbell registers */
|
|
void *db;
|
|
|
|
/** Number of device slots */
|
|
unsigned int slots;
|
|
/** Number of interrupters */
|
|
unsigned int intrs;
|
|
/** Number of ports */
|
|
unsigned int ports;
|
|
|
|
/** Number of page-sized scratchpad buffers */
|
|
unsigned int scratchpads;
|
|
|
|
/** 64-bit addressing capability */
|
|
int addr64;
|
|
/** Context size shift */
|
|
unsigned int csz_shift;
|
|
/** xHCI extended capabilities offset */
|
|
unsigned int xecp;
|
|
|
|
/** Page size */
|
|
size_t pagesize;
|
|
|
|
/** USB legacy support capability (if present and enabled) */
|
|
unsigned int legacy;
|
|
|
|
/** Device context base address array */
|
|
uint64_t *dcbaa;
|
|
|
|
/** Scratchpad buffer area */
|
|
userptr_t scratchpad;
|
|
/** Scratchpad buffer array */
|
|
uint64_t *scratchpad_array;
|
|
|
|
/** Command ring */
|
|
struct xhci_trb_ring command;
|
|
/** Event ring */
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struct xhci_event_ring event;
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/** Current command (if any) */
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union xhci_trb *pending;
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|
|
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/** Device slots, indexed by slot ID */
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struct xhci_slot **slot;
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|
|
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/** USB bus */
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struct usb_bus *bus;
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|
|
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/** Intel PCH quirk */
|
|
struct xhci_pch pch;
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|
};
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|
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/** An xHCI device slot */
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struct xhci_slot {
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/** xHCI device */
|
|
struct xhci_device *xhci;
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|
/** USB device */
|
|
struct usb_device *usb;
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|
/** Slot ID */
|
|
unsigned int id;
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|
/** Slot context */
|
|
struct xhci_slot_context *context;
|
|
/** Route string */
|
|
unsigned int route;
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|
/** Root hub port number */
|
|
unsigned int port;
|
|
/** Protocol speed ID */
|
|
unsigned int psiv;
|
|
/** Number of ports (if this device is a hub) */
|
|
unsigned int ports;
|
|
/** Transaction translator slot ID */
|
|
unsigned int tt_id;
|
|
/** Transaction translator port */
|
|
unsigned int tt_port;
|
|
/** Endpoints, indexed by context ID */
|
|
struct xhci_endpoint *endpoint[XHCI_CTX_END];
|
|
};
|
|
|
|
/** An xHCI endpoint */
|
|
struct xhci_endpoint {
|
|
/** xHCI device */
|
|
struct xhci_device *xhci;
|
|
/** xHCI slot */
|
|
struct xhci_slot *slot;
|
|
/** USB endpoint */
|
|
struct usb_endpoint *ep;
|
|
/** Context index */
|
|
unsigned int ctx;
|
|
/** Endpoint type */
|
|
unsigned int type;
|
|
/** Endpoint interval */
|
|
unsigned int interval;
|
|
/** Endpoint context */
|
|
struct xhci_endpoint_context *context;
|
|
/** Transfer ring */
|
|
struct xhci_trb_ring ring;
|
|
};
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|
|
|
#endif /* _IPXE_XHCI_H */
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