506 lines
12 KiB
C
506 lines
12 KiB
C
#ifndef _VMXNET3_H
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#define _VMXNET3_H
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/*
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* Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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/**
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* @file
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*
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* VMware vmxnet3 virtual NIC driver
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*
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*/
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#include <ipxe/pci.h>
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/** Maximum number of TX queues */
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#define VMXNET3_MAX_TX_QUEUES 8
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/** Maximum number of RX queues */
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#define VMXNET3_MAX_RX_QUEUES 16
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/** Maximum number of interrupts */
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#define VMXNET3_MAX_INTRS 25
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/** Maximum packet size */
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#define VMXNET3_MAX_PACKET_LEN 0x4000
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/** "PT" PCI BAR address */
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#define VMXNET3_PT_BAR PCI_BASE_ADDRESS_0
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/** "PT" PCI BAR size */
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#define VMXNET3_PT_LEN 0x1000
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/** Interrupt Mask Register */
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#define VMXNET3_PT_IMR 0x0
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/** Transmit producer index */
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#define VMXNET3_PT_TXPROD 0x600
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/** Rx producer index for ring 1 */
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#define VMXNET3_PT_RXPROD 0x800
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/** Rx producer index for ring 2 */
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#define VMXNET3_PT_RXPROD2 0xa00
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/** "VD" PCI BAR address */
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#define VMXNET3_VD_BAR PCI_BASE_ADDRESS_1
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/** "VD" PCI BAR size */
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#define VMXNET3_VD_LEN 0x1000
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/** vmxnet3 Revision Report Selection */
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#define VMXNET3_VD_VRRS 0x0
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/** UPT Version Report Selection */
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#define VMXNET3_VD_UVRS 0x8
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/** Driver Shared Address Low */
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#define VMXNET3_VD_DSAL 0x10
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/** Driver Shared Address High */
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#define VMXNET3_VD_DSAH 0x18
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/** Command */
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#define VMXNET3_VD_CMD 0x20
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/** MAC Address Low */
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#define VMXNET3_VD_MACL 0x28
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/** MAC Address High */
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#define VMXNET3_VD_MACH 0x30
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/** Interrupt Cause Register */
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#define VMXNET3_VD_ICR 0x38
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/** Event Cause Register */
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#define VMXNET3_VD_ECR 0x40
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/** Commands */
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enum vmxnet3_command {
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VMXNET3_CMD_FIRST_SET = 0xcafe0000,
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VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
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VMXNET3_CMD_QUIESCE_DEV,
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VMXNET3_CMD_RESET_DEV,
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VMXNET3_CMD_UPDATE_RX_MODE,
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VMXNET3_CMD_UPDATE_MAC_FILTERS,
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VMXNET3_CMD_UPDATE_VLAN_FILTERS,
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VMXNET3_CMD_UPDATE_RSSIDT,
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VMXNET3_CMD_UPDATE_IML,
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VMXNET3_CMD_UPDATE_PMCFG,
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VMXNET3_CMD_UPDATE_FEATURE,
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VMXNET3_CMD_LOAD_PLUGIN,
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VMXNET3_CMD_FIRST_GET = 0xf00d0000,
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VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
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VMXNET3_CMD_GET_STATS,
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VMXNET3_CMD_GET_LINK,
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VMXNET3_CMD_GET_PERM_MAC_LO,
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VMXNET3_CMD_GET_PERM_MAC_HI,
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VMXNET3_CMD_GET_DID_LO,
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VMXNET3_CMD_GET_DID_HI,
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VMXNET3_CMD_GET_DEV_EXTRA_INFO,
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VMXNET3_CMD_GET_CONF_INTR
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};
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/** Events */
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enum vmxnet3_event {
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VMXNET3_ECR_RQERR = 0x00000001,
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VMXNET3_ECR_TQERR = 0x00000002,
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VMXNET3_ECR_LINK = 0x00000004,
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VMXNET3_ECR_DIC = 0x00000008,
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VMXNET3_ECR_DEBUG = 0x00000010,
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};
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/** Miscellaneous configuration descriptor */
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struct vmxnet3_misc_config {
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/** Driver version */
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uint32_t version;
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/** Guest information */
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uint32_t guest_info;
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/** Version supported */
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uint32_t version_support;
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/** UPT version supported */
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uint32_t upt_version_support;
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/** UPT features supported */
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uint64_t upt_features;
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/** Driver-private data address */
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uint64_t driver_data_address;
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/** Queue descriptors data address */
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uint64_t queue_desc_address;
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/** Driver-private data length */
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uint32_t driver_data_len;
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/** Queue descriptors data length */
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uint32_t queue_desc_len;
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/** Maximum transmission unit */
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uint32_t mtu;
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/** Maximum number of RX scatter-gather */
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uint16_t max_num_rx_sg;
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/** Number of TX queues */
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uint8_t num_tx_queues;
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/** Number of RX queues */
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uint8_t num_rx_queues;
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/** Reserved */
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uint32_t reserved0[4];
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} __attribute__ (( packed ));
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/** Driver version magic */
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#define VMXNET3_VERSION_MAGIC 0x69505845
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/** Interrupt configuration */
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struct vmxnet3_interrupt_config {
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uint8_t mask_mode;
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uint8_t num_intrs;
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uint8_t event_intr_index;
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uint8_t moderation_level[VMXNET3_MAX_INTRS];
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uint32_t control;
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uint32_t reserved0[2];
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} __attribute__ (( packed ));
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/** Interrupt control - disable all interrupts */
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#define VMXNET3_IC_DISABLE_ALL 0x1
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/** Receive filter configuration */
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struct vmxnet3_rx_filter_config {
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/** Receive filter mode */
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uint32_t mode;
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/** Multicast filter table length */
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uint16_t multicast_len;
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/** Reserved */
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uint16_t reserved0;
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/** Multicast filter table address */
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uint64_t multicast_address;
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/** VLAN filter table (one bit per possible VLAN) */
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uint8_t vlan_filter[512];
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} __attribute__ (( packed ));
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/** Receive filter mode */
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enum vmxnet3_rx_filter_mode {
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VMXNET3_RXM_UCAST = 0x01, /**< Unicast only */
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VMXNET3_RXM_MCAST = 0x02, /**< Multicast passing the filters */
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VMXNET3_RXM_BCAST = 0x04, /**< Broadcast only */
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VMXNET3_RXM_ALL_MULTI = 0x08, /**< All multicast */
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VMXNET3_RXM_PROMISC = 0x10, /**< Promiscuous */
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};
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/** Variable-length configuration descriptor */
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struct vmxnet3_variable_config {
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uint32_t version;
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uint32_t length;
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uint64_t address;
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} __attribute__ (( packed ));
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/** Driver shared area */
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struct vmxnet3_shared {
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/** Magic signature */
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uint32_t magic;
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/** Reserved */
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uint32_t reserved0;
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/** Miscellaneous configuration */
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struct vmxnet3_misc_config misc;
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/** Interrupt configuration */
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struct vmxnet3_interrupt_config interrupt;
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/** Receive filter configuration */
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struct vmxnet3_rx_filter_config rx_filter;
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/** RSS configuration */
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struct vmxnet3_variable_config rss;
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/** Pattern-matching configuration */
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struct vmxnet3_variable_config pattern;
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/** Plugin configuration */
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struct vmxnet3_variable_config plugin;
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/** Event notifications */
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uint32_t ecr;
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/** Reserved */
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uint32_t reserved1[5];
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} __attribute__ (( packed ));
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/** Alignment of driver shared area */
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#define VMXNET3_SHARED_ALIGN 8
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/** Driver shared area magic */
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#define VMXNET3_SHARED_MAGIC 0xbabefee1
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/** Transmit descriptor */
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struct vmxnet3_tx_desc {
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/** Address */
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uint64_t address;
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/** Flags */
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uint32_t flags[2];
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} __attribute__ (( packed ));
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/** Transmit generation flag */
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#define VMXNET3_TXF_GEN 0x00004000UL
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/** Transmit end-of-packet flag */
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#define VMXNET3_TXF_EOP 0x000001000UL
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/** Transmit completion request flag */
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#define VMXNET3_TXF_CQ 0x000002000UL
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/** Transmit completion descriptor */
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struct vmxnet3_tx_comp {
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/** Index of the end-of-packet descriptor */
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uint32_t index;
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/** Reserved */
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uint32_t reserved0[2];
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/** Flags */
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uint32_t flags;
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} __attribute__ (( packed ));
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/** Transmit completion generation flag */
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#define VMXNET3_TXCF_GEN 0x80000000UL
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/** Transmit queue control */
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struct vmxnet3_tx_queue_control {
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uint32_t num_deferred;
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uint32_t threshold;
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uint64_t reserved0;
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} __attribute__ (( packed ));
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/** Transmit queue configuration */
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struct vmxnet3_tx_queue_config {
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/** Descriptor ring address */
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uint64_t desc_address;
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/** Data ring address */
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uint64_t immediate_address;
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/** Completion ring address */
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uint64_t comp_address;
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/** Driver-private data address */
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uint64_t driver_data_address;
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/** Reserved */
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uint64_t reserved0;
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/** Number of descriptors */
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uint32_t num_desc;
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/** Number of data descriptors */
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uint32_t num_immediate;
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/** Number of completion descriptors */
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uint32_t num_comp;
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/** Driver-private data length */
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uint32_t driver_data_len;
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/** Interrupt index */
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uint8_t intr_index;
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/** Reserved */
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uint8_t reserved[7];
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} __attribute__ (( packed ));
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/** Transmit queue statistics */
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struct vmxnet3_tx_stats {
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/** Reserved */
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uint64_t reserved[10];
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} __attribute__ (( packed ));
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/** Receive descriptor */
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struct vmxnet3_rx_desc {
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/** Address */
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uint64_t address;
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/** Flags */
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uint32_t flags;
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/** Reserved */
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uint32_t reserved0;
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} __attribute__ (( packed ));
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/** Receive generation flag */
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#define VMXNET3_RXF_GEN 0x80000000UL
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/** Receive completion descriptor */
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struct vmxnet3_rx_comp {
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/** Descriptor index */
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uint32_t index;
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/** RSS hash value */
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uint32_t rss;
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/** Length */
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uint32_t len;
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/** Flags */
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uint32_t flags;
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} __attribute__ (( packed ));
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/** Receive completion generation flag */
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#define VMXNET3_RXCF_GEN 0x80000000UL
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/** Receive queue control */
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struct vmxnet3_rx_queue_control {
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uint8_t update_prod;
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uint8_t reserved0[7];
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uint64_t reserved1;
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} __attribute__ (( packed ));
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/** Receive queue configuration */
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struct vmxnet3_rx_queue_config {
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/** Descriptor ring addresses */
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uint64_t desc_address[2];
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/** Completion ring address */
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uint64_t comp_address;
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/** Driver-private data address */
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uint64_t driver_data_address;
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/** Reserved */
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uint64_t reserved0;
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/** Number of descriptors */
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uint32_t num_desc[2];
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/** Number of completion descriptors */
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uint32_t num_comp;
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/** Driver-private data length */
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uint32_t driver_data_len;
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/** Interrupt index */
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uint8_t intr_index;
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/** Reserved */
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uint8_t reserved[7];
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} __attribute__ (( packed ));
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/** Receive queue statistics */
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struct vmxnet3_rx_stats {
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/** Reserved */
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uint64_t reserved[10];
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} __attribute__ (( packed ));
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/** Queue status */
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struct vmxnet3_queue_status {
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uint8_t stopped;
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uint8_t reserved0[3];
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uint32_t error;
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} __attribute__ (( packed ));
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/** Transmit queue descriptor */
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struct vmxnet3_tx_queue {
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struct vmxnet3_tx_queue_control ctrl;
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struct vmxnet3_tx_queue_config cfg;
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struct vmxnet3_queue_status status;
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struct vmxnet3_tx_stats state;
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uint8_t reserved[88];
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} __attribute__ (( packed ));
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/** Receive queue descriptor */
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struct vmxnet3_rx_queue {
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struct vmxnet3_rx_queue_control ctrl;
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struct vmxnet3_rx_queue_config cfg;
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struct vmxnet3_queue_status status;
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struct vmxnet3_rx_stats stats;
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uint8_t reserved[88];
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} __attribute__ (( packed ));
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/**
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* Queue descriptor set
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*
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* We use only a single TX and RX queue
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*/
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struct vmxnet3_queues {
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/** Transmit queue descriptor(s) */
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struct vmxnet3_tx_queue tx;
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/** Receive queue descriptor(s) */
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struct vmxnet3_rx_queue rx;
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} __attribute__ (( packed ));
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/** Alignment of queue descriptor set */
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#define VMXNET3_QUEUES_ALIGN 128
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/** Alignment of rings */
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#define VMXNET3_RING_ALIGN 512
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/** Number of TX descriptors */
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#define VMXNET3_NUM_TX_DESC 32
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/** Number of TX completion descriptors */
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#define VMXNET3_NUM_TX_COMP 32
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/** Number of RX descriptors */
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#define VMXNET3_NUM_RX_DESC 32
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/** Number of RX completion descriptors */
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#define VMXNET3_NUM_RX_COMP 32
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/**
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* DMA areas
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*
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* These are arranged in order of decreasing alignment, to allow for a
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* single allocation
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*/
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struct vmxnet3_dma {
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/** TX descriptor ring */
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struct vmxnet3_tx_desc tx_desc[VMXNET3_NUM_TX_DESC];
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/** TX completion ring */
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struct vmxnet3_tx_comp tx_comp[VMXNET3_NUM_TX_COMP];
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/** RX descriptor ring */
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struct vmxnet3_rx_desc rx_desc[VMXNET3_NUM_RX_DESC];
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/** RX completion ring */
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struct vmxnet3_rx_comp rx_comp[VMXNET3_NUM_RX_COMP];
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/** Queue descriptors */
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struct vmxnet3_queues queues;
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/** Shared area */
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struct vmxnet3_shared shared;
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} __attribute__ (( packed ));
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/** DMA area alignment */
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#define VMXNET3_DMA_ALIGN 512
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/** Producer and consumer counters */
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struct vmxnet3_counters {
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/** Transmit producer counter */
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unsigned int tx_prod;
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/** Transmit completion consumer counter */
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unsigned int tx_cons;
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/** Receive producer counter */
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unsigned int rx_prod;
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/** Receive fill level */
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unsigned int rx_fill;
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/** Receive consumer counter */
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unsigned int rx_cons;
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};
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/** A vmxnet3 NIC */
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struct vmxnet3_nic {
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/** "PT" register base address */
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void *pt;
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/** "VD" register base address */
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void *vd;
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/** DMA area */
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struct vmxnet3_dma *dma;
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/** Producer and consumer counters */
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struct vmxnet3_counters count;
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/** Transmit I/O buffers */
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struct io_buffer *tx_iobuf[VMXNET3_NUM_TX_DESC];
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[VMXNET3_NUM_RX_DESC];
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};
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/** vmxnet3 version that we support */
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#define VMXNET3_VERSION_SELECT 1
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/** UPT version that we support */
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#define VMXNET3_UPT_VERSION_SELECT 1
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/** MTU size */
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#define VMXNET3_MTU ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* FCS */ )
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/** Transmit ring maximum fill level */
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#define VMXNET3_TX_FILL ( VMXNET3_NUM_TX_DESC - 1 )
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/** Receive ring maximum fill level */
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#define VMXNET3_RX_FILL 8
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/** Received packet alignment padding */
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#define NET_IP_ALIGN 2
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#endif /* _VMXNET3_H */
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