357 lines
12 KiB
C
357 lines
12 KiB
C
#ifndef _VELOCITY_H
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#define _VELOCITY_H
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/** @file
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*
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* VIA Velocity network driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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/** Skeleton BAR size */
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#define VELOCITY_BAR_SIZE 256
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/** Default timeout */
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#define VELOCITY_TIMEOUT_US 10 * 1000
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struct velocity_frag {
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uint32_t addr;
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uint32_t des2;
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} __attribute__ ((packed));
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/** Velocity descriptor format */
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struct velocity_tx_descriptor {
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uint32_t des0;
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uint32_t des1;
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/* We only use the first fragment, the HW requires us to have 7 */
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struct velocity_frag frags[7];
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} __attribute__ ((packed));
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struct velocity_rx_descriptor {
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uint32_t des0;
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uint32_t des1;
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uint32_t addr;
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uint32_t des2;
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} __attribute__ ((packed));
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#define VELOCITY_DES0_RMBC(_n) (((_n) >> 16) & 0x1fff)
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#define VELOCITY_DES0_OWN (1 << 31)
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#define VELOCITY_DES0_TERR (1 << 15)
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#define VELOCITY_DES0_RXOK (1 << 15)
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#define VELOCITY_DES0_FDX (1 << 14)
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#define VELOCITY_DES0_GMII (1 << 13)
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#define VELOCITY_DES0_LNKFL (1 << 12)
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#define VELOCITY_DES0_SHDN (1 << 10)
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#define VELOCITY_DES0_CRS (1 << 9)
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#define VELOCITY_DES0_CDH (1 << 8)
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#define VELOCITY_DES0_ABT (1 << 7)
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#define VELOCITY_DES0_OWT (1 << 6)
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#define VELOCITY_DES0_OWC (1 << 5)
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#define VELOCITY_DES0_COLS (1 << 4)
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#define VELOCITY_DES0_RXSHDN (1 << 30)
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#define VELOCITY_DES0_RXER (1 << 5)
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#define VELOCITY_DES0_RLE (1 << 4)
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#define VELOCITY_DES0_CE (1 << 3)
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#define VELOCITY_DES0_FAE (1 << 2)
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#define VELOCITY_DES0_CRC (1 << 1)
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#define VELOCITY_DES0_RX_ERR ( VELOCITY_DES0_RXER | \
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VELOCITY_DES0_RLE | \
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VELOCITY_DES0_CE | \
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VELOCITY_DES0_FAE | \
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VELOCITY_DES0_CRC )
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/** TX descriptor fragment number */
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#define VELOCITY_DES1_FRAG(_n) (((_n + 1) & 0xf) << 28)
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#define VELOCITY_DES1_TCPLS ((1 << 24) | (1 << 25))
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#define VELOCITY_DES1_INTR (1 << 23)
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#define VELOCITY_DES1_PIC (1 << 22)
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#define VELOCITY_DES1_VETAG (1 << 21)
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#define VELOCITY_DES1_IPCK (1 << 20)
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#define VELOCITY_DES1_UDPCK (1 << 19)
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#define VELOCITY_DES1_TCPCK (1 << 18)
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#define VELOCITY_DES1_JMBO (1 << 17)
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#define VELOCITY_DES1_CRC (1 << 16)
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#define VELOCITY_DES2_IC (1 << 31)
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#define VELOCITY_DES2_SIZE(_n) (((_n) & 0x1fff) << 16)
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/** Number of receive descriptors
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*
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* Must be a multiple of 4 (hardware requirement).
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*/
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#define VELOCITY_RXDESC_NUM 8
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#define VELOCITY_RXDESC_SIZE \
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( VELOCITY_RXDESC_NUM * sizeof ( struct velocity_rx_descriptor ) )
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/** Number of transmit descriptors */
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#define VELOCITY_TXDESC_NUM 8
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#define VELOCITY_TXDESC_SIZE \
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( VELOCITY_TXDESC_NUM * sizeof ( struct velocity_tx_descriptor ) )
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/** Descriptor alignment */
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#define VELOCITY_RING_ALIGN 64
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/** Receive buffer length */
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#define VELOCITY_RX_MAX_LEN 1536
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/** MAC address registers */
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#define VELOCITY_MAC0 0x00
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#define VELOCITY_MAC1 0x01
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#define VELOCITY_MAC2 0x02
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#define VELOCITY_MAC3 0x03
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#define VELOCITY_MAC4 0x04
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#define VELOCITY_MAC5 0x05
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/** Receive control register */
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#define VELOCITY_RCR 0x06
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#define RHINE_RCR_SYMERR_ACCEPT (1 << 7) /*< Accept symbol error */
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#define RHINE_RCR_FILTER_ACCEPT (1 << 6) /*< Accept based on filter */
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#define RHINE_RCR_LONG_ACCEPT (1 << 5) /*< Accept long packets */
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#define RHINE_RCR_PROMISC (1 << 4) /*< Promiscuous mode */
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#define RHINE_RCR_BCAST_ACCEPT (1 << 3) /*< Accept broadcast */
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#define RHINE_RCR_MCAST_ACCEPT (1 << 2) /*< Accept multicast */
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#define RHINE_RCR_RUNT_ACCEPT (1 << 1) /*< Accept runt frames */
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#define RHINE_RCR_ERR_ACCEPT (1 << 0) /*< Accept erroneous frames */
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/** Transmit control register */
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#define VELOCITY_TCR 0x07
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#define VELOCITY_TCR_LB0 (1 << 0) /*< Loopback control */
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#define VELOCITY_TCR_LB1 (1 << 1) /*< Loopback control */
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#define VELOCITY_TCR_COLTMC0 (1 << 2) /*< Collision retry control */
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#define VELOCITY_TCR_COLTMC1 (1 << 3) /*< Collision retry control */
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/** Command register 0 (set) */
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#define VELOCITY_CRS0 0x08
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#define VELOCITY_CR0_TXON (1 << 3) /*< Transmit enable */
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#define VELOCITY_CR0_RXON (1 << 2) /*< Receive enable */
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#define VELOCITY_CR0_STOP (1 << 1) /*< Stop NIC */
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#define VELOCITY_CR0_START (1 << 0) /*< Start NIC */
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/** Command register 1 (set) */
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#define VELOCITY_CRS1 0x09
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#define VELOCITY_CR1_SFRST (1 << 7) /*< Software reset */
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#define VELOCITY_CR1_TM1EN (1 << 6) /*< Perioding software counting */
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#define VELOCITY_CR1_TM0EN (1 << 5) /*< Single-shot software counting */
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#define VELOCITY_CR1_DPOLL (1 << 3) /*< Disable auto polling */
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#define VELOCITY_CR1_DISAU (1 << 0) /*< Unicast reception disable */
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/** Command register 2 (set) */
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#define VELOCITY_CRS2 0x0A
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#define VELOCITY_CR2_XONEN (1 << 7) /*< XON/XOFF mode enable */
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#define VELOCITY_CR2_FDXTFCEN (1 << 6) /*< FDX flow control TX */
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#define VELOCITY_CR2_FDXRFCEN (1 << 5)
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#define VELOCITY_CR2_HDXFCEN (1 << 4)
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/** Command register 3 (set) */
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#define VELOCITY_CRS3 0x0B
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#define VELOCITY_CR3_FOSRST (1 << 6)
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#define VELOCITY_CR3_FPHYRST (1 << 5)
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#define VELOCITY_CR3_DIAG (1 << 4)
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#define VELOCITY_CR3_INTPCTL (1 << 2)
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#define VELOCITY_CR3_GINTMSK1 (1 << 1)
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#define VELOCITY_CR3_SWPEND (1 << 0)
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/** Command register 0 (clear) */
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#define VELOCITY_CRC0 0x0C
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/** Command register 1 (clear) */
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#define VELOCITY_CRC1 0x0D
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/** Command register 2 (clear */
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#define VELOCITY_CRC2 0x0E
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/** Command register 3 (clear */
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#define VELOCITY_CRC3 0x0F
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#define VELOCITY_CAM0 0x10
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#define VELOCITY_CAM1 0x11
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#define VELOCITY_CAM2 0x12
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#define VELOCITY_CAM3 0x13
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#define VELOCITY_CAM4 0x14
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#define VELOCITY_CAM5 0x15
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#define VELOCITY_CAM6 0x16
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#define VELOCITY_CAM7 0x17
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#define VELOCITY_TXDESC_HI 0x18 /* Hi part of 64bit txdesc base addr */
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#define VELOCITY_DATABUF_HI 0x1D /* Hi part of 64bit data buffer addr */
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#define VELOCITY_INTCTL0 0x20 /* interrupt control register */
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#define VELOCITY_RXSUPPTHR 0x20
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#define VELOCITY_TXSUPPTHR 0x20
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#define VELOCITY_INTHOLDOFF 0x20
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#define VELOCITY_INTCTL1 0x21 /* interrupt control register */
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#define VELOCITY_TXHOSTERR 0x22 /* TX host error status */
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#define VELOCITY_RXHOSTERR 0x23 /* RX host error status */
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/** Interrupt status register 0 */
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#define VELOCITY_ISR0 0x24
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#define VELOCITY_ISR0_PTX3 (1 << 7)
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#define VELOCITY_ISR0_PTX2 (1 << 6)
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#define VELOCITY_ISR0_PTX1 (1 << 5)
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#define VELOCITY_ISR0_PTX0 (1 << 4)
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#define VELOCITY_ISR0_PTXI (1 << 3)
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#define VELOCITY_ISR0_PRXI (1 << 2)
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#define VELOCITY_ISR0_PPTXI (1 << 1)
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#define VELOCITY_ISR0_PPRXI (1 << 0)
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/** Interrupt status register 1 */
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#define VELOCITY_ISR1 0x25
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#define VELOCITY_ISR1_SRCI (1 << 7)
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#define VELOCITY_ISR1_LSTPEI (1 << 6)
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#define VELOCITY_ISR1_LSTEI (1 << 5)
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#define VELOCITY_ISR1_OVFL (1 << 4)
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#define VELOCITY_ISR1_FLONI (1 << 3)
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#define VELOCITY_ISR1_RACEI (1 << 2)
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/** Interrupt status register 2 */
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#define VELOCITY_ISR2 0x26
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#define VELOCITY_ISR2_HFLD (1 << 7)
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#define VELOCITY_ISR2_UDPI (1 << 6)
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#define VELOCITY_ISR2_MIBFI (1 << 5)
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#define VELOCITY_ISR2_SHDNII (1 << 4)
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#define VELOCITY_ISR2_PHYI (1 << 3)
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#define VELOCITY_ISR2_PWEI (1 << 2)
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#define VELOCITY_ISR2_TMR1I (1 << 1)
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#define VELOCITY_ISR2_TMR0I (1 << 0)
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/** Interrupt status register 3 */
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#define VELOCITY_ISR3 0x27
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/** Interrupt mask register 0 */
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#define VELOCITY_IMR0 0x28
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/** Interrupt mask register 1 */
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#define VELOCITY_IMR1 0x29
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/** Interrupt mask register 2 */
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#define VELOCITY_IMR2 0x2a
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/** Interrupt mask register 3 */
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#define VELOCITY_IMR3 0x2b
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#define VELOCITY_TXSTS_PORT 0x2C /* Transmit status port (???) */
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#define VELOCITY_TXQCSRS 0x30 /* TX queue ctl/status set */
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#define VELOCITY_TXQCSRS_DEAD3 (1 << 15)
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#define VELOCITY_TXQCSRS_WAK3 (1 << 14)
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#define VELOCITY_TXQCSRS_ACT3 (1 << 13)
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#define VELOCITY_TXQCSRS_RUN3 (1 << 12)
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#define VELOCITY_TXQCSRS_DEAD2 (1 << 11)
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#define VELOCITY_TXQCSRS_WAK2 (1 << 10)
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#define VELOCITY_TXQCSRS_ACT2 (1 << 9)
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#define VELOCITY_TXQCSRS_RUN2 (1 << 8)
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#define VELOCITY_TXQCSRS_DEAD1 (1 << 7)
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#define VELOCITY_TXQCSRS_WAK1 (1 << 6)
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#define VELOCITY_TXQCSRS_ACT1 (1 << 5)
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#define VELOCITY_TXQCSRS_RUN1 (1 << 4)
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#define VELOCITY_TXQCSRS_DEAD0 (1 << 3)
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#define VELOCITY_TXQCSRS_WAK0 (1 << 2)
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#define VELOCITY_TXQCSRS_ACT0 (1 << 1)
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#define VELOCITY_TXQCSRS_RUN0 (1 << 0)
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#define VELOCITY_RXQCSRS 0x32 /* RX queue ctl/status set */
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#define VELOCITY_RXQCSRC 0x36
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#define VELOCITY_RXQCSR_DEAD (1 << 3)
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#define VELOCITY_RXQCSR_WAK (1 << 2)
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#define VELOCITY_RXQCSR_ACT (1 << 1)
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#define VELOCITY_RXQCSR_RUN (1 << 0)
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#define VELOCITY_TXQCSRC 0x34 /* TX queue ctl/status clear */
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#define VELOCITY_RXQCSRC 0x36 /* RX queue ctl/status clear */
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#define VELOCITY_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
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#define VELOCITY_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
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#define VELOCITY_TXQTIMER 0x3E /* TX queue timer pend register */
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#define VELOCITY_RXQTIMER 0x3F /* RX queue timer pend register */
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#define VELOCITY_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
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#define VELOCITY_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
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#define VELOCITY_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
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#define VELOCITY_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */
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#define VELOCITY_RXDESCNUM 0x50 /* Size of RX desc ring */
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#define VELOCITY_TXDESCNUM 0x52 /* Size of TX desc ring */
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#define VELOCITY_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */
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#define VELOCITY_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */
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#define VELOCITY_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */
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#define VELOCITY_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */
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#define VELOCITY_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */
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#define VELOCITY_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */
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#define VELOCITY_FIFOTEST0 0x60 /* FIFO test register */
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#define VELOCITY_FIFOTEST1 0x64 /* FIFO test register */
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#define VELOCITY_CAMADDR 0x68 /* CAM address register */
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#define VELOCITY_CAMCTL 0x69 /* CAM control register */
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#define VELOCITY_MIICFG 0x6C /* MII port config register */
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#define VELOCITY_MIISR 0x6D /* MII port status register */
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#define VELOCITY_MIISR_IDLE (1 << 7)
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#define VELOCITY_PHYSTS0 0x6E /* PHY status register */
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#define VELOCITY_PHYSTS0_LINK (1 << 6)
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#define VELOCITY_PHYSTS1 0x6F /* PHY status register */
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#define VELOCITY_MIICR 0x70 /* MII command register */
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#define VELOCITY_MIICR_MAUTO (1 << 7)
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#define VELOCITY_MIICR_RCMD (1 << 6)
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#define VELOCITY_MIICR_WCMD (1 << 5)
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#define VELOCITY_MIICR_MDPM (1 << 4)
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#define VELOCITY_MIICR_MOUT (1 << 3)
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#define VELOCITY_MIICR_MDO (1 << 2)
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#define VELOCITY_MIICR_MDI (1 << 1)
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#define VELOCITY_MIICR_MDC (1 << 0)
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#define VELOCITY_MIIADDR 0x71 /* MII address register */
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#define VELOCITY_MIIDATA 0x72 /* MII data register */
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#define VELOCITY_SSTIMER 0x74 /* single-shot timer */
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#define VELOCITY_PTIMER 0x76 /* periodic timer */
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#define VELOCITY_DMACFG0 0x7C /* DMA config 0 */
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#define VELOCITY_DMACFG1 0x7D /* DMA config 1 */
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#define VELOCITY_RXCFG 0x7E /* MAC RX config */
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#define VELOCITY_TXCFG 0x7F /* MAC TX config */
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#define VELOCITY_SWEEDATA 0x85 /* EEPROM software loaded data */
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/** Chip Configuration Register A */
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#define VELOCITY_CFGA 0x78
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#define VELOCITY_CFGA_PACPI (1 << 0)
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/** Power Management Sticky Register */
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#define VELOCITY_STICKY 0x83
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#define VELOCITY_STICKY_DS0 (1 << 0)
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#define VELOCITY_STICKY_DS1 (1 << 1)
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#define VELOCITY_EEWRDAT 0x8C /* EEPROM embedded write */
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#define VELOCITY_EECSUM 0x92 /* EEPROM checksum */
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#define VELOCITY_EECSR 0x93 /* EEPROM control/status */
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#define VELOCITY_EECSR_RELOAD (1 << 5)
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#define VELOCITY_EERDDAT 0x94 /* EEPROM embedded read */
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#define VELOCITY_EEADDR 0x96 /* EEPROM address */
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#define VELOCITY_EECMD 0x97 /* EEPROM embedded command */
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/** A Velocity network card */
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struct velocity_nic {
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/** Registers */
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void *regs;
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/** MII interface */
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struct mii_interface mii;
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/** Netdev */
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struct net_device *netdev;
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/** Receive descriptor ring */
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struct velocity_rx_descriptor *rx_ring;
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/** Receive I/O buffers */
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struct io_buffer *rx_buffs[VELOCITY_RXDESC_NUM];
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/** Receive producer index */
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unsigned int rx_prod;
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/** Receive consumer index */
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unsigned int rx_cons;
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/** Receive commit number
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*
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* Used to fullfill the hardware requirement of returning receive buffers
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* to the hardware only in blocks of 4.
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*/
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unsigned int rx_commit;
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/** Transmit descriptor ring */
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struct velocity_tx_descriptor *tx_ring;
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/** Transmit producer index */
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unsigned int tx_prod;
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/** Transmit consumer index */
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unsigned int tx_cons;
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};
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#endif /* _VELOCITY_H */
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