118 lines
4.0 KiB
C
118 lines
4.0 KiB
C
#ifndef _INTELX_H
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#define _INTELX_H
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/** @file
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*
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* Intel 10 Gigabit Ethernet network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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#include "intel.h"
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/** Device Control Register */
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#define INTELX_CTRL 0x00000UL
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#define INTELX_CTRL_LRST 0x00000008UL /**< Link reset */
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#define INTELX_CTRL_RST 0x04000000UL /**< Device reset */
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/** Time to delay for device reset, in milliseconds */
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#define INTELX_RESET_DELAY_MS 20
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/** Extended Interrupt Cause Read Register */
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#define INTELX_EICR 0x00800UL
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#define INTELX_EIRQ_RX0 0x00000001UL /**< RX0 (via IVAR) */
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#define INTELX_EIRQ_TX0 0x00000002UL /**< RX0 (via IVAR) */
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#define INTELX_EIRQ_RXO 0x00020000UL /**< Receive overrun */
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#define INTELX_EIRQ_LSC 0x00100000UL /**< Link status change */
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/** Interrupt Mask Set/Read Register */
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#define INTELX_EIMS 0x00880UL
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/** Interrupt Mask Clear Register */
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#define INTELX_EIMC 0x00888UL
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/** Interrupt Vector Allocation Register */
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#define INTELX_IVAR 0x00900UL
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#define INTELX_IVAR_RX0(bit) ( (bit) << 0 ) /**< RX queue 0 allocation */
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#define INTELX_IVAR_RX0_DEFAULT INTELX_IVAR_RX0 ( 0x00 )
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#define INTELX_IVAR_RX0_MASK INTELX_IVAR_RX0 ( 0x3f )
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#define INTELX_IVAR_RX0_VALID 0x00000080UL /**< RX queue 0 valid */
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#define INTELX_IVAR_TX0(bit) ( (bit) << 8 ) /**< TX queue 0 allocation */
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#define INTELX_IVAR_TX0_DEFAULT INTELX_IVAR_TX0 ( 0x01 )
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#define INTELX_IVAR_TX0_MASK INTELX_IVAR_TX0 ( 0x3f )
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#define INTELX_IVAR_TX0_VALID 0x00008000UL /**< TX queue 0 valid */
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/** Receive Filter Control Register */
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#define INTELX_FCTRL 0x05080UL
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#define INTELX_FCTRL_MPE 0x00000100UL /**< Multicast promiscuous */
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#define INTELX_FCTRL_UPE 0x00000200UL /**< Unicast promiscuous mode */
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#define INTELX_FCTRL_BAM 0x00000400UL /**< Broadcast accept mode */
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/** Receive Address Low
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*
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* The MAC address registers RAL0/RAH0 exist at address 0x05400 for
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* the 82598 and 0x0a200 for the 82599, according to the datasheet.
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* In practice, the 82599 seems to also provide a copy of these
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* registers at 0x05400. To aim for maximum compatibility, we try
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* both addresses when reading the initial MAC address, and set both
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* addresses when setting the MAC address.
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*/
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#define INTELX_RAL0 0x05400UL
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#define INTELX_RAL0_ALT 0x0a200UL
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/** Receive Address High */
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#define INTELX_RAH0 0x05404UL
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#define INTELX_RAH0_ALT 0x0a204UL
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#define INTELX_RAH0_AV 0x80000000UL /**< Address valid */
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/** Receive Descriptor register block */
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#define INTELX_RD 0x01000UL
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/** Receive Descriptor Control Register */
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#define INTELX_RXDCTL_VME 0x40000000UL /**< Strip VLAN tag */
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/** Split Receive Control Register */
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#define INTELX_SRRCTL 0x02100UL
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#define INTELX_SRRCTL_BSIZE(kb) ( (kb) << 0 ) /**< Receive buffer size */
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#define INTELX_SRRCTL_BSIZE_DEFAULT INTELX_SRRCTL_BSIZE ( 0x02 )
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#define INTELX_SRRCTL_BSIZE_MASK INTELX_SRRCTL_BSIZE ( 0x1f )
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/** Receive DMA Control Register */
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#define INTELX_RDRXCTL 0x02f00UL
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#define INTELX_RDRXCTL_SECRC 0x00000001UL /**< Strip CRC */
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/** Receive Control Register */
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#define INTELX_RXCTRL 0x03000UL
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#define INTELX_RXCTRL_RXEN 0x00000001UL /**< Receive enable */
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/** Transmit DMA Control Register */
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#define INTELX_DMATXCTL 0x04a80UL
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#define INTELX_DMATXCTL_TE 0x00000001UL /**< Transmit enable */
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/** Transmit Descriptor register block */
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#define INTELX_TD 0x06000UL
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/** RX DCA Control Register */
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#define INTELX_DCA_RXCTRL 0x02200UL
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#define INTELX_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */
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/** MAC Core Control 0 Register */
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#define INTELX_HLREG0 0x04240UL
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#define INTELX_HLREG0_JUMBOEN 0x00000004UL /**< Jumbo frame enable */
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/** Maximum Frame Size Register */
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#define INTELX_MAXFRS 0x04268UL
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#define INTELX_MAXFRS_MFS(len) ( (len) << 16 ) /**< Maximum frame size */
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#define INTELX_MAXFRS_MFS_DEFAULT \
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INTELX_MAXFRS_MFS ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
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#define INTELX_MAXFRS_MFS_MASK INTELX_MAXFRS_MFS ( 0xffff )
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/** Link Status Register */
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#define INTELX_LINKS 0x042a4UL
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#define INTELX_LINKS_UP 0x40000000UL /**< Link up */
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#endif /* _INTELX_H */
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