195 lines
4.6 KiB
C
195 lines
4.6 KiB
C
#ifndef _DM96XX_H
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#define _DM96XX_H
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/** @file
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*
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* Davicom DM96xx USB Ethernet driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/usb.h>
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#include <ipxe/usbnet.h>
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#include <ipxe/if_ether.h>
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/** Read register(s) */
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#define DM96XX_READ_REGISTER \
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( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
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USB_REQUEST_TYPE ( 0x00 ) )
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/** Write register(s) */
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#define DM96XX_WRITE_REGISTER \
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( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
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USB_REQUEST_TYPE ( 0x01 ) )
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/** Write single register */
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#define DM96XX_WRITE1_REGISTER \
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( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
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USB_REQUEST_TYPE ( 0x03 ) )
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/** Network control register */
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#define DM96XX_NCR 0x00
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#define DM96XX_NCR_RST 0x01 /**< Software reset */
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/** Network status register */
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#define DM96XX_NSR 0x01
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#define DM96XX_NSR_LINKST 0x40 /**< Link status */
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/** Receive control register */
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#define DM96XX_RCR 0x05
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#define DM96XX_RCR_ALL 0x08 /**< Pass all multicast */
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#define DM96XX_RCR_RUNT 0x04 /**< Pass runt packet */
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#define DM96XX_RCR_PRMSC 0x02 /**< Promiscuous mode */
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#define DM96XX_RCR_RXEN 0x01 /**< RX enable */
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/** Receive status register */
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#define DM96XX_RSR 0x06
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#define DM96XX_RSR_MF 0x40 /**< Multicast frame */
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/** PHY address registers */
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#define DM96XX_PAR 0x10
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/** Chip revision register */
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#define DM96XX_CHIPR 0x2c
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#define DM96XX_CHIPR_9601 0x00 /**< DM9601 */
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#define DM96XX_CHIPR_9620 0x01 /**< DM9620 */
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/** RX header control/status register (DM9620+ only) */
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#define DM96XX_MODE_CTL 0x91
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#define DM96XX_MODE_CTL_MODE 0x80 /**< 4-byte header mode */
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/** DM96xx interrupt data */
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struct dm96xx_interrupt {
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/** Network status register */
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uint8_t nsr;
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/** Transmit status registers */
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uint8_t tsr[2];
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/** Receive status register */
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uint8_t rsr;
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/** Receive overflow counter register */
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uint8_t rocr;
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/** Receive packet counter */
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uint8_t rxc;
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/** Transmit packet counter */
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uint8_t txc;
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/** General purpose register */
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uint8_t gpr;
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} __attribute__ (( packed ));
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/** DM96xx receive header */
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struct dm96xx_rx_header {
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/** Packet status */
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uint8_t rsr;
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/** Packet length (excluding this header, including CRC) */
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uint16_t len;
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} __attribute__ (( packed ));
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/** DM96xx transmit header */
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struct dm96xx_tx_header {
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/** Packet length (excluding this header) */
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uint16_t len;
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} __attribute__ (( packed ));
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/** A DM96xx network device */
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struct dm96xx_device {
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/** USB device */
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struct usb_device *usb;
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/** USB bus */
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struct usb_bus *bus;
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/** Network device */
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struct net_device *netdev;
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/** USB network device */
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struct usbnet_device usbnet;
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};
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/**
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* Read registers
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*
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* @v dm96xx DM96xx device
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* @v offset Register offset
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* @v data Data buffer
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* @v len Length of data
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* @ret rc Return status code
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*/
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static inline __attribute__ (( always_inline )) int
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dm96xx_read_registers ( struct dm96xx_device *dm96xx, unsigned int offset,
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void *data, size_t len ) {
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return usb_control ( dm96xx->usb, DM96XX_READ_REGISTER, 0, offset,
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data, len );
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}
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/**
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* Read register
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*
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* @v dm96xx DM96xx device
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* @v offset Register offset
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* @ret value Register value, or negative error
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*/
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static inline __attribute__ (( always_inline )) int
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dm96xx_read_register ( struct dm96xx_device *dm96xx, unsigned int offset ) {
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uint8_t value;
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int rc;
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if ( ( rc = dm96xx_read_registers ( dm96xx, offset, &value,
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sizeof ( value ) ) ) != 0 )
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return rc;
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return value;
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}
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/**
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* Write registers
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*
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* @v dm96xx DM96xx device
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* @v offset Register offset
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* @v data Data buffer
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* @v len Length of data
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* @ret rc Return status code
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*/
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static inline __attribute__ (( always_inline )) int
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dm96xx_write_registers ( struct dm96xx_device *dm96xx, unsigned int offset,
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void *data, size_t len ) {
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return usb_control ( dm96xx->usb, DM96XX_WRITE_REGISTER, 0, offset,
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data, len );
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}
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/**
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* Write register
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*
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* @v dm96xx DM96xx device
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* @v offset Register offset
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* @v value Register value
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* @ret rc Return status code
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*/
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static inline __attribute__ (( always_inline )) int
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dm96xx_write_register ( struct dm96xx_device *dm96xx, unsigned int offset,
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uint8_t value ) {
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return usb_control ( dm96xx->usb, DM96XX_WRITE1_REGISTER, value,
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offset, NULL, 0 );
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}
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/** Reset delay (in microseconds) */
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#define DM96XX_RESET_DELAY_US 10
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/** Interrupt maximum fill level
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*
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* This is a policy decision.
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*/
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#define DM96XX_INTR_MAX_FILL 2
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/** Bulk IN maximum fill level
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*
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* This is a policy decision.
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*/
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#define DM96XX_IN_MAX_FILL 8
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/** Bulk IN buffer size */
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#define DM96XX_IN_MTU \
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( 4 /* DM96xx header */ + ETH_FRAME_LEN + \
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4 /* possible VLAN header */ + 4 /* CRC */ )
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#endif /* _DM96XX_H */
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