175 lines
4.1 KiB
C
175 lines
4.1 KiB
C
#ifndef _AXGE_H
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#define _AXGE_H
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/** @file
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*
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* Asix 10/100/1000 USB Ethernet driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/usb.h>
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#include <ipxe/usbnet.h>
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/** Read MAC register */
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#define AXGE_READ_MAC_REGISTER \
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( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
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USB_REQUEST_TYPE ( 0x01 ) )
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/** Write MAC register */
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#define AXGE_WRITE_MAC_REGISTER \
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( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
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USB_REQUEST_TYPE ( 0x01 ) )
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/** Physical Link Status Register */
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#define AXGE_PLSR 0x02
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#define AXGE_PLSR_EPHY_10 0x10 /**< Ethernet at 10Mbps */
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#define AXGE_PLSR_EPHY_100 0x20 /**< Ethernet at 100Mbps */
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#define AXGE_PLSR_EPHY_1000 0x40 /**< Ethernet at 1000Mbps */
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#define AXGE_PLSR_EPHY_ANY \
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( AXGE_PLSR_EPHY_10 | \
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AXGE_PLSR_EPHY_100 | \
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AXGE_PLSR_EPHY_1000 )
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/** RX Control Register */
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#define AXGE_RCR 0x0b
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#define AXGE_RCR_PRO 0x0001 /**< Promiscuous mode */
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#define AXGE_RCR_AMALL 0x0002 /**< Accept all multicasts */
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#define AXGE_RCR_AB 0x0008 /**< Accept broadcasts */
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#define AXGE_RCR_SO 0x0080 /**< Start operation */
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/** Node ID Register */
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#define AXGE_NIDR 0x10
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/** Medium Status Register */
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#define AXGE_MSR 0x22
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#define AXGE_MSR_GM 0x0001 /**< Gigabit mode */
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#define AXGE_MSR_FD 0x0002 /**< Full duplex */
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#define AXGE_MSR_RFC 0x0010 /**< RX flow control enable */
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#define AXGE_MSR_TFC 0x0020 /**< TX flow control enable */
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#define AXGE_MSR_RE 0x0100 /**< Receive enable */
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/** Ethernet PHY Power and Reset Control Register */
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#define AXGE_EPPRCR 0x26
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#define AXGE_EPPRCR_IPRL 0x0020 /**< Undocumented */
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/** Delay after initialising EPPRCR */
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#define AXGE_EPPRCR_DELAY_MS 200
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/** Bulk IN Control Register (undocumented) */
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#define AXGE_BICR 0x2e
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/** Bulk IN Control (undocumented) */
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struct axge_bulk_in_control {
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/** Control */
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uint8_t ctrl;
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/** Timer */
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uint16_t timer;
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/** Size */
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uint8_t size;
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/** Inter-frame gap */
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uint8_t ifg;
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} __attribute__ (( packed ));
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/** Clock Select Register (undocumented) */
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#define AXGE_CSR 0x33
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#define AXGE_CSR_BCS 0x01 /**< Undocumented */
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#define AXGE_CSR_ACS 0x02 /**< Undocumented */
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/** Delay after initialising CSR */
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#define AXGE_CSR_DELAY_MS 100
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/** Transmit packet header */
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struct axge_tx_header {
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/** Packet length */
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uint32_t len;
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/** Answers on a postcard, please */
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uint32_t wtf;
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} __attribute__ (( packed ));
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/** Receive packet footer */
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struct axge_rx_footer {
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/** Packet count */
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uint16_t count;
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/** Header offset */
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uint16_t offset;
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} __attribute__ (( packed ));
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/** Receive packet descriptor */
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struct axge_rx_descriptor {
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/** Checksum information */
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uint16_t check;
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/** Length and error flags */
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uint16_t len_flags;
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} __attribute__ (( packed ));
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/** Receive packet length mask */
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#define AXGE_RX_LEN_MASK 0x1fff
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/** Receive packet length alignment */
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#define AXGE_RX_LEN_PAD_ALIGN 8
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/** Receive packet CRC error */
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#define AXGE_RX_CRC_ERROR 0x2000
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/** Receive packet dropped error */
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#define AXGE_RX_DROP_ERROR 0x8000
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/** Interrupt data */
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struct axge_interrupt {
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/** Magic signature */
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uint16_t magic;
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/** Link state */
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uint16_t link;
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/** PHY register MR01 */
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uint16_t mr01;
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/** PHY register MR05 */
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uint16_t mr05;
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} __attribute__ (( packed ));
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/** Interrupt magic signature */
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#define AXGE_INTR_MAGIC 0x00a1
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/** Link is up */
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#define AXGE_INTR_LINK_PPLS 0x0001
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/** An AXGE network device */
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struct axge_device {
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/** USB device */
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struct usb_device *usb;
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/** USB bus */
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struct usb_bus *bus;
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/** Network device */
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struct net_device *netdev;
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/** USB network device */
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struct usbnet_device usbnet;
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};
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/** Interrupt maximum fill level
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*
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* This is a policy decision.
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*/
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#define AXGE_INTR_MAX_FILL 2
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/** Bulk IN maximum fill level
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*
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* This is a policy decision.
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*/
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#define AXGE_IN_MAX_FILL 8
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/** Bulk IN buffer size
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*
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* This is a policy decision.
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*/
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#define AXGE_IN_MTU 2048
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/** Amount of space to reserve at start of bulk IN buffers
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*
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* This is required to allow for protocols such as ARP which may reuse
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* a received I/O buffer for transmission.
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*/
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#define AXGE_IN_RESERVE sizeof ( struct axge_tx_header )
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#endif /* _AXGE_H */
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