370 lines
9.9 KiB
C
370 lines
9.9 KiB
C
#ifndef _QIB7322_H
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#define _QIB7322_H
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/*
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* Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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/**
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* @file
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*
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* QLogic QIB7322 Infiniband HCA
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*
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*/
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#define PSEUDOBIT_LITTLE_ENDIAN
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#include <ipxe/pseudobit.h>
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#include "qib_7322_regs.h"
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/** A QIB7322 GPIO register */
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struct QIB_7322_GPIO_pb {
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pseudo_bit_t GPIO[16];
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pseudo_bit_t Reserved[48];
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};
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struct QIB_7322_GPIO {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIO_pb );
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};
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/** A QIB7322 general scalar register */
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struct QIB_7322_scalar_pb {
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pseudo_bit_t Value[64];
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};
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struct QIB_7322_scalar {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_scalar_pb );
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};
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/** QIB7322 feature mask */
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struct QIB_7322_feature_mask_pb {
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pseudo_bit_t Port0_Link_Speed_Supported[3];
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pseudo_bit_t Port1_Link_Speed_Supported[3];
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pseudo_bit_t _unused_0[58];
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};
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struct QIB_7322_feature_mask {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_feature_mask_pb );
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};
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/** QIB7322 send per-buffer control word */
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struct QIB_7322_SendPbc_pb {
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pseudo_bit_t LengthP1_toibc[11];
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pseudo_bit_t Reserved1[4];
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pseudo_bit_t LengthP1_trigger[11];
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pseudo_bit_t Reserved2[3];
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pseudo_bit_t TestEbp[1];
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pseudo_bit_t Test[1];
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pseudo_bit_t Intr[1];
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pseudo_bit_t StaticRateControlCnt[14];
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pseudo_bit_t Reserved3[12];
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pseudo_bit_t Port[1];
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pseudo_bit_t VLane[3];
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pseudo_bit_t Reserved4[1];
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pseudo_bit_t VL15[1];
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};
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struct QIB_7322_SendPbc {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbc_pb );
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};
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/** QIB7322 send buffer availability */
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struct QIB_7322_SendBufAvail_pb {
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pseudo_bit_t InUseCheck[162][2];
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pseudo_bit_t Reserved[60];
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};
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struct QIB_7322_SendBufAvail {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail_pb );
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};
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/** DMA alignment for send buffer availability */
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#define QIB7322_SENDBUFAVAIL_ALIGN 64
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/** QIB7322 port-specific receive control */
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struct QIB_7322_RcvCtrl_P_pb {
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pseudo_bit_t ContextEnable[18];
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pseudo_bit_t _unused_1[21];
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pseudo_bit_t RcvIBPortEnable[1];
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pseudo_bit_t RcvQPMapEnable[1];
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pseudo_bit_t RcvPartitionKeyDisable[1];
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pseudo_bit_t RcvResetCredit[1];
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pseudo_bit_t _unused_2[21];
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};
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struct QIB_7322_RcvCtrl_P {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_P_pb );
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};
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/** A QIB7322 eager receive descriptor */
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struct QIB_7322_RcvEgr_pb {
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pseudo_bit_t Addr[37];
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pseudo_bit_t BufSize[3];
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pseudo_bit_t Reserved[24];
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};
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struct QIB_7322_RcvEgr {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgr_pb );
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};
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/** QIB7322 receive header flags */
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struct QIB_7322_RcvHdrFlags_pb {
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pseudo_bit_t PktLen[11];
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pseudo_bit_t RcvType[3];
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pseudo_bit_t SoftB[1];
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pseudo_bit_t SoftA[1];
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pseudo_bit_t EgrIndex[12];
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pseudo_bit_t Reserved1[3];
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pseudo_bit_t UseEgrBfr[1];
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pseudo_bit_t RcvSeq[4];
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pseudo_bit_t HdrqOffset[11];
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pseudo_bit_t Reserved2[8];
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pseudo_bit_t IBErr[1];
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pseudo_bit_t MKErr[1];
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pseudo_bit_t TIDErr[1];
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pseudo_bit_t KHdrErr[1];
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pseudo_bit_t MTUErr[1];
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pseudo_bit_t LenErr[1];
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pseudo_bit_t ParityErr[1];
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pseudo_bit_t VCRCErr[1];
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pseudo_bit_t ICRCErr[1];
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};
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struct QIB_7322_RcvHdrFlags {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrFlags_pb );
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};
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/** QIB7322 DDS tuning parameters */
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struct QIB_7322_IBSD_DDS_MAP_TABLE_pb {
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pseudo_bit_t Pre[3];
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pseudo_bit_t PreXtra[2];
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pseudo_bit_t Post[4];
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pseudo_bit_t Main[5];
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pseudo_bit_t Amp[4];
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pseudo_bit_t _unused_0[46];
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};
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struct QIB_7322_IBSD_DDS_MAP_TABLE {
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PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_DDS_MAP_TABLE_pb );
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};
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/** QIB7322 memory BAR size */
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#define QIB7322_BAR0_SIZE 0x400000
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/** QIB7322 base port number */
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#define QIB7322_PORT_BASE 1
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/** QIB7322 maximum number of ports */
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#define QIB7322_MAX_PORTS 2
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/** QIB7322 maximum width */
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#define QIB7322_MAX_WIDTH 4
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/** QIB7322 board identifiers */
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enum qib7322_board_id {
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QIB7322_BOARD_QLE7342_EMULATION = 0,
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QIB7322_BOARD_QLE7340 = 1,
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QIB7322_BOARD_QLE7342 = 2,
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QIB7322_BOARD_QMI7342 = 3,
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QIB7322_BOARD_QMH7342_UNSUPPORTED = 4,
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QIB7322_BOARD_QME7342 = 5,
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QIB7322_BOARD_QMH7342 = 6,
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QIB7322_BOARD_QLE7342_TEST = 15,
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};
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/** QIB7322 I2C SCL line GPIO number */
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#define QIB7322_GPIO_SCL 0
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/** QIB7322 I2C SDA line GPIO number */
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#define QIB7322_GPIO_SDA 1
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/** GUID offset within EEPROM */
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#define QIB7322_EEPROM_GUID_OFFSET 3
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/** GUID size within EEPROM */
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#define QIB7322_EEPROM_GUID_SIZE 8
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/** Board serial number offset within EEPROM */
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#define QIB7322_EEPROM_SERIAL_OFFSET 12
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/** Board serial number size within EEPROM */
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#define QIB7322_EEPROM_SERIAL_SIZE 12
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/** QIB7322 small send buffer size */
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#define QIB7322_SMALL_SEND_BUF_SIZE 4096
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/** QIB7322 small send buffer starting index */
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#define QIB7322_SMALL_SEND_BUF_START 0
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/** QIB7322 small send buffer count */
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#define QIB7322_SMALL_SEND_BUF_COUNT 128
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/** QIB7322 large send buffer size */
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#define QIB7322_LARGE_SEND_BUF_SIZE 8192
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/** QIB7322 large send buffer starting index */
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#define QIB7322_LARGE_SEND_BUF_START 128
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/** QIB7322 large send buffer count */
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#define QIB7322_LARGE_SEND_BUF_COUNT 32
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/** QIB7322 VL15 port 0 send buffer starting index */
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#define QIB7322_VL15_PORT0_SEND_BUF_START 160
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/** QIB7322 VL15 port 0 send buffer count */
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#define QIB7322_VL15_PORT0_SEND_BUF_COUNT 1
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/** QIB7322 VL15 port 0 send buffer size */
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#define QIB7322_VL15_PORT0_SEND_BUF_SIZE 8192
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/** QIB7322 VL15 port 0 send buffer starting index */
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#define QIB7322_VL15_PORT1_SEND_BUF_START 161
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/** QIB7322 VL15 port 0 send buffer count */
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#define QIB7322_VL15_PORT1_SEND_BUF_COUNT 1
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/** QIB7322 VL15 port 0 send buffer size */
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#define QIB7322_VL15_PORT1_SEND_BUF_SIZE 8192
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/** Number of small send buffers used
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*
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* This is a policy decision. Must be less than or equal to the total
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* number of small send buffers supported by the hardware
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* (QIB7322_SMALL_SEND_BUF_COUNT).
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*/
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#define QIB7322_SMALL_SEND_BUF_USED 32
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/** Number of contexts (including kernel context)
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*
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* This is a policy decision. Must be 6, 10 or 18.
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*/
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#define QIB7322_NUM_CONTEXTS 6
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/** ContextCfg values for different numbers of contexts */
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enum qib7322_contextcfg {
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QIB7322_CONTEXTCFG_6CTX = 0,
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QIB7322_CONTEXTCFG_10CTX = 1,
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QIB7322_CONTEXTCFG_18CTX = 2,
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};
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/** ContextCfg values for different numbers of contexts */
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#define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL 1024
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#define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER 4096
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#define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL 1024
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#define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER 2048
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#define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL 1024
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#define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER 1024
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/** Eager buffer required alignment */
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#define QIB7322_EAGER_BUFFER_ALIGN 2048
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/** Eager buffer size encodings */
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enum qib7322_eager_buffer_size {
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QIB7322_EAGER_BUFFER_NONE = 0,
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QIB7322_EAGER_BUFFER_2K = 1,
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QIB7322_EAGER_BUFFER_4K = 2,
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QIB7322_EAGER_BUFFER_8K = 3,
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QIB7322_EAGER_BUFFER_16K = 4,
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QIB7322_EAGER_BUFFER_32K = 5,
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QIB7322_EAGER_BUFFER_64K = 6,
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};
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/** Number of RX headers per context
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*
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* This is a policy decision.
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*/
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#define QIB7322_RECV_HEADER_COUNT 8
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/** Maximum size of each RX header
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*
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* This is a policy decision. Must be divisible by 4.
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*/
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#define QIB7322_RECV_HEADER_SIZE 96
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/** Total size of an RX header ring */
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#define QIB7322_RECV_HEADERS_SIZE \
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( QIB7322_RECV_HEADER_SIZE * QIB7322_RECV_HEADER_COUNT )
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/** RX header alignment */
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#define QIB7322_RECV_HEADERS_ALIGN 64
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/** RX payload size
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*
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* This is a policy decision. Must be a valid eager buffer size.
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*/
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#define QIB7322_RECV_PAYLOAD_SIZE 2048
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/** Maximum number of credits per port
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*
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* 64kB of internal RX buffer space, in units of 64 bytes, split
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* between two ports.
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*/
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#define QIB7322_MAX_CREDITS ( ( 65536 / 64 ) / QIB7322_MAX_PORTS )
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/** Number of credits to advertise for VL15
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*
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* This is a policy decision. Using 9 credits allows for 9*64=576
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* bytes, which is enough for two MADs.
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*/
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#define QIB7322_MAX_CREDITS_VL15 9
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/** Number of credits to advertise for VL0
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*
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* This is a policy decision.
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*/
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#define QIB7322_MAX_CREDITS_VL0 \
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( QIB7322_MAX_CREDITS - QIB7322_MAX_CREDITS_VL15 )
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/** QPN used for Infinipath Packets
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*
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* This is a policy decision. Must have bit 0 clear. Must not be a
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* QPN that we will use.
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*/
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#define QIB7322_QP_IDETH 0xdead0
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/** Maximum time for wait for AHB, in us */
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#define QIB7322_AHB_MAX_WAIT_US 500
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/** QIB7322 AHB locations */
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#define QIB7322_AHB_LOC_ADDRESS( _location ) ( (_location) & 0xffff )
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#define QIB7322_AHB_LOC_TARGET( _location ) ( (_location) >> 16 )
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#define QIB7322_AHB_CHAN_0 0
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#define QIB7322_AHB_CHAN_1 1
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#define QIB7322_AHB_PLL 2
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#define QIB7322_AHB_CHAN_2 3
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#define QIB7322_AHB_CHAN_3 4
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#define QIB7322_AHB_SUBSYS 5
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#define QIB7322_AHB_CHAN( _channel ) ( (_channel) + ( (_channel) >> 1 ) )
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#define QIB7322_AHB_TARGET_0 2
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#define QIB7322_AHB_TARGET_1 3
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#define QIB7322_AHB_TARGET( _port ) ( (_port) + 2 )
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#define QIB7322_AHB_LOCATION( _port, _channel, _register ) \
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( ( QIB7322_AHB_TARGET(_port) << 16 ) | \
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( QIB7322_AHB_CHAN(_channel) << 7 ) | \
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( (_register) << 1 ) )
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/** QIB7322 link states */
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enum qib7322_link_state {
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QIB7322_LINK_STATE_DOWN = 0,
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QIB7322_LINK_STATE_INIT = 1,
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QIB7322_LINK_STATE_ARM = 2,
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QIB7322_LINK_STATE_ACTIVE = 3,
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QIB7322_LINK_STATE_ACT_DEFER = 4,
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};
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/** Maximum time to wait for link state changes, in us */
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#define QIB7322_LINK_STATE_MAX_WAIT_US 20
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#endif /* _QIB7322_H */
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