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[sfc] Add driver for Solarflare SFC8XXX adapters 

Signed-off-by: Martin Habets <mhabets@solarflare.com>
Modified-by: Michael Brown <mcb30@ipxe.org>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Martin Habets 2017-04-07 10:46:15 +01:00 committed by Michael Brown
parent ffb5fe4ced
commit f3788fa837
11 changed files with 5605 additions and 0 deletions
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1
src/Makefile
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@ -78,6 +78,7 @@ SRCDIRS += drivers/net/ath/ath9k
SRCDIRS += drivers/net/vxge
SRCDIRS += drivers/net/efi
SRCDIRS += drivers/net/tg3
SRCDIRS += drivers/net/sfc
SRCDIRS += drivers/block
SRCDIRS += drivers/nvs
SRCDIRS += drivers/bitbash

364
src/drivers/net/sfc/ef10_regs.h Normal file
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@ -0,0 +1,364 @@
/****************************************************************************
*
* Driver for Solarflare network controllers and boards
* Copyright 2012-2017 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*/
#ifndef EFX_EF10_REGS_H
#define EFX_EF10_REGS_H
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
/** \file ef10_regs.h
* EF10 hardware architecture definitions
*
* EF10 hardware architecture definitions have a name prefix following
* the format:
*
* E<type>_<min-rev><max-rev>_
*
* The following <type> strings are used:
*
* MMIO register Host memory structure
* Address R
* Bitfield RF SF
* Enumerator FE SE
*
* <min-rev> is the first revision to which the definition applies:
*
* D: Huntington A0
*
* If the definition has been changed or removed in later revisions
* then <max-rev> is the last revision to which the definition applies;
* otherwise it is "Z".
*/
/**************************************************************************
*
* EF10 registers and descriptors
*
**************************************************************************
*/
/* BIU_HW_REV_ID_REG: */
#define ER_DZ_BIU_HW_REV_ID 0x00000000
#define ERF_DZ_HW_REV_ID_LBN 0
#define ERF_DZ_HW_REV_ID_WIDTH 32
/* BIU_MC_SFT_STATUS_REG: */
#define ER_DZ_BIU_MC_SFT_STATUS 0x00000010
#define ER_DZ_BIU_MC_SFT_STATUS_STEP 4
#define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8
#define ERF_DZ_MC_SFT_STATUS_LBN 0
#define ERF_DZ_MC_SFT_STATUS_WIDTH 32
/* BIU_INT_ISR_REG: */
#define ER_DZ_BIU_INT_ISR 0x00000090
#define ERF_DZ_ISR_REG_LBN 0
#define ERF_DZ_ISR_REG_WIDTH 32
/* MC_DB_LWRD_REG: */
#define ER_DZ_MC_DB_LWRD 0x00000200
#define ERF_DZ_MC_DOORBELL_L_LBN 0
#define ERF_DZ_MC_DOORBELL_L_WIDTH 32
/* MC_DB_HWRD_REG: */
#define ER_DZ_MC_DB_HWRD 0x00000204
#define ERF_DZ_MC_DOORBELL_H_LBN 0
#define ERF_DZ_MC_DOORBELL_H_WIDTH 32
/* EVQ_RPTR_REG: */
#define ER_DZ_EVQ_RPTR 0x00000400
#define ER_DZ_EVQ_RPTR_STEP 8192
#define ER_DZ_EVQ_RPTR_ROWS 2048
#define ERF_DZ_EVQ_RPTR_VLD_LBN 15
#define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
#define ERF_DZ_EVQ_RPTR_LBN 0
#define ERF_DZ_EVQ_RPTR_WIDTH 15
/* EVQ_TMR_REG: */
#define ER_DZ_EVQ_TMR 0x00000420
#define ER_DZ_EVQ_TMR_STEP 8192
#define ER_DZ_EVQ_TMR_ROWS 2048
#define ERF_DZ_TC_TIMER_MODE_LBN 14
#define ERF_DZ_TC_TIMER_MODE_WIDTH 2
#define ERF_DZ_TC_TIMER_VAL_LBN 0
#define ERF_DZ_TC_TIMER_VAL_WIDTH 14
/* RX_DESC_UPD_REG: */
#define ER_DZ_RX_DESC_UPD 0x00000830
#define ER_DZ_RX_DESC_UPD_STEP 8192
#define ER_DZ_RX_DESC_UPD_ROWS 2048
#define ERF_DZ_RX_DESC_WPTR_LBN 0
#define ERF_DZ_RX_DESC_WPTR_WIDTH 12
/* TX_DESC_UPD_REG: */
#define ER_DZ_TX_DESC_UPD 0x00000a10
#define ER_DZ_TX_DESC_UPD_STEP 8192
#define ER_DZ_TX_DESC_UPD_ROWS 2048
#define ERF_DZ_RSVD_LBN 76
#define ERF_DZ_RSVD_WIDTH 20
#define ERF_DZ_TX_DESC_WPTR_LBN 64
#define ERF_DZ_TX_DESC_WPTR_WIDTH 12
#define ERF_DZ_TX_DESC_HWORD_LBN 32
#define ERF_DZ_TX_DESC_HWORD_WIDTH 32
#define ERF_DZ_TX_DESC_LWORD_LBN 0
#define ERF_DZ_TX_DESC_LWORD_WIDTH 32
/* DRIVER_EV */
#define ESF_DZ_DRV_CODE_LBN 60
#define ESF_DZ_DRV_CODE_WIDTH 4
#define ESF_DZ_DRV_SUB_CODE_LBN 56
#define ESF_DZ_DRV_SUB_CODE_WIDTH 4
#define ESE_DZ_DRV_TIMER_EV 3
#define ESE_DZ_DRV_START_UP_EV 2
#define ESE_DZ_DRV_WAKE_UP_EV 1
#define ESF_DZ_DRV_SUB_DATA_LBN 0
#define ESF_DZ_DRV_SUB_DATA_WIDTH 56
#define ESF_DZ_DRV_EVQ_ID_LBN 0
#define ESF_DZ_DRV_EVQ_ID_WIDTH 14
#define ESF_DZ_DRV_TMR_ID_LBN 0
#define ESF_DZ_DRV_TMR_ID_WIDTH 14
/* EVENT_ENTRY */
#define ESF_DZ_EV_CODE_LBN 60
#define ESF_DZ_EV_CODE_WIDTH 4
#define ESE_DZ_EV_CODE_MCDI_EV 12
#define ESE_DZ_EV_CODE_DRIVER_EV 5
#define ESE_DZ_EV_CODE_TX_EV 2
#define ESE_DZ_EV_CODE_RX_EV 0
#define ESE_DZ_OTHER other
#define ESF_DZ_EV_DATA_LBN 0
#define ESF_DZ_EV_DATA_WIDTH 60
/* MC_EVENT */
#define ESF_DZ_MC_CODE_LBN 60
#define ESF_DZ_MC_CODE_WIDTH 4
#define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59
#define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1
#define ESF_DZ_MC_DROP_EVENT_LBN 58
#define ESF_DZ_MC_DROP_EVENT_WIDTH 1
#define ESF_DZ_MC_SOFT_LBN 0
#define ESF_DZ_MC_SOFT_WIDTH 58
/* RX_EVENT */
#define ESF_DZ_RX_CODE_LBN 60
#define ESF_DZ_RX_CODE_WIDTH 4
#define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59
#define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1
#define ESF_DZ_RX_DROP_EVENT_LBN 58
#define ESF_DZ_RX_DROP_EVENT_WIDTH 1
#define ESF_DZ_RX_EV_RSVD2_LBN 54
#define ESF_DZ_RX_EV_RSVD2_WIDTH 4
#define ESF_DZ_RX_EV_SOFT2_LBN 52
#define ESF_DZ_RX_EV_SOFT2_WIDTH 2
#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
#define ESF_DZ_RX_L4_CLASS_LBN 45
#define ESF_DZ_RX_L4_CLASS_WIDTH 3
#define ESE_DZ_L4_CLASS_RSVD7 7
#define ESE_DZ_L4_CLASS_RSVD6 6
#define ESE_DZ_L4_CLASS_RSVD5 5
#define ESE_DZ_L4_CLASS_RSVD4 4
#define ESE_DZ_L4_CLASS_RSVD3 3
#define ESE_DZ_L4_CLASS_UDP 2
#define ESE_DZ_L4_CLASS_TCP 1
#define ESE_DZ_L4_CLASS_UNKNOWN 0
#define ESF_DZ_RX_L3_CLASS_LBN 42
#define ESF_DZ_RX_L3_CLASS_WIDTH 3
#define ESE_DZ_L3_CLASS_RSVD7 7
#define ESE_DZ_L3_CLASS_IP6_FRAG 6
#define ESE_DZ_L3_CLASS_ARP 5
#define ESE_DZ_L3_CLASS_IP4_FRAG 4
#define ESE_DZ_L3_CLASS_FCOE 3
#define ESE_DZ_L3_CLASS_IP6 2
#define ESE_DZ_L3_CLASS_IP4 1
#define ESE_DZ_L3_CLASS_UNKNOWN 0
#define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39
#define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3
#define ESE_DZ_ETH_TAG_CLASS_RSVD7 7
#define ESE_DZ_ETH_TAG_CLASS_RSVD6 6
#define ESE_DZ_ETH_TAG_CLASS_RSVD5 5
#define ESE_DZ_ETH_TAG_CLASS_RSVD4 4
#define ESE_DZ_ETH_TAG_CLASS_RSVD3 3
#define ESE_DZ_ETH_TAG_CLASS_VLAN2 2
#define ESE_DZ_ETH_TAG_CLASS_VLAN1 1
#define ESE_DZ_ETH_TAG_CLASS_NONE 0
#define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36
#define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3
#define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2
#define ESE_DZ_ETH_BASE_CLASS_LLC 1
#define ESE_DZ_ETH_BASE_CLASS_ETH2 0
#define ESF_DZ_RX_MAC_CLASS_LBN 35
#define ESF_DZ_RX_MAC_CLASS_WIDTH 1
#define ESE_DZ_MAC_CLASS_MCAST 1
#define ESE_DZ_MAC_CLASS_UCAST 0
#define ESF_DZ_RX_EV_SOFT1_LBN 32
#define ESF_DZ_RX_EV_SOFT1_WIDTH 3
#define ESF_DZ_RX_EV_RSVD1_LBN 31
#define ESF_DZ_RX_EV_RSVD1_WIDTH 1
#define ESF_DZ_RX_ABORT_LBN 30
#define ESF_DZ_RX_ABORT_WIDTH 1
#define ESF_DZ_RX_ECC_ERR_LBN 29
#define ESF_DZ_RX_ECC_ERR_WIDTH 1
#define ESF_DZ_RX_CRC1_ERR_LBN 28
#define ESF_DZ_RX_CRC1_ERR_WIDTH 1
#define ESF_DZ_RX_CRC0_ERR_LBN 27
#define ESF_DZ_RX_CRC0_ERR_WIDTH 1
#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26
#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1
#define ESF_DZ_RX_IPCKSUM_ERR_LBN 25
#define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1
#define ESF_DZ_RX_ECRC_ERR_LBN 24
#define ESF_DZ_RX_ECRC_ERR_WIDTH 1
#define ESF_DZ_RX_QLABEL_LBN 16
#define ESF_DZ_RX_QLABEL_WIDTH 5
#define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15
#define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1
#define ESF_DZ_RX_CONT_LBN 14
#define ESF_DZ_RX_CONT_WIDTH 1
#define ESF_DZ_RX_BYTES_LBN 0
#define ESF_DZ_RX_BYTES_WIDTH 14
/* RX_KER_DESC */
#define ESF_DZ_RX_KER_RESERVED_LBN 62
#define ESF_DZ_RX_KER_RESERVED_WIDTH 2
#define ESF_DZ_RX_KER_BYTE_CNT_LBN 48
#define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14
#define ESF_DZ_RX_KER_BUF_ADDR_LBN 0
#define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48
/* TX_CSUM_TSTAMP_DESC */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
#define ESF_DZ_TX_OPTION_TYPE_LBN 60
#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
#define ESE_DZ_TX_OPTION_DESC_TSO 7
#define ESE_DZ_TX_OPTION_DESC_VLAN 6
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESF_DZ_TX_TIMESTAMP_LBN 5
#define ESF_DZ_TX_TIMESTAMP_WIDTH 1
#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
#define ESE_DZ_TX_OPTION_CRC_FCOE 1
#define ESE_DZ_TX_OPTION_CRC_OFF 0
#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
/* TX_EVENT */
#define ESF_DZ_TX_CODE_LBN 60
#define ESF_DZ_TX_CODE_WIDTH 4
#define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59
#define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1
#define ESF_DZ_TX_DROP_EVENT_LBN 58
#define ESF_DZ_TX_DROP_EVENT_WIDTH 1
#define ESF_DZ_TX_EV_RSVD_LBN 48
#define ESF_DZ_TX_EV_RSVD_WIDTH 10
#define ESF_DZ_TX_SOFT2_LBN 32
#define ESF_DZ_TX_SOFT2_WIDTH 16
#define ESF_DZ_TX_CAN_MERGE_LBN 31
#define ESF_DZ_TX_CAN_MERGE_WIDTH 1
#define ESF_DZ_TX_SOFT1_LBN 24
#define ESF_DZ_TX_SOFT1_WIDTH 7
#define ESF_DZ_TX_QLABEL_LBN 16
#define ESF_DZ_TX_QLABEL_WIDTH 5
#define ESF_DZ_TX_DESCR_INDX_LBN 0
#define ESF_DZ_TX_DESCR_INDX_WIDTH 16
/* TX_KER_DESC */
#define ESF_DZ_TX_KER_TYPE_LBN 63
#define ESF_DZ_TX_KER_TYPE_WIDTH 1
#define ESF_DZ_TX_KER_CONT_LBN 62
#define ESF_DZ_TX_KER_CONT_WIDTH 1
#define ESF_DZ_TX_KER_BYTE_CNT_LBN 48
#define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14
#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0
#define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
/* TX_PIO_DESC */
#define ESF_DZ_TX_PIO_TYPE_LBN 63
#define ESF_DZ_TX_PIO_TYPE_WIDTH 1
#define ESF_DZ_TX_PIO_OPT_LBN 60
#define ESF_DZ_TX_PIO_OPT_WIDTH 3
#define ESF_DZ_TX_PIO_CONT_LBN 59
#define ESF_DZ_TX_PIO_CONT_WIDTH 1
#define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32
#define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12
#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
/* TX_TSO_DESC */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
#define ESF_DZ_TX_OPTION_TYPE_LBN 60
#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
#define ESE_DZ_TX_OPTION_DESC_TSO 7
#define ESE_DZ_TX_OPTION_DESC_VLAN 6
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
#define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8
#define ESF_DZ_TX_TSO_IP_ID_LBN 32
#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
/*************************************************************************/
/* TX_DESC_UPD_REG: Transmit descriptor update register.
* We may write just one dword of these registers.
*/
#define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4)
#define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32)
#define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH
/* The workaround for bug 35388 requires multiplexing writes through
* the TX_DESC_UPD_DWORD address.
* TX_DESC_UPD: 0ppppppppppp (bit 11 lost)
* EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits)
* EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost)
*/
#define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD
#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8
#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4
#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8
#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9
#define ERF_DD_EVQ_IND_RPTR_LBN 0
#define ERF_DD_EVQ_IND_RPTR_WIDTH 8
#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10
#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2
#define EFE_DD_EVQ_IND_TIMER_FLAGS 3
#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8
#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2
#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0
#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8
/* TX_PIOBUF
* PIO buffer aperture (paged)
*/
#define ER_DZ_TX_PIOBUF 4096
#define ER_DZ_TX_PIOBUF_SIZE 2048
/* RX packet prefix */
#define ES_DZ_RX_PREFIX_HASH_OFST 0
#define ES_DZ_RX_PREFIX_VLAN1_OFST 4
#define ES_DZ_RX_PREFIX_VLAN2_OFST 6
#define ES_DZ_RX_PREFIX_PKTLEN_OFST 8
#define ES_DZ_RX_PREFIX_TSTAMP_OFST 10
#define ES_DZ_RX_PREFIX_SIZE 14
#endif /* EFX_EF10_REGS_H */

555
src/drivers/net/sfc/efx_bitfield.h Normal file
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@ -0,0 +1,555 @@
/****************************************************************************
*
* Driver for Solarflare network controllers and boards
* Copyright 2005-2006 Fen Systems Ltd.
* Copyright 2006-2017 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*/
#ifndef EFX_BITFIELD_H
#define EFX_BITFIELD_H
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#include <byteswap.h>
/** \file efx_bitfield.h
* Efx bitfield access
*
* Efx NICs make extensive use of bitfields up to 128 bits
* wide. Since there is no native 128-bit datatype on most systems,
* and since 64-bit datatypes are inefficient on 32-bit systems and
* vice versa, we wrap accesses in a way that uses the most efficient
* datatype.
*
* The NICs are PCI devices and therefore little-endian. Since most
* of the quantities that we deal with are DMAed to/from host memory,
* we define our datatypes (efx_oword_t, efx_qword_t and
* efx_dword_t) to be little-endian.
*/
/* Lowest bit numbers and widths */
#define EFX_DUMMY_FIELD_LBN 0
#define EFX_DUMMY_FIELD_WIDTH 0
#define EFX_WORD_0_LBN 0
#define EFX_WORD_0_WIDTH 16
#define EFX_WORD_1_LBN 16
#define EFX_WORD_1_WIDTH 16
#define EFX_DWORD_0_LBN 0
#define EFX_DWORD_0_WIDTH 32
#define EFX_DWORD_1_LBN 32
#define EFX_DWORD_1_WIDTH 32
#define EFX_DWORD_2_LBN 64
#define EFX_DWORD_2_WIDTH 32
#define EFX_DWORD_3_LBN 96
#define EFX_DWORD_3_WIDTH 32
#define EFX_QWORD_0_LBN 0
#define EFX_QWORD_0_WIDTH 64
/* Specified attribute (e.g. LBN) of the specified field */
#define EFX_VAL(field, attribute) field ## _ ## attribute
/* Low bit number of the specified field */
#define EFX_LOW_BIT(field) EFX_VAL(field, LBN)
/* Bit width of the specified field */
#define EFX_WIDTH(field) EFX_VAL(field, WIDTH)
/* High bit number of the specified field */
#define EFX_HIGH_BIT(field) (EFX_LOW_BIT(field) + EFX_WIDTH(field) - 1)
/* Mask equal in width to the specified field.
*
* For example, a field with width 5 would have a mask of 0x1f.
*
* The maximum width mask that can be generated is 64 bits.
*/
#define EFX_MASK64(width) \
((width) == 64 ? ~((u64) 0) : \
(((((u64) 1) << (width))) - 1))
/* Mask equal in width to the specified field.
*
* For example, a field with width 5 would have a mask of 0x1f.
*
* The maximum width mask that can be generated is 32 bits. Use
* EFX_MASK64 for higher width fields.
*/
#define EFX_MASK32(width) \
((width) == 32 ? ~((u32) 0) : \
(((((u32) 1) << (width))) - 1))
/** A doubleword (4 byte) datatype - little-endian in HW */
typedef union efx_dword {
__le32 u32[1];
} efx_dword_t;
/** A quadword (8 byte) datatype - little-endian in HW */
typedef union efx_qword {
__le64 u64[1];
__le32 u32[2];
efx_dword_t dword[2];
} efx_qword_t;
/** An octword (eight-word, so 16 byte) datatype - little-endian in HW */
typedef union efx_oword {
__le64 u64[2];
efx_qword_t qword[2];
__le32 u32[4];
efx_dword_t dword[4];
} efx_oword_t;
/* Format string and value expanders for printk */
#define EFX_DWORD_FMT "%08x"
#define EFX_QWORD_FMT "%08x:%08x"
#define EFX_OWORD_FMT "%08x:%08x:%08x:%08x"
#define EFX_DWORD_VAL(dword) \
((unsigned int) le32_to_cpu((dword).u32[0]))
#define EFX_QWORD_VAL(qword) \
((unsigned int) le32_to_cpu((qword).u32[1])), \
((unsigned int) le32_to_cpu((qword).u32[0]))
#define EFX_OWORD_VAL(oword) \
((unsigned int) le32_to_cpu((oword).u32[3])), \
((unsigned int) le32_to_cpu((oword).u32[2])), \
((unsigned int) le32_to_cpu((oword).u32[1])), \
((unsigned int) le32_to_cpu((oword).u32[0]))
/*
* Extract bit field portion [low,high) from the native-endian element
* which contains bits [min,max).
*
* For example, suppose "element" represents the high 32 bits of a
* 64-bit value, and we wish to extract the bits belonging to the bit
* field occupying bits 28-45 of this 64-bit value.
*
* Then EFX_EXTRACT ( element, 32, 63, 28, 45 ) would give
*
* ( element ) << 4
*
* The result will contain the relevant bits filled in in the range
* [0,high-low), with garbage in bits [high-low+1,...).
*/
#define EFX_EXTRACT_NATIVE(native_element, min, max, low, high) \
((low) > (max) || (high) < (min) ? 0 : \
(low) > (min) ? \
(native_element) >> ((low) - (min)) : \
(native_element) << ((min) - (low)))
/*
* Extract bit field portion [low,high) from the 64-bit little-endian
* element which contains bits [min,max)
*/
#define EFX_EXTRACT64(element, min, max, low, high) \
EFX_EXTRACT_NATIVE(le64_to_cpu(element), min, max, low, high)
/*
* Extract bit field portion [low,high) from the 32-bit little-endian
* element which contains bits [min,max)
*/
#define EFX_EXTRACT32(element, min, max, low, high) \
EFX_EXTRACT_NATIVE(le32_to_cpu(element), min, max, low, high)
#define EFX_EXTRACT_OWORD64(oword, low, high) \
((EFX_EXTRACT64((oword).u64[0], 0, 63, low, high) | \
EFX_EXTRACT64((oword).u64[1], 64, 127, low, high)) & \
EFX_MASK64((high) + 1 - (low)))
#define EFX_EXTRACT_QWORD64(qword, low, high) \
(EFX_EXTRACT64((qword).u64[0], 0, 63, low, high) & \
EFX_MASK64((high) + 1 - (low)))
#define EFX_EXTRACT_OWORD32(oword, low, high) \
((EFX_EXTRACT32((oword).u32[0], 0, 31, low, high) | \
EFX_EXTRACT32((oword).u32[1], 32, 63, low, high) | \
EFX_EXTRACT32((oword).u32[2], 64, 95, low, high) | \
EFX_EXTRACT32((oword).u32[3], 96, 127, low, high)) & \
EFX_MASK32((high) + 1 - (low)))
#define EFX_EXTRACT_QWORD32(qword, low, high) \
((EFX_EXTRACT32((qword).u32[0], 0, 31, low, high) | \
EFX_EXTRACT32((qword).u32[1], 32, 63, low, high)) & \
EFX_MASK32((high) + 1 - (low)))
#define EFX_EXTRACT_DWORD(dword, low, high) \
(EFX_EXTRACT32((dword).u32[0], 0, 31, low, high) & \
EFX_MASK32((high) + 1 - (low)))
#define EFX_OWORD_FIELD64(oword, field) \
EFX_EXTRACT_OWORD64(oword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field))
#define EFX_QWORD_FIELD64(qword, field) \
EFX_EXTRACT_QWORD64(qword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field))
#define EFX_OWORD_FIELD32(oword, field) \
EFX_EXTRACT_OWORD32(oword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field))
#define EFX_QWORD_FIELD32(qword, field) \
EFX_EXTRACT_QWORD32(qword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field))
#define EFX_DWORD_FIELD(dword, field) \
EFX_EXTRACT_DWORD(dword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field))
#define EFX_OWORD_IS_ZERO64(oword) \
(((oword).u64[0] | (oword).u64[1]) == (__force __le64) 0)
#define EFX_QWORD_IS_ZERO64(qword) \
(((qword).u64[0]) == (__force __le64) 0)
#define EFX_OWORD_IS_ZERO32(oword) \
(((oword).u32[0] | (oword).u32[1] | (oword).u32[2] | (oword).u32[3]) \
== (__force __le32) 0)
#define EFX_QWORD_IS_ZERO32(qword) \
(((qword).u32[0] | (qword).u32[1]) == (__force __le32) 0)
#define EFX_DWORD_IS_ZERO(dword) \
(((dword).u32[0]) == (__force __le32) 0)
#define EFX_OWORD_IS_ALL_ONES64(oword) \
(((oword).u64[0] & (oword).u64[1]) == ~((__force __le64) 0))
#define EFX_QWORD_IS_ALL_ONES64(qword) \
((qword).u64[0] == ~((__force __le64) 0))
#define EFX_OWORD_IS_ALL_ONES32(oword) \
(((oword).u32[0] & (oword).u32[1] & (oword).u32[2] & (oword).u32[3]) \
== ~((__force __le32) 0))
#define EFX_QWORD_IS_ALL_ONES32(qword) \
(((qword).u32[0] & (qword).u32[1]) == ~((__force __le32) 0))
#define EFX_DWORD_IS_ALL_ONES(dword) \
((dword).u32[0] == ~((__force __le32) 0))
#if BITS_PER_LONG == 64
#define EFX_OWORD_FIELD EFX_OWORD_FIELD64
#define EFX_QWORD_FIELD EFX_QWORD_FIELD64
#define EFX_OWORD_IS_ZERO EFX_OWORD_IS_ZERO64
#define EFX_QWORD_IS_ZERO EFX_QWORD_IS_ZERO64
#define EFX_OWORD_IS_ALL_ONES EFX_OWORD_IS_ALL_ONES64
#define EFX_QWORD_IS_ALL_ONES EFX_QWORD_IS_ALL_ONES64
#else
#define EFX_OWORD_FIELD EFX_OWORD_FIELD32
#define EFX_QWORD_FIELD EFX_QWORD_FIELD32
#define EFX_OWORD_IS_ZERO EFX_OWORD_IS_ZERO32
#define EFX_QWORD_IS_ZERO EFX_QWORD_IS_ZERO32
#define EFX_OWORD_IS_ALL_ONES EFX_OWORD_IS_ALL_ONES32
#define EFX_QWORD_IS_ALL_ONES EFX_QWORD_IS_ALL_ONES32
#endif
/*
* Construct bit field portion
*
* Creates the portion of the bit field [low,high) that lies within
* the range [min,max).
*/
#define EFX_INSERT_NATIVE64(min, max, low, high, value) \
(((low > max) || (high < min)) ? 0 : \
((low > min) ? \
(((u64) (value)) << (low - min)) : \
(((u64) (value)) >> (min - low))))
#define EFX_INSERT_NATIVE32(min, max, low, high, value) \
(((low > max) || (high < min)) ? 0 : \
((low > min) ? \
(((u32) (value)) << (low - min)) : \
(((u32) (value)) >> (min - low))))
#define EFX_INSERT_NATIVE(min, max, low, high, value) \
((((max - min) >= 32) || ((high - low) >= 32)) ? \
EFX_INSERT_NATIVE64(min, max, low, high, value) : \
EFX_INSERT_NATIVE32(min, max, low, high, value))
/*
* Construct bit field portion
*
* Creates the portion of the named bit field that lies within the
* range [min,max).
*/
#define EFX_INSERT_FIELD_NATIVE(min, max, field, value) \
EFX_INSERT_NATIVE(min, max, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field), value)
/*
* Construct bit field
*
* Creates the portion of the named bit fields that lie within the
* range [min,max).
*/
#define EFX_INSERT_FIELDS_NATIVE(min, max, \
field1, value1, \
field2, value2, \
field3, value3, \
field4, value4, \
field5, value5, \
field6, value6, \
field7, value7, \
field8, value8, \
field9, value9, \
field10, value10) \
(EFX_INSERT_FIELD_NATIVE((min), (max), field1, (value1)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field2, (value2)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field3, (value3)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field4, (value4)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field5, (value5)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field6, (value6)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field7, (value7)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field8, (value8)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field9, (value9)) | \
EFX_INSERT_FIELD_NATIVE((min), (max), field10, (value10)))
#define EFX_INSERT_FIELDS64(...) \
cpu_to_le64(EFX_INSERT_FIELDS_NATIVE(__VA_ARGS__))
#define EFX_INSERT_FIELDS32(...) \
cpu_to_le32(EFX_INSERT_FIELDS_NATIVE(__VA_ARGS__))
#define EFX_POPULATE_OWORD64(oword, ...) do { \
(oword).u64[0] = EFX_INSERT_FIELDS64(0, 63, __VA_ARGS__); \
(oword).u64[1] = EFX_INSERT_FIELDS64(64, 127, __VA_ARGS__); \
} while (0)
#define EFX_POPULATE_QWORD64(qword, ...) do { \
(qword).u64[0] = EFX_INSERT_FIELDS64(0, 63, __VA_ARGS__); \
} while (0)
#define EFX_POPULATE_OWORD32(oword, ...) do { \
(oword).u32[0] = EFX_INSERT_FIELDS32(0, 31, __VA_ARGS__); \
(oword).u32[1] = EFX_INSERT_FIELDS32(32, 63, __VA_ARGS__); \
(oword).u32[2] = EFX_INSERT_FIELDS32(64, 95, __VA_ARGS__); \
(oword).u32[3] = EFX_INSERT_FIELDS32(96, 127, __VA_ARGS__); \
} while (0)
#define EFX_POPULATE_QWORD32(qword, ...) do { \
(qword).u32[0] = EFX_INSERT_FIELDS32(0, 31, __VA_ARGS__); \
(qword).u32[1] = EFX_INSERT_FIELDS32(32, 63, __VA_ARGS__); \
} while (0)
#define EFX_POPULATE_DWORD(dword, ...) do { \
(dword).u32[0] = EFX_INSERT_FIELDS32(0, 31, __VA_ARGS__); \
} while (0)
#if BITS_PER_LONG == 64
#define EFX_POPULATE_OWORD EFX_POPULATE_OWORD64
#define EFX_POPULATE_QWORD EFX_POPULATE_QWORD64
#else
#define EFX_POPULATE_OWORD EFX_POPULATE_OWORD32
#define EFX_POPULATE_QWORD EFX_POPULATE_QWORD32
#endif
/* Populate an octword field with various numbers of arguments */
#define EFX_POPULATE_OWORD_10 EFX_POPULATE_OWORD
#define EFX_POPULATE_OWORD_9(oword, ...) \
EFX_POPULATE_OWORD_10(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_8(oword, ...) \
EFX_POPULATE_OWORD_9(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_7(oword, ...) \
EFX_POPULATE_OWORD_8(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_6(oword, ...) \
EFX_POPULATE_OWORD_7(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_5(oword, ...) \
EFX_POPULATE_OWORD_6(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_4(oword, ...) \
EFX_POPULATE_OWORD_5(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_3(oword, ...) \
EFX_POPULATE_OWORD_4(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_2(oword, ...) \
EFX_POPULATE_OWORD_3(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_OWORD_1(oword, ...) \
EFX_POPULATE_OWORD_2(oword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_ZERO_OWORD(oword) \
EFX_POPULATE_OWORD_1(oword, EFX_DUMMY_FIELD, 0)
#define EFX_SET_OWORD(oword) \
EFX_POPULATE_OWORD_4(oword, \
EFX_DWORD_0, 0xffffffff, \
EFX_DWORD_1, 0xffffffff, \
EFX_DWORD_2, 0xffffffff, \
EFX_DWORD_3, 0xffffffff)
/* Populate a quadword field with various numbers of arguments */
#define EFX_POPULATE_QWORD_10 EFX_POPULATE_QWORD
#define EFX_POPULATE_QWORD_9(qword, ...) \
EFX_POPULATE_QWORD_10(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_8(qword, ...) \
EFX_POPULATE_QWORD_9(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_7(qword, ...) \
EFX_POPULATE_QWORD_8(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_6(qword, ...) \
EFX_POPULATE_QWORD_7(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_5(qword, ...) \
EFX_POPULATE_QWORD_6(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_4(qword, ...) \
EFX_POPULATE_QWORD_5(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_3(qword, ...) \
EFX_POPULATE_QWORD_4(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_2(qword, ...) \
EFX_POPULATE_QWORD_3(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_QWORD_1(qword, ...) \
EFX_POPULATE_QWORD_2(qword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_ZERO_QWORD(qword) \
EFX_POPULATE_QWORD_1(qword, EFX_DUMMY_FIELD, 0)
#define EFX_SET_QWORD(qword) \
EFX_POPULATE_QWORD_2(qword, \
EFX_DWORD_0, 0xffffffff, \
EFX_DWORD_1, 0xffffffff)
/* Populate a dword field with various numbers of arguments */
#define EFX_POPULATE_DWORD_10 EFX_POPULATE_DWORD
#define EFX_POPULATE_DWORD_9(dword, ...) \
EFX_POPULATE_DWORD_10(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_8(dword, ...) \
EFX_POPULATE_DWORD_9(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_7(dword, ...) \
EFX_POPULATE_DWORD_8(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_6(dword, ...) \
EFX_POPULATE_DWORD_7(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_5(dword, ...) \
EFX_POPULATE_DWORD_6(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_4(dword, ...) \
EFX_POPULATE_DWORD_5(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_3(dword, ...) \
EFX_POPULATE_DWORD_4(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_2(dword, ...) \
EFX_POPULATE_DWORD_3(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_POPULATE_DWORD_1(dword, ...) \
EFX_POPULATE_DWORD_2(dword, EFX_DUMMY_FIELD, 0, __VA_ARGS__)
#define EFX_ZERO_DWORD(dword) \
EFX_POPULATE_DWORD_1(dword, EFX_DUMMY_FIELD, 0)
#define EFX_SET_DWORD(dword) \
EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 0xffffffff)
/*
* Modify a named field within an already-populated structure. Used
* for read-modify-write operations.
*
*/
#define EFX_INVERT_OWORD(oword) do { \
(oword).u64[0] = ~((oword).u64[0]); \
(oword).u64[1] = ~((oword).u64[1]); \
} while (0)
#define EFX_AND_OWORD(oword, from, mask) \
do { \
(oword).u64[0] = (from).u64[0] & (mask).u64[0]; \
(oword).u64[1] = (from).u64[1] & (mask).u64[1]; \
} while (0)
#define EFX_AND_QWORD(qword, from, mask) \
(qword).u64[0] = (from).u64[0] & (mask).u64[0]
#define EFX_OR_OWORD(oword, from, mask) \
do { \
(oword).u64[0] = (from).u64[0] | (mask).u64[0]; \
(oword).u64[1] = (from).u64[1] | (mask).u64[1]; \
} while (0)
#define EFX_INSERT64(min, max, low, high, value) \
cpu_to_le64(EFX_INSERT_NATIVE(min, max, low, high, value))
#define EFX_INSERT32(min, max, low, high, value) \
cpu_to_le32(EFX_INSERT_NATIVE(min, max, low, high, value))
#define EFX_INPLACE_MASK64(min, max, low, high) \
EFX_INSERT64(min, max, low, high, EFX_MASK64((high) + 1 - (low)))
#define EFX_INPLACE_MASK32(min, max, low, high) \
EFX_INSERT32(min, max, low, high, EFX_MASK32((high) + 1 - (low)))
#define EFX_SET_OWORD64(oword, low, high, value) do { \
(oword).u64[0] = (((oword).u64[0] \
& ~EFX_INPLACE_MASK64(0, 63, low, high)) \
| EFX_INSERT64(0, 63, low, high, value)); \
(oword).u64[1] = (((oword).u64[1] \
& ~EFX_INPLACE_MASK64(64, 127, low, high)) \
| EFX_INSERT64(64, 127, low, high, value)); \
} while (0)
#define EFX_SET_QWORD64(qword, low, high, value) do { \
(qword).u64[0] = (((qword).u64[0] \
& ~EFX_INPLACE_MASK64(0, 63, low, high)) \
| EFX_INSERT64(0, 63, low, high, value)); \
} while (0)
#define EFX_SET_OWORD32(oword, low, high, value) do { \
(oword).u32[0] = (((oword).u32[0] \
& ~EFX_INPLACE_MASK32(0, 31, low, high)) \
| EFX_INSERT32(0, 31, low, high, value)); \
(oword).u32[1] = (((oword).u32[1] \
& ~EFX_INPLACE_MASK32(32, 63, low, high)) \
| EFX_INSERT32(32, 63, low, high, value)); \
(oword).u32[2] = (((oword).u32[2] \
& ~EFX_INPLACE_MASK32(64, 95, low, high)) \
| EFX_INSERT32(64, 95, low, high, value)); \
(oword).u32[3] = (((oword).u32[3] \
& ~EFX_INPLACE_MASK32(96, 127, low, high)) \
| EFX_INSERT32(96, 127, low, high, value)); \
} while (0)
#define EFX_SET_QWORD32(qword, low, high, value) do { \
(qword).u32[0] = (((qword).u32[0] \
& ~EFX_INPLACE_MASK32(0, 31, low, high)) \
| EFX_INSERT32(0, 31, low, high, value)); \
(qword).u32[1] = (((qword).u32[1] \
& ~EFX_INPLACE_MASK32(32, 63, low, high)) \
| EFX_INSERT32(32, 63, low, high, value)); \
} while (0)
#define EFX_SET_DWORD32(dword, low, high, value) do { \
(dword).u32[0] = (((dword).u32[0] \
& ~EFX_INPLACE_MASK32(0, 31, low, high)) \
| EFX_INSERT32(0, 31, low, high, value)); \
} while (0)
#define EFX_SET_OWORD_FIELD64(oword, field, value) \
EFX_SET_OWORD64(oword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field), value)
#define EFX_SET_QWORD_FIELD64(qword, field, value) \
EFX_SET_QWORD64(qword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field), value)
#define EFX_SET_OWORD_FIELD32(oword, field, value) \
EFX_SET_OWORD32(oword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field), value)
#define EFX_SET_QWORD_FIELD32(qword, field, value) \
EFX_SET_QWORD32(qword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field), value)
#define EFX_SET_DWORD_FIELD(dword, field, value) \
EFX_SET_DWORD32(dword, EFX_LOW_BIT(field), \
EFX_HIGH_BIT(field), value)
#if BITS_PER_LONG == 64
#define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD64
#define EFX_SET_QWORD_FIELD EFX_SET_QWORD_FIELD64
#else
#define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD32
#define EFX_SET_QWORD_FIELD EFX_SET_QWORD_FIELD32
#endif
/* Used to avoid compiler warnings about shift range exceeding width
* of the data types when dma_addr_t is only 32 bits wide.
*/
#define DMA_ADDR_T_WIDTH (8 * sizeof(dma_addr_t))
#define EFX_DMA_TYPE_WIDTH(width) \
(((width) < DMA_ADDR_T_WIDTH) ? (width) : DMA_ADDR_T_WIDTH)
/* Static initialiser */
#define EFX_OWORD32(a, b, c, d) \
{ .u32 = { cpu_to_le32(a), cpu_to_le32(b), \
cpu_to_le32(c), cpu_to_le32(d) } }
#endif /* EFX_BITFIELD_H */

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/**************************************************************************
*
* Driver datapath common code for Solarflare network cards
*
* Written by Shradha Shah <sshah@solarflare.com>
*
* Copyright Fen Systems Ltd. 2005
* Copyright Level 5 Networks Inc. 2005
* Copyright 2006-2017 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*
***************************************************************************/
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <assert.h>
#include <byteswap.h>
#include <ipxe/io.h>
#include <ipxe/pci.h>
#include <ipxe/malloc.h>
#include <ipxe/iobuf.h>
#include <ipxe/netdevice.h>
#include "efx_common.h"
#include "efx_bitfield.h"
#include "mc_driver_pcol.h"
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
/*******************************************************************************
*
*
* Low-level hardware access
*
*
******************************************************************************/
void
efx_writel(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
{
DBGCIO(efx, "Writing partial register %x with " EFX_DWORD_FMT "\n",
reg, EFX_DWORD_VAL(*value));
_efx_writel(efx, value->u32[0], reg);
}
void
efx_readl(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
{
value->u32[0] = _efx_readl(efx, reg);
DBGCIO(efx, "Read from register %x, got " EFX_DWORD_FMT "\n",
reg, EFX_DWORD_VAL(*value));
}
/*******************************************************************************
*
*
* Inititialization and Close
*
*
******************************************************************************/
void efx_probe(struct net_device *netdev, enum efx_revision revision)
{
struct efx_nic *efx = netdev_priv(netdev);
struct pci_device *pci = container_of(netdev->dev,
struct pci_device, dev);
efx->netdev = netdev;
efx->revision = revision;
/* MMIO bar */
efx->mmio_start = pci_bar_start(pci, PCI_BASE_ADDRESS_2);
efx->mmio_len = pci_bar_size(pci, PCI_BASE_ADDRESS_2);
efx->membase = ioremap(efx->mmio_start, efx->mmio_len);
DBGCP(efx, "BAR of %lx bytes at phys %lx mapped at %p\n",
efx->mmio_len, efx->mmio_start, efx->membase);
/* Enable PCI access */
adjust_pci_device(pci);
}
void efx_remove(struct net_device *netdev)
{
struct efx_nic *efx = netdev_priv(netdev);
iounmap(efx->membase);
efx->membase = NULL;
}

232
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/**************************************************************************
*
* GPL common net driver for Solarflare network cards
*
* Written by Michael Brown <mbrown@fensystems.co.uk>
*
* Copyright Fen Systems Ltd. 2005
* Copyright Level 5 Networks Inc. 2005
* Copyright Solarflare Communications Inc. 2013-2017
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*
***************************************************************************/
#ifndef EFX_COMMON_H
#define EFX_COMMON_H
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#define __packed __attribute__((__packed__))
#define __force /*nothing*/
typedef uint16_t __le16;
typedef uint32_t __le32;
typedef uint64_t __le64;
#define BUILD_BUG_ON_ZERO(e) (sizeof(struct{int: -!!(e); }))
#define BUILD_BUG_ON(e) ((void)BUILD_BUG_ON_ZERO(e))
#include <stdbool.h>
#include <ipxe/io.h>
#include <ipxe/netdevice.h>
#include "efx_bitfield.h"
#include "mcdi.h"
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/**************************************************************************
*
* Hardware data structures and sizing
*
***************************************************************************/
typedef efx_qword_t efx_rx_desc_t;
typedef efx_qword_t efx_tx_desc_t;
typedef efx_qword_t efx_event_t;
#define EFX_BUF_ALIGN 4096
#define EFX_RXD_SIZE 512
#define EFX_RXD_MASK (EFX_RXD_SIZE - 1)
#define EFX_TXD_SIZE 512
#define EFX_TXD_MASK (EFX_TXD_SIZE - 1)
#define EFX_EVQ_SIZE 512
#define EFX_EVQ_MASK (EFX_EVQ_SIZE - 1)
/* There is space for 512 rx descriptors available. This number can be
* anything between 1 and 512 in powers of 2. This value will affect the
* network performance. During a test we were able to push 239 descriptors
* before we ran out of space.
*/
#define EFX_NUM_RX_DESC 64
#define EFX_NUM_RX_DESC_MASK (EFX_NUM_RX_DESC - 1)
/* The packet size is usually 1500 bytes hence we choose 1600 as the buf size,
* which is (1500+metadata)
*/
#define EFX_RX_BUF_SIZE 1600
/* Settings for the state field in efx_nic.
*/
#define EFX_STATE_POLLING 1
typedef unsigned long long dma_addr_t;
/** A buffer table allocation backing a tx dma, rx dma or eventq */
struct efx_special_buffer {
dma_addr_t dma_addr;
int id;
};
/** A transmit queue */
struct efx_tx_queue {
/* The hardware ring */
efx_tx_desc_t *ring;
/* The software ring storing io_buffers. */
struct io_buffer *buf[EFX_TXD_SIZE];
/* The buffer table reservation pushed to hardware */
struct efx_special_buffer entry;
/* Software descriptor write ptr */
unsigned int write_ptr;
/* Hardware descriptor read ptr */
unsigned int read_ptr;
};
/** A receive queue */
struct efx_rx_queue {
/* The hardware ring */
efx_rx_desc_t *ring;
/* The software ring storing io_buffers */
struct io_buffer *buf[EFX_NUM_RX_DESC];
/* The buffer table reservation pushed to hardware */
struct efx_special_buffer entry;
/* Descriptor write ptr, into both the hardware and software rings */
unsigned int write_ptr;
/* Hardware completion ptr */
unsigned int read_ptr;
/* The value of RX_CONT in the previous RX event */
unsigned int rx_cont_prev;
};
/** An event queue */
struct efx_ev_queue {
/* The hardware ring to push to hardware.
* Must be the first entry in the structure.
*/
efx_event_t *ring;
/* The buffer table reservation pushed to hardware */
struct efx_special_buffer entry;
/* Pointers into the ring */
unsigned int read_ptr;
};
/* Hardware revisions */
enum efx_revision {
EFX_HUNTINGTON,
};
/** Hardware access */
struct efx_nic {
struct net_device *netdev;
enum efx_revision revision;
const struct efx_nic_type *type;
int port;
u32 state;
/** Memory and IO base */
void *membase;
unsigned long mmio_start;
unsigned long mmio_len;
/* Buffer table allocation head */
int buffer_head;
/* Queues */
struct efx_rx_queue rxq;
struct efx_tx_queue txq;
struct efx_ev_queue evq;
unsigned int rx_prefix_size;
/** INT_REG_KER */
int int_en;
efx_oword_t int_ker __aligned;
/* Set to true if firmware supports the workaround for bug35388 */
bool workaround_35388;
};
/** Efx device type definition */
struct efx_nic_type {
int (*mcdi_rpc)(struct efx_nic *efx, unsigned int cmd,
const efx_dword_t *inbuf, size_t inlen,
efx_dword_t *outbuf, size_t outlen,
size_t *outlen_actual, bool quiet);
};
extern const struct efx_nic_type hunt_nic_type;
#define EFX_MAC_FRAME_LEN(_mtu) \
(((_mtu) \
+ /* EtherII already included */ \
+ 4 /* FCS */ \
/* No VLAN supported */ \
+ 16 /* bug16772 */ \
+ 7) & ~7)
/*******************************************************************************
*
*
* Hardware API
*
*
******************************************************************************/
static inline void _efx_writel(struct efx_nic *efx, uint32_t value,
unsigned int reg)
{
writel((value), (efx)->membase + (reg));
}
static inline uint32_t _efx_readl(struct efx_nic *efx, unsigned int reg)
{
return readl((efx)->membase + (reg));
}
#define efx_writel_table(efx, value, index, reg) \
efx_writel(efx, value, (reg) + ((index) * reg##_STEP))
#define efx_writel_page(efx, value, index, reg) \
efx_writel(efx, value, (reg) + ((index) * 0x2000))
/* Hardware access */
extern void efx_writel(struct efx_nic *efx, efx_dword_t *value,
unsigned int reg);
extern void efx_readl(struct efx_nic *efx, efx_dword_t *value,
unsigned int reg);
/* Initialisation */
extern void efx_probe(struct net_device *netdev, enum efx_revision rev);
extern void efx_remove(struct net_device *netdev);
#endif /* EFX_COMMON_H */

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/**************************************************************************
*
* Driver datapath for Solarflare network cards
*
* Written by Shradha Shah <sshah@solarflare.com>
*
* Copyright 2012-2017 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*
***************************************************************************/
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <assert.h>
#include <byteswap.h>
#include <ipxe/io.h>
#include <ipxe/pci.h>
#include <ipxe/malloc.h>
#include <ipxe/iobuf.h>
#include <ipxe/netdevice.h>
#include "efx_hunt.h"
#include "efx_bitfield.h"
#include "ef10_regs.h"
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
void efx_hunt_free_special_buffer(void *buf, int bytes)
{
free_dma(buf, bytes);
}
static void *efx_hunt_alloc_special_buffer(int bytes,
struct efx_special_buffer *entry)
{
void *buffer;
dma_addr_t dma_addr;
/* Allocate the buffer, aligned on a buffer address boundary. This
* buffer will be passed into an MC_CMD_INIT_*Q command to setup the
* appropriate type of queue via MCDI.
*/
buffer = malloc_dma(bytes, EFX_BUF_ALIGN);
if (!buffer)
return NULL;
entry->dma_addr = dma_addr = virt_to_bus(buffer);
assert((dma_addr & (EFX_BUF_ALIGN - 1)) == 0);
/* Buffer table entries aren't allocated, so set id to zero */
entry->id = 0;
DBGP("Allocated 0x%x bytes at %p\n", bytes, buffer);
return buffer;
}
/*******************************************************************************
*
*
* TX
*
*
******************************************************************************/
static void
efx_hunt_build_tx_desc(efx_tx_desc_t *txd, struct io_buffer *iob)
{
dma_addr_t dma_addr;
dma_addr = virt_to_bus(iob->data);
EFX_POPULATE_QWORD_4(*txd,
ESF_DZ_TX_KER_TYPE, 0,
ESF_DZ_TX_KER_CONT, 0,
ESF_DZ_TX_KER_BYTE_CNT, iob_len(iob),
ESF_DZ_TX_KER_BUF_ADDR, dma_addr);
}
static void
efx_hunt_notify_tx_desc(struct efx_nic *efx)
{
struct efx_tx_queue *txq = &efx->txq;
int ptr = txq->write_ptr & EFX_TXD_MASK;
efx_dword_t reg;
EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, ptr);
efx_writel_page(efx, &reg, 0, ER_DZ_TX_DESC_UPD_DWORD);
}
int
efx_hunt_transmit(struct net_device *netdev, struct io_buffer *iob)
{
struct efx_nic *efx = netdev_priv(netdev);
struct efx_tx_queue *txq = &efx->txq;
int fill_level, space;
efx_tx_desc_t *txd;
int buf_id;
fill_level = txq->write_ptr - txq->read_ptr;
space = EFX_TXD_SIZE - fill_level - 1;
if (space < 1)
return -ENOBUFS;
/* Save the iobuffer for later completion */
buf_id = txq->write_ptr & EFX_TXD_MASK;
assert(txq->buf[buf_id] == NULL);
txq->buf[buf_id] = iob;
DBGCIO(efx, "tx_buf[%d] for iob %p data %p len %zd\n",
buf_id, iob, iob->data, iob_len(iob));
/* Form the descriptor, and push it to hardware */
txd = txq->ring + buf_id;
efx_hunt_build_tx_desc(txd, iob);
++txq->write_ptr;
efx_hunt_notify_tx_desc(efx);
return 0;
}
static void
efx_hunt_transmit_done(struct efx_nic *efx, int id)
{
struct efx_tx_queue *txq = &efx->txq;
unsigned int read_ptr, stop;
/* Complete all buffers from read_ptr up to and including id */
read_ptr = txq->read_ptr & EFX_TXD_MASK;
stop = (id + 1) & EFX_TXD_MASK;
while (read_ptr != stop) {
struct io_buffer *iob = txq->buf[read_ptr];
assert(iob);
/* Complete the tx buffer */
if (iob)
netdev_tx_complete(efx->netdev, iob);
DBGCIO(efx, "tx_buf[%d] for iob %p done\n", read_ptr, iob);
txq->buf[read_ptr] = NULL;
++txq->read_ptr;
read_ptr = txq->read_ptr & EFX_TXD_MASK;
}
}
int efx_hunt_tx_init(struct net_device *netdev, dma_addr_t *dma_addr)
{
struct efx_nic *efx = netdev_priv(netdev);
struct efx_tx_queue *txq = &efx->txq;
size_t bytes;
/* Allocate hardware transmit queue */
bytes = sizeof(efx_tx_desc_t) * EFX_TXD_SIZE;
txq->ring = efx_hunt_alloc_special_buffer(bytes, &txq->entry);
if (!txq->ring)
return -ENOMEM;
txq->read_ptr = txq->write_ptr = 0;
*dma_addr = txq->entry.dma_addr;
return 0;
}
/*******************************************************************************
*
*
* RX
*
*
******************************************************************************/
static void
efx_hunt_build_rx_desc(efx_rx_desc_t *rxd, struct io_buffer *iob)
{
dma_addr_t dma_addr = virt_to_bus(iob->data);
EFX_POPULATE_QWORD_2(*rxd,
ESF_DZ_RX_KER_BYTE_CNT, EFX_RX_BUF_SIZE,
ESF_DZ_RX_KER_BUF_ADDR, dma_addr);
}
static void
efx_hunt_notify_rx_desc(struct efx_nic *efx)
{
struct efx_rx_queue *rxq = &efx->rxq;
int ptr = rxq->write_ptr & EFX_RXD_MASK;
efx_dword_t reg;
EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, ptr);
efx_writel_page(efx, &reg, 0, ER_DZ_RX_DESC_UPD);
}
static void
efx_hunt_rxq_fill(struct efx_nic *efx)
{
struct efx_rx_queue *rxq = &efx->rxq;
int fill_level = rxq->write_ptr - rxq->read_ptr;
int space = EFX_NUM_RX_DESC - fill_level - 1;
int pushed = 0;
while (space) {
int buf_id = rxq->write_ptr & (EFX_NUM_RX_DESC - 1);
int desc_id = rxq->write_ptr & EFX_RXD_MASK;
struct io_buffer *iob;
efx_rx_desc_t *rxd;
assert(rxq->buf[buf_id] == NULL);
iob = alloc_iob(EFX_RX_BUF_SIZE);
if (!iob)
break;
DBGCP(efx, "pushing rx_buf[%d] iob %p data %p\n",
buf_id, iob, iob->data);
rxq->buf[buf_id] = iob;
rxd = rxq->ring + desc_id;
efx_hunt_build_rx_desc(rxd, iob);
++rxq->write_ptr;
++pushed;
--space;
}
/* Push the ptr to hardware */
if (pushed > 0) {
efx_hunt_notify_rx_desc(efx);
DBGCP(efx, "pushed %d rx buffers to fill level %d\n",
pushed, rxq->write_ptr - rxq->read_ptr);
}
}
static void
efx_hunt_receive(struct efx_nic *efx, unsigned int id, int len, int drop)
{
struct efx_rx_queue *rxq = &efx->rxq;
unsigned int read_ptr = rxq->read_ptr & EFX_RXD_MASK;
unsigned int buf_ptr = rxq->read_ptr & EFX_NUM_RX_DESC_MASK;
struct io_buffer *iob;
/* id is the lower 4 bits of the desc index + 1 in huntington*/
/* hence anding with 15 */
assert((id & 15) == ((read_ptr + (len != 0)) & 15));
/* Pop this rx buffer out of the software ring */
iob = rxq->buf[buf_ptr];
rxq->buf[buf_ptr] = NULL;
DBGCIO(efx, "popping rx_buf[%d] iob %p data %p with %d bytes %s %x\n",
read_ptr, iob, iob->data, len, drop ? "bad" : "ok", drop);
/* Pass the packet up if required */
if (drop)
netdev_rx_err(efx->netdev, iob, EBADMSG);
else {
iob_put(iob, len);
iob_pull(iob, efx->rx_prefix_size);
netdev_rx(efx->netdev, iob);
}
++rxq->read_ptr;
}
int efx_hunt_rx_init(struct net_device *netdev, dma_addr_t *dma_addr)
{
struct efx_nic *efx = netdev_priv(netdev);
struct efx_rx_queue *rxq = &efx->rxq;
size_t bytes;
/* Allocate hardware receive queue */
bytes = sizeof(efx_rx_desc_t) * EFX_RXD_SIZE;
rxq->ring = efx_hunt_alloc_special_buffer(bytes, &rxq->entry);
if (rxq->ring == NULL)
return -ENOMEM;
rxq->read_ptr = rxq->write_ptr = 0;
*dma_addr = rxq->entry.dma_addr;
return 0;
}
/*******************************************************************************
*
*
* Event queues and interrupts
*
*
******************************************************************************/
int efx_hunt_ev_init(struct net_device *netdev, dma_addr_t *dma_addr)
{
struct efx_nic *efx = netdev_priv(netdev);
struct efx_ev_queue *evq = &efx->evq;
size_t bytes;
/* Allocate the hardware event queue */
bytes = sizeof(efx_event_t) * EFX_EVQ_SIZE;
evq->ring = efx_hunt_alloc_special_buffer(bytes, &evq->entry);
if (evq->ring == NULL)
return -ENOMEM;
memset(evq->ring, 0xff, bytes);
evq->read_ptr = 0;
*dma_addr = evq->entry.dma_addr;
return 0;
}
static void
efx_hunt_clear_interrupts(struct efx_nic *efx)
{
efx_dword_t reg;
/* read the ISR */
efx_readl(efx, &reg, ER_DZ_BIU_INT_ISR);
}
/**
* See if an event is present
*
* @v event EFX event structure
* @ret True An event is pending
* @ret False No event is pending
*
* We check both the high and low dword of the event for all ones. We
* wrote all ones when we cleared the event, and no valid event can
* have all ones in either its high or low dwords. This approach is
* robust against reordering.
*
* Note that using a single 64-bit comparison is incorrect; even
* though the CPU read will be atomic, the DMA write may not be.
*/
static inline int
efx_hunt_event_present(efx_event_t *event)
{
return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
EFX_DWORD_IS_ALL_ONES(event->dword[1])));
}
static void
efx_hunt_evq_read_ack(struct efx_nic *efx)
{
struct efx_ev_queue *evq = &efx->evq;
efx_dword_t reg;
if (efx->workaround_35388) {
EFX_POPULATE_DWORD_2(reg, ERF_DD_EVQ_IND_RPTR_FLAGS,
EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
ERF_DD_EVQ_IND_RPTR,
evq->read_ptr >> ERF_DD_EVQ_IND_RPTR_WIDTH);
efx_writel_page(efx, &reg, 0, ER_DD_EVQ_INDIRECT);
EFX_POPULATE_DWORD_2(reg, ERF_DD_EVQ_IND_RPTR_FLAGS,
EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
ERF_DD_EVQ_IND_RPTR, evq->read_ptr &
((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
efx_writel_page(efx, &reg, 0, ER_DD_EVQ_INDIRECT);
} else {
EFX_POPULATE_DWORD_1(reg, ERF_DZ_EVQ_RPTR, evq->read_ptr);
efx_writel_table(efx, &reg, 0, ER_DZ_EVQ_RPTR);
}
}
static unsigned int
efx_hunt_handle_event(struct efx_nic *efx, efx_event_t *evt)
{
struct efx_rx_queue *rxq = &efx->rxq;
int ev_code, desc_ptr, len;
int next_ptr_lbits, packet_drop;
int rx_cont;
/* Decode event */
ev_code = EFX_QWORD_FIELD(*evt, ESF_DZ_EV_CODE);
switch (ev_code) {
case ESE_DZ_EV_CODE_TX_EV:
desc_ptr = EFX_QWORD_FIELD(*evt, ESF_DZ_TX_DESCR_INDX);
efx_hunt_transmit_done(efx, desc_ptr);
break;
case ESE_DZ_EV_CODE_RX_EV:
len = EFX_QWORD_FIELD(*evt, ESF_DZ_RX_BYTES);
next_ptr_lbits = EFX_QWORD_FIELD(*evt, ESF_DZ_RX_DSC_PTR_LBITS);
rx_cont = EFX_QWORD_FIELD(*evt, ESF_DZ_RX_CONT);
/* We don't expect to receive scattered packets, so drop the
* packet if RX_CONT is set on the current or previous event, or
* if len is zero.
*/
packet_drop = (len == 0) | (rx_cont << 1) |
(rxq->rx_cont_prev << 2);
efx_hunt_receive(efx, next_ptr_lbits, len, packet_drop);
rxq->rx_cont_prev = rx_cont;
return 1;
default:
DBGCP(efx, "Unknown event type %d\n", ev_code);
break;
}
return 0;
}
void efx_hunt_poll(struct net_device *netdev)
{
struct efx_nic *efx = netdev_priv(netdev);
struct efx_ev_queue *evq = &efx->evq;
efx_event_t *evt;
int budget = 10;
/* Read the event queue by directly looking for events
* (we don't even bother to read the eventq write ptr)
*/
evt = evq->ring + evq->read_ptr;
while (efx_hunt_event_present(evt) && (budget > 0)) {
DBGCP(efx, "Event at index 0x%x address %p is "
EFX_QWORD_FMT "\n", evq->read_ptr,
evt, EFX_QWORD_VAL(*evt));
budget -= efx_hunt_handle_event(efx, evt);
/* Clear the event */
EFX_SET_QWORD(*evt);
/* Move to the next event. We don't ack the event
* queue until the end
*/
evq->read_ptr = ((evq->read_ptr + 1) & EFX_EVQ_MASK);
evt = evq->ring + evq->read_ptr;
}
/* Push more rx buffers if needed */
efx_hunt_rxq_fill(efx);
/* Clear any pending interrupts */
efx_hunt_clear_interrupts(efx);
/* Ack the event queue if interrupts are enabled */
if (efx->int_en)
efx_hunt_evq_read_ack(efx);
}
void efx_hunt_irq(struct net_device *netdev, int enable)
{
struct efx_nic *efx = netdev_priv(netdev);
efx->int_en = enable;
/* If interrupts are enabled, prime the event queue. Otherwise ack any
* pending interrupts
*/
if (enable)
efx_hunt_evq_read_ack(efx);
else if (efx->netdev->state & NETDEV_OPEN)
efx_hunt_clear_interrupts(efx);
}
/*******************************************************************************
*
*
* Initialization and Close
*
*
******************************************************************************/
int efx_hunt_open(struct net_device *netdev)
{
struct efx_nic *efx = netdev_priv(netdev);
efx_dword_t cmd;
/* Set interrupt moderation to 0*/
EFX_POPULATE_DWORD_2(cmd,
ERF_DZ_TC_TIMER_MODE, 0,
ERF_DZ_TC_TIMER_VAL, 0);
efx_writel_page(efx, &cmd, 0, ER_DZ_EVQ_TMR);
/* Ack the eventq */
if (efx->int_en)
efx_hunt_evq_read_ack(efx);
/* Push receive buffers */
efx_hunt_rxq_fill(efx);
return 0;
}
void efx_hunt_close(struct net_device *netdev)
{
struct efx_nic *efx = netdev_priv(netdev);
struct efx_rx_queue *rxq = &efx->rxq;
struct efx_tx_queue *txq = &efx->txq;
int i;
/* Complete outstanding descriptors */
for (i = 0; i < EFX_NUM_RX_DESC; i++) {
if (rxq->buf[i]) {
free_iob(rxq->buf[i]);
rxq->buf[i] = NULL;
}
}
for (i = 0; i < EFX_TXD_SIZE; i++) {
if (txq->buf[i]) {
netdev_tx_complete(efx->netdev, txq->buf[i]);
txq->buf[i] = NULL;
}
}
/* Clear interrupts */
efx_hunt_clear_interrupts(efx);
}

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/**************************************************************************
*
* GPL net driver for Solarflare network cards
*
* Written by Shradha Shah <sshah@solarflare.com>
*
* Copyright 2012-2017 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*
***************************************************************************/
#ifndef EFX_HUNT_H
#define EFX_HUNT_H
#include "efx_common.h"
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
/**************************************************************************
*
* Hardware data structures and sizing
*
***************************************************************************/
#define EFX_EV_SIZE(_nevs) ((_nevs) * sizeof(efx_qword_t))
#define EFX_EVQ_NBUFS(_nevs) (EFX_EV_SIZE(_nevs) / EFX_BUF_ALIGN)
#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof(efx_qword_t))
#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_ALIGN)
#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof(efx_qword_t))
#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_ALIGN)
/** MCDI request structure */
struct efx_mcdi_req_s {
unsigned int emr_cmd;
efx_dword_t *emr_in_buf;
size_t emr_in_length;
int emr_rc;
efx_dword_t *emr_out_buf;
size_t emr_out_length;
size_t emr_out_length_used;
};
/*******************************************************************************
*
*
* Hardware API
*
*
******************************************************************************/
extern void efx_hunt_free_special_buffer(void *buf, int bytes);
/* Data path entry points */
extern int efx_hunt_transmit(struct net_device *netdev, struct io_buffer *iob);
extern void efx_hunt_poll(struct net_device *netdev);
extern void efx_hunt_irq(struct net_device *netdev, int enable);
/* Initialisation */
extern int efx_hunt_ev_init(struct net_device *netdev, dma_addr_t *dma_addr);
extern int efx_hunt_rx_init(struct net_device *netdev, dma_addr_t *dma_addr);
extern int efx_hunt_tx_init(struct net_device *netdev, dma_addr_t *dma_addr);
extern int efx_hunt_open(struct net_device *netdev);
extern void efx_hunt_close(struct net_device *netdev);
#endif /* EFX_HUNT_H */

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src/drivers/net/sfc/mc_driver_pcol.h Normal file
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src/drivers/net/sfc/mcdi.h Normal file
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@ -0,0 +1,164 @@
/****************************************************************************
* Driver for Solarflare network controllers and boards
*
* Written by Martin Habets <mhabets@solarflare.com>
*
* Copyright 2012-2017 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*/
#ifndef SFC_MCDI_H
#define SFC_MCDI_H
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#ifndef DIV_ROUND_UP
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#endif
#define MCDI_SEQ_MASK 0xf
/* We expect that 16- and 32-bit fields in MCDI requests and responses
* are appropriately aligned, but 64-bit fields are only
* 32-bit-aligned. Also, on Siena we must copy to the MC shared
* memory strictly 32 bits at a time, so add any necessary padding.
*/
#define MCDI_DECLARE_BUF(_name, _len) \
efx_dword_t _name[DIV_ROUND_UP(_len, 4)]
#define MCDI_DECLARE_BUF_OUT_OR_ERR(_name, _len) \
MCDI_DECLARE_BUF(_name, max_t(size_t, _len, 8))
#define _MCDI_PTR(_buf, _offset) \
((u8 *)(_buf) + (_offset))
#define MCDI_PTR(_buf, _field) \
_MCDI_PTR(_buf, MC_CMD_ ## _field ## _OFST)
#define _MCDI_CHECK_ALIGN(_ofst, _align) \
((_ofst) + BUILD_BUG_ON_ZERO((_ofst) & (_align - 1)))
#define _MCDI_DWORD(_buf, _field) \
((_buf) + (_MCDI_CHECK_ALIGN(MC_CMD_ ## _field ## _OFST, 4) >> 2))
#define MCDI_WORD(_buf, _field) \
((u16)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 2) + \
le16_to_cpu(*(__force const __le16 *)MCDI_PTR(_buf, _field)))
#define MCDI_SET_DWORD(_buf, _field, _value) \
EFX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), EFX_DWORD_0, _value)
#define MCDI_DWORD(_buf, _field) \
EFX_DWORD_FIELD(*_MCDI_DWORD(_buf, _field), EFX_DWORD_0)
#define MCDI_POPULATE_DWORD_1(_buf, _field, _name1, _value1) \
EFX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1)
#define MCDI_POPULATE_DWORD_2(_buf, _field, _name1, _value1, \
_name2, _value2) \
EFX_POPULATE_DWORD_2(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1, \
MC_CMD_ ## _name2, _value2)
#define MCDI_POPULATE_DWORD_3(_buf, _field, _name1, _value1, \
_name2, _value2, _name3, _value3) \
EFX_POPULATE_DWORD_3(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1, \
MC_CMD_ ## _name2, _value2, \
MC_CMD_ ## _name3, _value3)
#define MCDI_POPULATE_DWORD_4(_buf, _field, _name1, _value1, \
_name2, _value2, _name3, _value3, \
_name4, _value4) \
EFX_POPULATE_DWORD_4(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1, \
MC_CMD_ ## _name2, _value2, \
MC_CMD_ ## _name3, _value3, \
MC_CMD_ ## _name4, _value4)
#define MCDI_POPULATE_DWORD_5(_buf, _field, _name1, _value1, \
_name2, _value2, _name3, _value3, \
_name4, _value4, _name5, _value5) \
EFX_POPULATE_DWORD_5(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1, \
MC_CMD_ ## _name2, _value2, \
MC_CMD_ ## _name3, _value3, \
MC_CMD_ ## _name4, _value4, \
MC_CMD_ ## _name5, _value5)
#define MCDI_POPULATE_DWORD_6(_buf, _field, _name1, _value1, \
_name2, _value2, _name3, _value3, \
_name4, _value4, _name5, _value5, \
_name6, _value6) \
EFX_POPULATE_DWORD_6(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1, \
MC_CMD_ ## _name2, _value2, \
MC_CMD_ ## _name3, _value3, \
MC_CMD_ ## _name4, _value4, \
MC_CMD_ ## _name5, _value5, \
MC_CMD_ ## _name6, _value6)
#define MCDI_POPULATE_DWORD_7(_buf, _field, _name1, _value1, \
_name2, _value2, _name3, _value3, \
_name4, _value4, _name5, _value5, \
_name6, _value6, _name7, _value7) \
EFX_POPULATE_DWORD_7(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1, \
MC_CMD_ ## _name2, _value2, \
MC_CMD_ ## _name3, _value3, \
MC_CMD_ ## _name4, _value4, \
MC_CMD_ ## _name5, _value5, \
MC_CMD_ ## _name6, _value6, \
MC_CMD_ ## _name7, _value7)
#define MCDI_SET_QWORD(_buf, _field, _value) \
do { \
EFX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[0], \
EFX_DWORD_0, (u32)(_value)); \
EFX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[1], \
EFX_DWORD_0, (u64)(_value) >> 32); \
} while (0)
#define MCDI_QWORD(_buf, _field) \
(EFX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[0], EFX_DWORD_0) | \
(u64)EFX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[1], EFX_DWORD_0) << 32)
#define MCDI_FIELD(_ptr, _type, _field) \
EFX_EXTRACT_DWORD( \
*(efx_dword_t *) \
_MCDI_PTR(_ptr, MC_CMD_ ## _type ## _ ## _field ## _OFST & ~3),\
MC_CMD_ ## _type ## _ ## _field ## _LBN & 0x1f, \
(MC_CMD_ ## _type ## _ ## _field ## _LBN & 0x1f) + \
MC_CMD_ ## _type ## _ ## _field ## _WIDTH - 1)
#define _MCDI_ARRAY_PTR(_buf, _field, _index, _align) \
(_MCDI_PTR(_buf, _MCDI_CHECK_ALIGN(MC_CMD_ ## _field ## _OFST, _align))\
+ (_index) * _MCDI_CHECK_ALIGN(MC_CMD_ ## _field ## _LEN, _align))
#define MCDI_DECLARE_STRUCT_PTR(_name) \
efx_dword_t *_name
#define MCDI_ARRAY_STRUCT_PTR(_buf, _field, _index) \
((efx_dword_t *)_MCDI_ARRAY_PTR(_buf, _field, _index, 4))
#define MCDI_VAR_ARRAY_LEN(_len, _field) \
min_t(size_t, MC_CMD_ ## _field ## _MAXNUM, \
((_len) - MC_CMD_ ## _field ## _OFST) / MC_CMD_ ## _field ## _LEN)
#define MCDI_ARRAY_WORD(_buf, _field, _index) \
(BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 2) + \
le16_to_cpu(*(__force const __le16 *) \
_MCDI_ARRAY_PTR(_buf, _field, _index, 2)))
#define _MCDI_ARRAY_DWORD(_buf, _field, _index) \
(BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 4) + \
(efx_dword_t *)_MCDI_ARRAY_PTR(_buf, _field, _index, 4))
#define MCDI_SET_ARRAY_DWORD(_buf, _field, _index, _value) \
EFX_SET_DWORD_FIELD(*_MCDI_ARRAY_DWORD(_buf, _field, _index), \
EFX_DWORD_0, _value)
#define MCDI_ARRAY_DWORD(_buf, _field, _index) \
EFX_DWORD_FIELD(*_MCDI_ARRAY_DWORD(_buf, _field, _index), EFX_DWORD_0)
#define _MCDI_ARRAY_QWORD(_buf, _field, _index) \
(BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 8) + \
(efx_dword_t *)_MCDI_ARRAY_PTR(_buf, _field, _index, 4))
#define MCDI_SET_ARRAY_QWORD(_buf, _field, _index, _value) \
do { \
EFX_SET_DWORD_FIELD(_MCDI_ARRAY_QWORD(_buf, _field, _index)[0],\
EFX_DWORD_0, (u32)(_value)); \
EFX_SET_DWORD_FIELD(_MCDI_ARRAY_QWORD(_buf, _field, _index)[1],\
EFX_DWORD_0, (u64)(_value) >> 32); \
} while (0)
#define MCDI_ARRAY_FIELD(_buf, _field1, _type, _index, _field2) \
MCDI_FIELD(MCDI_ARRAY_STRUCT_PTR(_buf, _field1, _index), \
_type ## _TYPEDEF, _field2)
#define MCDI_EVENT_FIELD(_ev, _field) \
EFX_QWORD_FIELD(_ev, MCDI_EVENT_ ## _field)
#endif

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src/drivers/net/sfc/sfc_hunt.c Normal file
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src/include/ipxe/errfile.h
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@ -197,6 +197,8 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#define ERRFILE_axge ( ERRFILE_DRIVER | 0x00c10000 )
#define ERRFILE_thunderx ( ERRFILE_DRIVER | 0x00c20000 )
#define ERRFILE_af_packet ( ERRFILE_DRIVER | 0x00c30000 )
#define ERRFILE_sfc_hunt ( ERRFILE_DRIVER | 0x00c40000 )
#define ERRFILE_efx_hunt ( ERRFILE_DRIVER | 0x00c50000 )
#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )