[intel] Add intelx driver for Intel 10 Gigabit Ethernet NICs
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
parent
1dd4e51063
commit
cdca99f068
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/*
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* Copyright (C) 2013 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <stdint.h>
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#include <string.h>
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#include <unistd.h>
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#include <errno.h>
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#include <byteswap.h>
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#include <ipxe/netdevice.h>
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#include <ipxe/ethernet.h>
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#include <ipxe/if_ether.h>
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#include <ipxe/iobuf.h>
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#include <ipxe/malloc.h>
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#include <ipxe/pci.h>
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#include "intelx.h"
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/** @file
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*
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* Intel 10 Gigabit Ethernet network card driver
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*
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*/
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/******************************************************************************
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*
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* MAC address
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*
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******************************************************************************
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*/
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/**
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* Try to fetch initial MAC address
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*
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* @v intel Intel device
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* @v ral0 RAL0 register address
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* @v hw_addr Hardware address to fill in
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* @ret rc Return status code
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*/
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static int intelx_try_fetch_mac ( struct intel_nic *intel, unsigned int ral0,
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uint8_t *hw_addr ) {
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union intel_receive_address mac;
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/* Read current address from RAL0/RAH0 */
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mac.reg.low = cpu_to_le32 ( readl ( intel->regs + ral0 ) );
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mac.reg.high = cpu_to_le32 ( readl ( intel->regs + ral0 +
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( INTELX_RAH0 - INTELX_RAL0 ) ) );
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/* Use current address if valid */
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if ( is_valid_ether_addr ( mac.raw ) ) {
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DBGC ( intel, "INTEL %p has autoloaded MAC address %s at "
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"%#05x\n", intel, eth_ntoa ( mac.raw ), ral0 );
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memcpy ( hw_addr, mac.raw, ETH_ALEN );
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return 0;
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}
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return -ENOENT;
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}
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/**
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* Fetch initial MAC address
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*
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* @v intel Intel device
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* @v hw_addr Hardware address to fill in
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* @ret rc Return status code
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*/
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static int intelx_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
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int rc;
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/* Try to fetch address from INTELX_RAL0 */
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if ( ( rc = intelx_try_fetch_mac ( intel, INTELX_RAL0,
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hw_addr ) ) == 0 ) {
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return 0;
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}
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/* Try to fetch address from INTELX_RAL0_ALT */
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if ( ( rc = intelx_try_fetch_mac ( intel, INTELX_RAL0_ALT,
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hw_addr ) ) == 0 ) {
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return 0;
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}
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DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
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return -ENOENT;
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}
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/******************************************************************************
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*
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* Device reset
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*
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******************************************************************************
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*/
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/**
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* Reset hardware
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*
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* @v intel Intel device
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* @ret rc Return status code
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*/
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static int intelx_reset ( struct intel_nic *intel ) {
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uint32_t ctrl;
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/* Perform a global software reset */
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ctrl = readl ( intel->regs + INTELX_CTRL );
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writel ( ( ctrl | INTELX_CTRL_RST | INTELX_CTRL_LRST ),
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intel->regs + INTELX_CTRL );
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mdelay ( INTELX_RESET_DELAY_MS );
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DBGC ( intel, "INTEL %p reset (ctrl %08x)\n", intel, ctrl );
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return 0;
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}
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/******************************************************************************
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*
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* Link state
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*
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******************************************************************************
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*/
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/**
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* Check link state
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*
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* @v netdev Network device
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*/
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static void intelx_check_link ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t links;
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/* Read link status */
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links = readl ( intel->regs + INTELX_LINKS );
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DBGC ( intel, "INTEL %p link status is %08x\n", intel, links );
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/* Update network device */
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if ( links & INTELX_LINKS_UP ) {
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netdev_link_up ( netdev );
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} else {
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netdev_link_down ( netdev );
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}
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}
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/******************************************************************************
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*
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* Network device interface
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*
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******************************************************************************
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*/
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/**
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* Open network device
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*
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* @v netdev Network device
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* @ret rc Return status code
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*/
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static int intelx_open ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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union intel_receive_address mac;
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uint32_t ral0;
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uint32_t rah0;
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uint32_t dmatxctl;
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uint32_t fctrl;
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uint32_t srrctl;
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uint32_t hlreg0;
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uint32_t maxfrs;
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uint32_t rdrxctl;
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uint32_t rxctrl;
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uint32_t dca_rxctrl;
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int rc;
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/* Create transmit descriptor ring */
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if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
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goto err_create_tx;
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/* Create receive descriptor ring */
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if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
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goto err_create_rx;
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/* Program MAC address */
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memset ( &mac, 0, sizeof ( mac ) );
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memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
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ral0 = le32_to_cpu ( mac.reg.low );
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rah0 = ( le32_to_cpu ( mac.reg.high ) | INTELX_RAH0_AV );
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writel ( ral0, intel->regs + INTELX_RAL0 );
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writel ( rah0, intel->regs + INTELX_RAH0 );
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writel ( ral0, intel->regs + INTELX_RAL0_ALT );
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writel ( rah0, intel->regs + INTELX_RAH0_ALT );
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/* Allocate interrupt vectors */
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writel ( ( INTELX_IVAR_RX0_DEFAULT | INTELX_IVAR_RX0_VALID |
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INTELX_IVAR_TX0_DEFAULT | INTELX_IVAR_TX0_VALID ),
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intel->regs + INTELX_IVAR );
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/* Enable transmitter */
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dmatxctl = readl ( intel->regs + INTELX_DMATXCTL );
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dmatxctl |= INTELX_DMATXCTL_TE;
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writel ( dmatxctl, intel->regs + INTELX_DMATXCTL );
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/* Configure receive filter */
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fctrl = readl ( intel->regs + INTELX_FCTRL );
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fctrl |= ( INTELX_FCTRL_BAM | INTELX_FCTRL_UPE | INTELX_FCTRL_MPE );
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writel ( fctrl, intel->regs + INTELX_FCTRL );
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/* Configure receive buffer sizes */
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srrctl = readl ( intel->regs + INTELX_SRRCTL );
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srrctl &= ~INTELX_SRRCTL_BSIZE_MASK;
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srrctl |= INTELX_SRRCTL_BSIZE_DEFAULT;
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writel ( srrctl, intel->regs + INTELX_SRRCTL );
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/* Configure jumbo frames. Required to allow the extra 4-byte
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* headroom for VLANs, since we don't use the hardware's
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* native VLAN offload.
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*/
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hlreg0 = readl ( intel->regs + INTELX_HLREG0 );
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hlreg0 |= INTELX_HLREG0_JUMBOEN;
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writel ( hlreg0, intel->regs + INTELX_HLREG0 );
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/* Configure frame size */
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maxfrs = readl ( intel->regs + INTELX_MAXFRS );
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maxfrs &= ~INTELX_MAXFRS_MFS_MASK;
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maxfrs |= INTELX_MAXFRS_MFS_DEFAULT;
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writel ( maxfrs, intel->regs + INTELX_MAXFRS );
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/* Configure receive DMA */
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rdrxctl = readl ( intel->regs + INTELX_RDRXCTL );
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rdrxctl |= INTELX_RDRXCTL_SECRC;
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writel ( rdrxctl, intel->regs + INTELX_RDRXCTL );
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/* Clear "must-be-zero" bit for direct cache access (DCA). We
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* leave DCA disabled anyway, but if we do not clear this bit
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* then the received packets contain garbage data.
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*/
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dca_rxctrl = readl ( intel->regs + INTELX_DCA_RXCTRL );
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dca_rxctrl &= ~INTELX_DCA_RXCTRL_MUST_BE_ZERO;
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writel ( dca_rxctrl, intel->regs + INTELX_DCA_RXCTRL );
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/* Enable receiver */
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rxctrl = readl ( intel->regs + INTELX_RXCTRL );
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rxctrl |= INTELX_RXCTRL_RXEN;
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writel ( rxctrl, intel->regs + INTELX_RXCTRL );
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/* Fill receive ring */
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intel_refill_rx ( intel );
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/* Update link state */
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intelx_check_link ( netdev );
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return 0;
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intel_destroy_ring ( intel, &intel->rx );
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err_create_rx:
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intel_destroy_ring ( intel, &intel->tx );
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err_create_tx:
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return rc;
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}
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/**
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* Close network device
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*
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* @v netdev Network device
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*/
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static void intelx_close ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t rxctrl;
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uint32_t dmatxctl;
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/* Disable receiver */
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rxctrl = readl ( intel->regs + INTELX_RXCTRL );
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rxctrl &= ~INTELX_RXCTRL_RXEN;
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writel ( rxctrl, intel->regs + INTELX_RXCTRL );
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/* Disable transmitter */
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dmatxctl = readl ( intel->regs + INTELX_DMATXCTL );
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dmatxctl &= ~INTELX_DMATXCTL_TE;
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writel ( dmatxctl, intel->regs + INTELX_DMATXCTL );
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/* Destroy receive descriptor ring */
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intel_destroy_ring ( intel, &intel->rx );
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/* Discard any unused receive buffers */
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intel_empty_rx ( intel );
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/* Destroy transmit descriptor ring */
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intel_destroy_ring ( intel, &intel->tx );
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/* Reset the NIC, to flush the transmit and receive FIFOs */
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intelx_reset ( intel );
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}
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/**
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* Poll for completed and received packets
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*
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* @v netdev Network device
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*/
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static void intelx_poll ( struct net_device *netdev ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t eicr;
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/* Check for and acknowledge interrupts */
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eicr = readl ( intel->regs + INTELX_EICR );
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if ( ! eicr )
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return;
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/* Poll for TX completions, if applicable */
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if ( eicr & INTELX_EIRQ_TX0 )
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intel_poll_tx ( netdev );
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/* Poll for RX completions, if applicable */
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if ( eicr & ( INTELX_EIRQ_RX0 | INTELX_EIRQ_RXO ) )
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intel_poll_rx ( netdev );
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/* Report receive overruns */
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if ( eicr & INTELX_EIRQ_RXO )
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netdev_rx_err ( netdev, NULL, -ENOBUFS );
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/* Check link state, if applicable */
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if ( eicr & INTELX_EIRQ_LSC )
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intelx_check_link ( netdev );
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/* Refill RX ring */
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intel_refill_rx ( intel );
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}
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/**
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* Enable or disable interrupts
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*
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* @v netdev Network device
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* @v enable Interrupts should be enabled
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*/
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static void intelx_irq ( struct net_device *netdev, int enable ) {
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struct intel_nic *intel = netdev->priv;
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uint32_t mask;
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mask = ( INTELX_EIRQ_LSC | INTELX_EIRQ_RXO | INTELX_EIRQ_TX0 |
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INTELX_EIRQ_RX0 );
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if ( enable ) {
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writel ( mask, intel->regs + INTELX_EIMS );
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} else {
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writel ( mask, intel->regs + INTELX_EIMC );
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}
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}
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/** Network device operations */
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static struct net_device_operations intelx_operations = {
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.open = intelx_open,
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.close = intelx_close,
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.transmit = intel_transmit,
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.poll = intelx_poll,
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.irq = intelx_irq,
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};
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/******************************************************************************
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*
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* PCI interface
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*
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******************************************************************************
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*/
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/**
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* Probe PCI device
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*
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* @v pci PCI device
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* @ret rc Return status code
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*/
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static int intelx_probe ( struct pci_device *pci ) {
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struct net_device *netdev;
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struct intel_nic *intel;
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int rc;
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/* Allocate and initialise net device */
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netdev = alloc_etherdev ( sizeof ( *intel ) );
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if ( ! netdev ) {
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rc = -ENOMEM;
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goto err_alloc;
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}
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netdev_init ( netdev, &intelx_operations );
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intel = netdev->priv;
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pci_set_drvdata ( pci, netdev );
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netdev->dev = &pci->dev;
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memset ( intel, 0, sizeof ( *intel ) );
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intel->port = PCI_FUNC ( pci->busdevfn );
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intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTELX_TD );
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intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTELX_RD );
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/* Fix up PCI device */
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adjust_pci_device ( pci );
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/* Map registers */
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intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
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/* Reset the NIC */
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if ( ( rc = intelx_reset ( intel ) ) != 0 )
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goto err_reset;
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/* Fetch MAC address */
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if ( ( rc = intelx_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
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goto err_fetch_mac;
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/* Register network device */
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if ( ( rc = register_netdev ( netdev ) ) != 0 )
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goto err_register_netdev;
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/* Set initial link state */
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intelx_check_link ( netdev );
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return 0;
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unregister_netdev ( netdev );
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err_register_netdev:
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err_fetch_mac:
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intelx_reset ( intel );
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err_reset:
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iounmap ( intel->regs );
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netdev_nullify ( netdev );
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netdev_put ( netdev );
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err_alloc:
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return rc;
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}
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/**
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* Remove PCI device
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*
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* @v pci PCI device
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*/
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static void intelx_remove ( struct pci_device *pci ) {
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struct net_device *netdev = pci_get_drvdata ( pci );
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struct intel_nic *intel = netdev->priv;
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/* Unregister network device */
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unregister_netdev ( netdev );
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/* Reset the NIC */
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intelx_reset ( intel );
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/* Free network device */
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iounmap ( intel->regs );
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netdev_nullify ( netdev );
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netdev_put ( netdev );
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}
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/** PCI device IDs */
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static struct pci_device_id intelx_nics[] = {
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PCI_ROM ( 0x8086, 0x10fb, "82599", "82599", 0 ),
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};
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/** PCI driver */
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struct pci_driver intelx_driver __pci_driver = {
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.ids = intelx_nics,
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.id_count = ( sizeof ( intelx_nics ) / sizeof ( intelx_nics[0] ) ),
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.probe = intelx_probe,
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.remove = intelx_remove,
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};
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@ -0,0 +1,114 @@
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#ifndef _INTELX_H
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#define _INTELX_H
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/** @file
|
||||
*
|
||||
* Intel 10 Gigabit Ethernet network card driver
|
||||
*
|
||||
*/
|
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|
||||
FILE_LICENCE ( GPL2_OR_LATER );
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|
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#include <stdint.h>
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#include <ipxe/if_ether.h>
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#include "intel.h"
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/** Device Control Register */
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#define INTELX_CTRL 0x00000UL
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#define INTELX_CTRL_LRST 0x00000008UL /**< Link reset */
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#define INTELX_CTRL_RST 0x04000000UL /**< Device reset */
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/** Time to delay for device reset, in milliseconds */
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#define INTELX_RESET_DELAY_MS 20
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/** Extended Interrupt Cause Read Register */
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#define INTELX_EICR 0x00800UL
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||||
#define INTELX_EIRQ_RX0 0x00000001UL /**< RX0 (via IVAR) */
|
||||
#define INTELX_EIRQ_TX0 0x00000002UL /**< RX0 (via IVAR) */
|
||||
#define INTELX_EIRQ_RXO 0x00020000UL /**< Receive overrun */
|
||||
#define INTELX_EIRQ_LSC 0x00100000UL /**< Link status change */
|
||||
|
||||
/** Interrupt Mask Set/Read Register */
|
||||
#define INTELX_EIMS 0x00880UL
|
||||
|
||||
/** Interrupt Mask Clear Register */
|
||||
#define INTELX_EIMC 0x00888UL
|
||||
|
||||
/** Interrupt Vector Allocation Register */
|
||||
#define INTELX_IVAR 0x00900UL
|
||||
#define INTELX_IVAR_RX0(bit) ( (bit) << 0 ) /**< RX queue 0 allocation */
|
||||
#define INTELX_IVAR_RX0_DEFAULT INTELX_IVAR_RX0 ( 0x00 )
|
||||
#define INTELX_IVAR_RX0_MASK INTELX_IVAR_RX0 ( 0x3f )
|
||||
#define INTELX_IVAR_RX0_VALID 0x00000080UL /**< RX queue 0 valid */
|
||||
#define INTELX_IVAR_TX0(bit) ( (bit) << 8 ) /**< TX queue 0 allocation */
|
||||
#define INTELX_IVAR_TX0_DEFAULT INTELX_IVAR_TX0 ( 0x01 )
|
||||
#define INTELX_IVAR_TX0_MASK INTELX_IVAR_TX0 ( 0x3f )
|
||||
#define INTELX_IVAR_TX0_VALID 0x00008000UL /**< TX queue 0 valid */
|
||||
|
||||
/** Receive Filter Control Register */
|
||||
#define INTELX_FCTRL 0x05080UL
|
||||
#define INTELX_FCTRL_MPE 0x00000100UL /**< Multicast promiscuous */
|
||||
#define INTELX_FCTRL_UPE 0x00000200UL /**< Unicast promiscuous mode */
|
||||
#define INTELX_FCTRL_BAM 0x00000400UL /**< Broadcast accept mode */
|
||||
|
||||
/** Receive Address Low
|
||||
*
|
||||
* The MAC address registers RAL0/RAH0 exist at address 0x05400 for
|
||||
* the 82598 and 0x0a200 for the 82599, according to the datasheet.
|
||||
* In practice, the 82599 seems to also provide a copy of these
|
||||
* registers at 0x05400. To aim for maximum compatibility, we try
|
||||
* both addresses when reading the initial MAC address, and set both
|
||||
* addresses when setting the MAC address.
|
||||
*/
|
||||
#define INTELX_RAL0 0x05400UL
|
||||
#define INTELX_RAL0_ALT 0x0a200UL
|
||||
|
||||
/** Receive Address High */
|
||||
#define INTELX_RAH0 0x05404UL
|
||||
#define INTELX_RAH0_ALT 0x0a204UL
|
||||
#define INTELX_RAH0_AV 0x80000000UL /**< Address valid */
|
||||
|
||||
/** Receive Descriptor register block */
|
||||
#define INTELX_RD 0x01000UL
|
||||
|
||||
/** Split Receive Control Register */
|
||||
#define INTELX_SRRCTL 0x02100UL
|
||||
#define INTELX_SRRCTL_BSIZE(kb) ( (kb) << 0 ) /**< Receive buffer size */
|
||||
#define INTELX_SRRCTL_BSIZE_DEFAULT INTELX_SRRCTL_BSIZE ( 0x02 )
|
||||
#define INTELX_SRRCTL_BSIZE_MASK INTELX_SRRCTL_BSIZE ( 0x1f )
|
||||
|
||||
/** Receive DMA Control Register */
|
||||
#define INTELX_RDRXCTL 0x02f00UL
|
||||
#define INTELX_RDRXCTL_SECRC 0x00000001UL /**< Strip CRC */
|
||||
|
||||
/** Receive Control Register */
|
||||
#define INTELX_RXCTRL 0x03000UL
|
||||
#define INTELX_RXCTRL_RXEN 0x00000001UL /**< Receive enable */
|
||||
|
||||
/** Transmit DMA Control Register */
|
||||
#define INTELX_DMATXCTL 0x04a80UL
|
||||
#define INTELX_DMATXCTL_TE 0x00000001UL /**< Transmit enable */
|
||||
|
||||
/** Transmit Descriptor register block */
|
||||
#define INTELX_TD 0x06000UL
|
||||
|
||||
/** RX DCA Control Register */
|
||||
#define INTELX_DCA_RXCTRL 0x02200UL
|
||||
#define INTELX_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */
|
||||
|
||||
/** MAC Core Control 0 Register */
|
||||
#define INTELX_HLREG0 0x04240UL
|
||||
#define INTELX_HLREG0_JUMBOEN 0x00000004UL /**< Jumbo frame enable */
|
||||
|
||||
/** Maximum Frame Size Register */
|
||||
#define INTELX_MAXFRS 0x04268UL
|
||||
#define INTELX_MAXFRS_MFS(len) ( (len) << 16 ) /**< Maximum frame size */
|
||||
#define INTELX_MAXFRS_MFS_DEFAULT \
|
||||
INTELX_MAXFRS_MFS ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
|
||||
#define INTELX_MAXFRS_MFS_MASK INTELX_MAXFRS_MFS ( 0xffff )
|
||||
|
||||
/** Link Status Register */
|
||||
#define INTELX_LINKS 0x042a4UL
|
||||
#define INTELX_LINKS_UP 0x40000000UL /**< Link up */
|
||||
|
||||
#endif /* _INTELX_H */
|
||||
|
|
@ -148,6 +148,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
|
|||
#define ERRFILE_skeleton ( ERRFILE_DRIVER | 0x00640000 )
|
||||
#define ERRFILE_intel ( ERRFILE_DRIVER | 0x00650000 )
|
||||
#define ERRFILE_myson ( ERRFILE_DRIVER | 0x00660000 )
|
||||
#define ERRFILE_intelx ( ERRFILE_DRIVER | 0x00670000 )
|
||||
|
||||
#define ERRFILE_scsi ( ERRFILE_DRIVER | 0x00700000 )
|
||||
#define ERRFILE_arbel ( ERRFILE_DRIVER | 0x00710000 )
|
||||
|
|
|
|||
Reference in New Issue