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[intel] Remove hardcoded offsets for descriptor ring registers 

The Intel 10 Gigabit NICs use the same simplified (aka "legacy")
descriptor format and the same layout for descriptor register blocks
as the Intel 1 Gigabit NICs.  The offsets of the descriptor register
blocks are not the same.

Simplify reuse of the existing code by removing all hardcoded offsets
for registers within descriptor register blocks, and ensuring that all
offsets are calculated using the descriptor register block base
address provided via intel_init_ring().

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown 2013-04-03 15:20:55 +01:00
parent 9909e7b10a
commit c2ba57e517
2 changed files with 6 additions and 18 deletions
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12
src/drivers/net/intel.c
View File

@ -248,10 +248,10 @@ static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
static void __attribute__ (( unused )) intel_diag ( struct intel_nic *intel ) {
DBGC ( intel, "INTEL %p TDH=%04x TDT=%04x RDH=%04x RDT=%04x\n", intel,
readl ( intel->regs + INTEL_TDH ),
readl ( intel->regs + INTEL_TDT ),
readl ( intel->regs + INTEL_RDH ),
readl ( intel->regs + INTEL_RDT ) );
readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
}
/******************************************************************************
@ -468,7 +468,7 @@ static void intel_refill_rx ( struct intel_nic *intel ) {
intel->rx_iobuf[rx_idx] = iobuf;
/* Push descriptor to card */
writel ( rx_tail, intel->regs + INTEL_RDT );
writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
( ( unsigned long long ) address ),
@ -599,7 +599,7 @@ static int intel_transmit ( struct net_device *netdev,
wmb();
/* Notify card that there are packets ready to transmit */
writel ( tx_tail, intel->regs + INTEL_TDT );
writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
( ( unsigned long long ) address ),

12
src/drivers/net/intel.h
View File

@ -175,18 +175,6 @@ enum intel_descriptor_status {
#define INTEL_xDCTL 0x28
#define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */
/** Receive Descriptor Head */
#define INTEL_RDH ( INTEL_RD + INTEL_xDH )
/** Receive Descriptor Tail */
#define INTEL_RDT ( INTEL_RD + INTEL_xDT )
/** Transmit Descriptor Head */
#define INTEL_TDH ( INTEL_TD + INTEL_xDH )
/** Transmit Descriptor Tail */
#define INTEL_TDT ( INTEL_TD + INTEL_xDT )
/** Receive Address Low */
#define INTEL_RAL0 0x05400UL