diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c
index 867efbcd..1e2cbdf4 100644
--- a/src/drivers/net/realtek.c
+++ b/src/drivers/net/realtek.c
@@ -415,11 +415,35 @@ static void realtek_check_link ( struct net_device *netdev ) {
 	if ( rtl->have_phy_regs ) {
 		phystatus = readb ( rtl->regs + RTL_PHYSTATUS );
 		link_up = ( phystatus & RTL_PHYSTATUS_LINKSTS );
-		DBGC ( rtl, "REALTEK %p PHY status is %02x\n", rtl, phystatus );
+		DBGC ( rtl, "REALTEK %p PHY status is %02x (%s%s%s%s%s%s, "
+		       "Link%s, %sDuplex)\n", rtl, phystatus,
+		       ( ( phystatus & RTL_PHYSTATUS_ENTBI ) ? "TBI" : "GMII" ),
+		       ( ( phystatus & RTL_PHYSTATUS_TXFLOW ) ?
+			 ", TxFlow" : "" ),
+		       ( ( phystatus & RTL_PHYSTATUS_RXFLOW ) ?
+			 ", RxFlow" : "" ),
+		       ( ( phystatus & RTL_PHYSTATUS_1000MF ) ?
+			 ", 1000Mbps" : "" ),
+		       ( ( phystatus & RTL_PHYSTATUS_100M ) ?
+			 ", 100Mbps" : "" ),
+		       ( ( phystatus & RTL_PHYSTATUS_10M ) ?
+			 ", 10Mbps" : "" ),
+		       ( ( phystatus & RTL_PHYSTATUS_LINKSTS ) ?
+			 "Up" : "Down" ),
+		       ( ( phystatus & RTL_PHYSTATUS_FULLDUP ) ?
+			 "Full" : "Half" ) );
 	} else {
 		msr = readb ( rtl->regs + RTL_MSR );
 		link_up = ( ! ( msr & RTL_MSR_LINKB ) );
-		DBGC ( rtl, "REALTEK %p media status is %02x\n", rtl, msr );
+		DBGC ( rtl, "REALTEK %p media status is %02x (Link%s, "
+		       "%dMbps%s%s%s%s%s)\n", rtl, msr,
+		       ( ( msr & RTL_MSR_LINKB ) ? "Down" : "Up" ),
+		       ( ( msr & RTL_MSR_SPEED_10 ) ? 10 : 100 ),
+		       ( ( msr & RTL_MSR_TXFCE ) ? ", TxFlow" : "" ),
+		       ( ( msr & RTL_MSR_RXFCE ) ? ", RxFlow" : "" ),
+		       ( ( msr & RTL_MSR_AUX_STATUS ) ? ", AuxPwr" : "" ),
+		       ( ( msr & RTL_MSR_TXPF ) ? ", TxPause" : "" ),
+		       ( ( msr & RTL_MSR_RXPF ) ? ", RxPause" : "" ) );
 	}
 
 	/* Report link state */
diff --git a/src/drivers/net/realtek.h b/src/drivers/net/realtek.h
index a17f963f..e426dc5a 100644
--- a/src/drivers/net/realtek.h
+++ b/src/drivers/net/realtek.h
@@ -187,7 +187,13 @@ enum realtek_legacy_status {
 
 /** Media Status Register (byte, 8139 only) */
 #define RTL_MSR 0x58
+#define RTL_MSR_TXFCE		0x80	/**< TX flow control enabled */
+#define RTL_MSR_RXFCE		0x40	/**< RX flow control enabled */
+#define RTL_MSR_AUX_STATUS	0x10	/**< Aux power present */
+#define RTL_MSR_SPEED_10	0x08	/**< 10Mbps */
 #define RTL_MSR_LINKB		0x04	/**< Inverse of link status */
+#define RTL_MSR_TXPF		0x02	/**< TX pause flag */
+#define RTL_MSR_RXPF		0x01	/**< RX pause flag */
 
 /** PHY Access Register (dword, 8169 only) */
 #define RTL_PHYAR 0x60
@@ -204,7 +210,14 @@ enum realtek_legacy_status {
 
 /** PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) */
 #define RTL_PHYSTATUS 0x6c
+#define RTL_PHYSTATUS_ENTBI	0x80	/**< TBI / GMII mode */
+#define RTL_PHYSTATUS_TXFLOW	0x40	/**< TX flow control enabled */
+#define RTL_PHYSTATUS_RXFLOW	0x20	/**< RX flow control enabled */
+#define RTL_PHYSTATUS_1000MF	0x10	/**< 1000Mbps full-duplex */
+#define RTL_PHYSTATUS_100M	0x08	/**< 100Mbps */
+#define RTL_PHYSTATUS_10M	0x04	/**< 10Mbps */
 #define RTL_PHYSTATUS_LINKSTS	0x02	/**< Link ok */
+#define RTL_PHYSTATUS_FULLDUP	0x01	/**< Full duplex */
 
 /** Transmit Priority Polling Register (byte, 8139C+ only) */
 #define RTL_TPPOLL_8139CP 0xd9