david/ipxe
david
/
ipxe
Archived
1
0
Fork 0
Code

[tg3] Fix driver for BCM5719, BCM5720, BCM5764M, BCM57762 

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Kevin Tran 2012-08-20 18:48:50 +01:00 committed by Michael Brown
parent 8f7cd88af5
commit a05871d89a
4 changed files with 29 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/drivers/net/tg3/tg3.c
View File

@ -247,11 +247,12 @@ static int tg3_open(struct net_device *dev)
return err;
tpr->rx_std_iob_cnt = 0;
tg3_refill_prod_ring(tp);
err = tg3_init_hw(tp, 1);
if (err != 0)
DBGC(tp->dev, "tg3_init_hw failed: %s\n", strerror(err));
else
tg3_refill_prod_ring(tp);
return err;
}
@ -301,7 +302,6 @@ static int tg3_transmit(struct net_device *dev, struct io_buffer *iob)
struct tg3 *tp = netdev_priv(dev);
u32 len, entry;
dma_addr_t mapping;
u32 bmsr;
if (tg3_tx_avail(tp) < 1) {
DBGC(dev, "Transmit ring full\n");
@ -323,14 +323,10 @@ static int tg3_transmit(struct net_device *dev, struct io_buffer *iob)
/* Packets are ready, update Tx producer idx local and on card. */
tw32_tx_mbox(tp->prodmbox, entry);
writel(entry, tp->regs + MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
tp->tx_prod = entry;
mb();
tg3_readphy(tp, MII_BMSR, &bmsr);
return 0;
}
@ -422,8 +418,10 @@ static void tg3_refill_prod_ring(struct tg3 *tp)
tpr->rx_std_iob_cnt++;
}
tpr->rx_std_prod_idx = idx;
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
if ((u32)idx != tpr->rx_std_prod_idx) {
tpr->rx_std_prod_idx = idx;
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
}
}
static void tg3_rx_complete(struct net_device *dev)
@ -469,7 +467,10 @@ static void tg3_rx_complete(struct net_device *dev)
tpr->rx_std_iob_cnt--;
}
tp->rx_rcb_ptr = sw_idx;
if (tp->rx_rcb_ptr != sw_idx) {
tw32_rx_mbox(tp->consmbox, sw_idx);
tp->rx_rcb_ptr = sw_idx;
}
tg3_refill_prod_ring(tp);
}
@ -480,7 +481,9 @@ static void tg3_poll(struct net_device *dev)
struct tg3 *tp = netdev_priv(dev);
/* ACK interrupts */
tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00);
/*
*tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00);
*/
tp->hw_status->status &= ~SD_STATUS_UPDATED;
tg3_poll_link(tp);
@ -905,6 +908,7 @@ static struct pci_device_id tg3_nics[] = {
PCI_ROM(0x14e4, 0x1684, "14e4-1684", "14e4-1684", 0),
PCI_ROM(0x14e4, 0x165b, "14e4-165b", "14e4-165b", 0),
PCI_ROM(0x14e4, 0x1681, "14e4-1681", "14e4-1681", 0),
PCI_ROM(0x14e4, 0x1682, "14e4-1682", "14e4-1682", 0),
PCI_ROM(0x14e4, 0x1680, "14e4-1680", "14e4-1680", 0),
PCI_ROM(0x14e4, 0x1688, "14e4-1688", "14e4-1688", 0),
PCI_ROM(0x14e4, 0x1689, "14e4-1689", "14e4-1689", 0),

2
src/drivers/net/tg3/tg3.h
View File

@ -153,6 +153,7 @@
#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
#define TG3_BDINFO_SIZE 0x10UL
#define RX_STD_MAX_SIZE 1536
#define TG3_RX_STD_MAX_SIZE_5700 512
#define TG3_RX_STD_MAX_SIZE_5717 2048
#define TG3_RX_JMB_MAX_SIZE_5700 256
@ -182,6 +183,7 @@
#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
#define TG3PCI_DEVICE_TIGON3_57762 0x1682
#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
#define TG3PCI_DEVICE_TIGON3_57795 0x16b6

8
src/drivers/net/tg3/tg3_hw.c
View File

@ -434,6 +434,7 @@ int tg3_get_invariants(struct tg3 *tp)
else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
@ -2127,9 +2128,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
if (tg3_flag(tp, 57765_PLUS))
val |= (RX_STD_MAX_SIZE << 2);
tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
tpr->rx_std_prod_idx = TG3_DEF_RX_RING_PENDING;
tpr->rx_std_prod_idx = 0;
/* std prod index is updated by tg3_refill_prod_ring() */
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, 0);
@ -2137,6 +2141,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
tg3_rings_reset(tp);
__tg3_set_mac_addr(tp,0);
#define TG3_MAX_MTU 1522
/* MTU + ethernet header + FCS + optional VLAN tag */
tw32(MAC_RX_MTU_SIZE, TG3_MAX_MTU);

14
src/drivers/net/tg3/tg3_phy.c
View File

@ -1008,12 +1008,11 @@ skip_phy_reset:
void tg3_poll_link(struct tg3 *tp)
{ DBGP("%s\n", __func__);
u32 mac_stat;
mac_stat = tr32(MAC_STATUS);
if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
if (tp->hw_status->status & SD_STATUS_LINK_CHG) {
DBGC(tp->dev,"link_changed\n");
tp->hw_status->status &= ~SD_STATUS_LINK_CHG;
tg3_setup_phy(tp, 0);
}
}
static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
@ -1506,9 +1505,8 @@ relink:
tw32_f(MAC_MODE, tp->mac_mode);
udelay(40);
/* We always use the link change register */
/* NOTE: this freezes for mdc? */
tw32_f(MAC_EVENT, 0);
/* Enabled attention when the link has changed state. */
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
udelay(40);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&