Separated out to a clean new drivers/infiniband directory.
This commit is contained in:
Michael Brown
parent
a5ec029d24
commit
982e4dd101
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@ -152,6 +152,7 @@ SRCDIRS += drivers/scsi
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SRCDIRS += drivers/ata
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SRCDIRS += drivers/nvs
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SRCDIRS += drivers/bitbash
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SRCDIRS += drivers/infiniband
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SRCDIRS += interface/pxe
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SRCDIRS += tests
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SRCDIRS += crypto crypto/axtls crypto/matrixssl
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@ -165,11 +166,6 @@ SRCDIRS += usr
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NON_AUTO_SRCS += core/elf_loader.c
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NON_AUTO_SRCS += drivers/net/prism2.c
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SRCS += drivers/net/mlx_ipoib/mt25218.c
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SRCS += drivers/net/mlx_ipoib/mt23108.c
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CFLAGS_mt25218 = -Wno-error
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CFLAGS_mt23108 = -Wno-error
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# Rules for finalising files. TGT_MAKEROM_FLAGS is defined as part of
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# the automatic build system and varies by target; it includes the
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# "-p 0x1234,0x5678" string to set the PCI IDs.
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,459 @@
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#ifndef _ARBEL_H
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#define _ARBEL_H
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/** @file
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*
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* Mellanox Arbel Infiniband HCA driver
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*
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*/
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#include <stdint.h>
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#include <gpxe/uaccess.h>
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#include "mlx_bitops.h"
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#include "MT25218_PRM.h"
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/*
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* Hardware constants
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*
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*/
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/* PCI BARs */
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#define ARBEL_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0
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#define ARBEL_PCI_CONFIG_BAR_SIZE 0x100000
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#define ARBEL_PCI_UAR_BAR PCI_BASE_ADDRESS_2
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#define ARBEL_PCI_UAR_IDX 1
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#define ARBEL_PCI_UAR_SIZE 0x1000
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/* UAR context table (UCE) resource types */
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#define ARBEL_UAR_RES_NONE 0x00
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#define ARBEL_UAR_RES_CQ_CI 0x01
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#define ARBEL_UAR_RES_CQ_ARM 0x02
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#define ARBEL_UAR_RES_SQ 0x03
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#define ARBEL_UAR_RES_RQ 0x04
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#define ARBEL_UAR_RES_GROUP_SEP 0x07
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/* Work queue entry and completion queue entry opcodes */
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#define ARBEL_OPCODE_SEND 0x0a
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#define ARBEL_OPCODE_RECV_ERROR 0xfe
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#define ARBEL_OPCODE_SEND_ERROR 0xff
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/* HCA command register opcodes */
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#define ARBEL_HCR_QUERY_DEV_LIM 0x0003
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#define ARBEL_HCR_QUERY_FW 0x0004
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#define ARBEL_HCR_INIT_HCA 0x0007
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#define ARBEL_HCR_CLOSE_HCA 0x0008
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#define ARBEL_HCR_INIT_IB 0x0009
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#define ARBEL_HCR_CLOSE_IB 0x000a
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#define ARBEL_HCR_SW2HW_MPT 0x000d
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#define ARBEL_HCR_MAP_EQ 0x0012
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#define ARBEL_HCR_SW2HW_EQ 0x0013
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#define ARBEL_HCR_HW2SW_EQ 0x0014
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#define ARBEL_HCR_SW2HW_CQ 0x0016
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#define ARBEL_HCR_HW2SW_CQ 0x0017
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#define ARBEL_HCR_RST2INIT_QPEE 0x0019
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#define ARBEL_HCR_INIT2RTR_QPEE 0x001a
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#define ARBEL_HCR_RTR2RTS_QPEE 0x001b
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#define ARBEL_HCR_2RST_QPEE 0x0021
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#define ARBEL_HCR_MAD_IFC 0x0024
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#define ARBEL_HCR_READ_MGM 0x0025
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#define ARBEL_HCR_WRITE_MGM 0x0026
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#define ARBEL_HCR_MGID_HASH 0x0027
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#define ARBEL_HCR_RUN_FW 0x0ff6
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#define ARBEL_HCR_DISABLE_LAM 0x0ff7
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#define ARBEL_HCR_ENABLE_LAM 0x0ff8
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#define ARBEL_HCR_UNMAP_ICM 0x0ff9
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#define ARBEL_HCR_MAP_ICM 0x0ffa
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#define ARBEL_HCR_UNMAP_ICM_AUX 0x0ffb
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#define ARBEL_HCR_MAP_ICM_AUX 0x0ffc
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#define ARBEL_HCR_SET_ICM_SIZE 0x0ffd
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#define ARBEL_HCR_UNMAP_FA 0x0ffe
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#define ARBEL_HCR_MAP_FA 0x0fff
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/* Service types */
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#define ARBEL_ST_UD 0x03
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/* MTUs */
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#define ARBEL_MTU_2048 0x04
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#define ARBEL_NO_EQ 64
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#define ARBEL_INVALID_LKEY 0x00000100UL
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#define ARBEL_DB_POST_SND_OFFSET 0x10
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/*
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* Datatypes that seem to be missing from the autogenerated documentation
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*
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*/
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struct arbelprm_mgm_hash_st {
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pseudo_bit_t reserved0[0x00020];
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/* -------------- */
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pseudo_bit_t hash[0x00010];
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pseudo_bit_t reserved1[0x00010];
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} __attribute__ (( packed ));
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struct arbelprm_scalar_parameter_st {
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pseudo_bit_t reserved0[0x00020];
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/* -------------- */
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pseudo_bit_t value[0x00020];
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} __attribute__ (( packed ));
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/*
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* Wrapper structures for hardware datatypes
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*
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*/
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struct MLX_DECLARE_STRUCT ( arbelprm_access_lam );
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struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_context );
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struct MLX_DECLARE_STRUCT ( arbelprm_completion_queue_entry );
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struct MLX_DECLARE_STRUCT ( arbelprm_completion_with_error );
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struct MLX_DECLARE_STRUCT ( arbelprm_cq_arm_db_record );
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struct MLX_DECLARE_STRUCT ( arbelprm_cq_ci_db_record );
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struct MLX_DECLARE_STRUCT ( arbelprm_eqc );
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struct MLX_DECLARE_STRUCT ( arbelprm_hca_command_register );
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struct MLX_DECLARE_STRUCT ( arbelprm_init_hca );
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struct MLX_DECLARE_STRUCT ( arbelprm_init_ib );
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struct MLX_DECLARE_STRUCT ( arbelprm_mad_ifc );
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struct MLX_DECLARE_STRUCT ( arbelprm_mgm_entry );
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struct MLX_DECLARE_STRUCT ( arbelprm_mgm_hash );
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struct MLX_DECLARE_STRUCT ( arbelprm_mpt );
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struct MLX_DECLARE_STRUCT ( arbelprm_qp_db_record );
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struct MLX_DECLARE_STRUCT ( arbelprm_qp_ee_state_transitions );
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struct MLX_DECLARE_STRUCT ( arbelprm_query_dev_lim );
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struct MLX_DECLARE_STRUCT ( arbelprm_query_fw );
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struct MLX_DECLARE_STRUCT ( arbelprm_queue_pair_ee_context_entry );
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struct MLX_DECLARE_STRUCT ( arbelprm_recv_wqe_segment_next );
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struct MLX_DECLARE_STRUCT ( arbelprm_scalar_parameter );
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struct MLX_DECLARE_STRUCT ( arbelprm_send_doorbell );
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struct MLX_DECLARE_STRUCT ( arbelprm_ud_address_vector );
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struct MLX_DECLARE_STRUCT ( arbelprm_virtual_physical_mapping );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ctrl_send );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_data_ptr );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_next );
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struct MLX_DECLARE_STRUCT ( arbelprm_wqe_segment_ud );
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/*
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* Composite hardware datatypes
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*
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*/
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#define ARBEL_MAX_GATHER 1
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struct arbelprm_ud_send_wqe {
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struct arbelprm_wqe_segment_next next;
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struct arbelprm_wqe_segment_ctrl_send ctrl;
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struct arbelprm_wqe_segment_ud ud;
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struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_GATHER];
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} __attribute__ (( packed ));
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#define ARBEL_MAX_SCATTER 1
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struct arbelprm_recv_wqe {
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/* The autogenerated header is inconsistent between send and
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* receive WQEs. The "ctrl" structure for receive WQEs is
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* defined to include the "next" structure. Since the "ctrl"
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* part of the "ctrl" structure contains only "reserved, must
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* be zero" bits, we ignore its definition and provide
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* something more usable.
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*/
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struct arbelprm_recv_wqe_segment_next next;
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uint32_t ctrl[2]; /* All "reserved, must be zero" */
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struct arbelprm_wqe_segment_data_ptr data[ARBEL_MAX_SCATTER];
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} __attribute__ (( packed ));
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union arbelprm_completion_entry {
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struct arbelprm_completion_queue_entry normal;
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struct arbelprm_completion_with_error error;
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} __attribute__ (( packed ));
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union arbelprm_doorbell_record {
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struct arbelprm_cq_arm_db_record cq_arm;
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struct arbelprm_cq_ci_db_record cq_ci;
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struct arbelprm_qp_db_record qp;
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} __attribute__ (( packed ));
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union arbelprm_doorbell_register {
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struct arbelprm_send_doorbell send;
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uint32_t dword[2];
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} __attribute__ (( packed ));
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union arbelprm_mad {
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struct arbelprm_mad_ifc ifc;
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union ib_mad mad;
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} __attribute__ (( packed ));
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/*
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* gPXE-specific definitions
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*
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*/
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/** Arbel device limits */
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struct arbel_dev_limits {
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/** Number of reserved QPs */
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unsigned int reserved_qps;
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/** QP context entry size */
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size_t qpc_entry_size;
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/** Extended QP context entry size */
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size_t eqpc_entry_size;
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/** Number of reserved SRQs */
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unsigned int reserved_srqs;
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/** SRQ context entry size */
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size_t srqc_entry_size;
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/** Number of reserved EEs */
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unsigned int reserved_ees;
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/** EE context entry size */
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size_t eec_entry_size;
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/** Extended EE context entry size */
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size_t eeec_entry_size;
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/** Number of reserved CQs */
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unsigned int reserved_cqs;
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/** CQ context entry size */
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size_t cqc_entry_size;
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/** Number of reserved MTTs */
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unsigned int reserved_mtts;
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/** MTT entry size */
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size_t mtt_entry_size;
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/** Number of reserved MRWs */
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unsigned int reserved_mrws;
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/** MPT entry size */
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size_t mpt_entry_size;
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/** Number of reserved RDBs */
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unsigned int reserved_rdbs;
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/** EQ context entry size */
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size_t eqc_entry_size;
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/** Number of reserved UARs */
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unsigned int reserved_uars;
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};
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/** Alignment of Arbel send work queue entries */
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#define ARBEL_SEND_WQE_ALIGN 128
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/** An Arbel send work queue entry */
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union arbel_send_wqe {
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struct arbelprm_ud_send_wqe ud;
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uint8_t force_align[ARBEL_SEND_WQE_ALIGN];
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} __attribute__ (( packed ));
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/** An Arbel send work queue */
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struct arbel_send_work_queue {
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/** Doorbell record number */
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unsigned int doorbell_idx;
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/** Work queue entries */
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union arbel_send_wqe *wqe;
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/** Size of work queue */
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size_t wqe_size;
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};
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/** Alignment of Arbel receive work queue entries */
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#define ARBEL_RECV_WQE_ALIGN 64
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/** An Arbel receive work queue entry */
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union arbel_recv_wqe {
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struct arbelprm_recv_wqe recv;
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uint8_t force_align[ARBEL_RECV_WQE_ALIGN];
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} __attribute__ (( packed ));
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/** An Arbel receive work queue */
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struct arbel_recv_work_queue {
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/** Doorbell record number */
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unsigned int doorbell_idx;
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/** Work queue entries */
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union arbel_recv_wqe *wqe;
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/** Size of work queue */
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size_t wqe_size;
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};
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/** Maximum number of allocatable queue pairs
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*
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* This is a policy decision, not a device limit.
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*/
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#define ARBEL_MAX_QPS 8
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/** Base queue pair number */
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#define ARBEL_QPN_BASE 0x550000
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/** An Arbel queue pair */
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struct arbel_queue_pair {
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/** Send work queue */
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struct arbel_send_work_queue send;
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/** Receive work queue */
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struct arbel_recv_work_queue recv;
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};
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/** Maximum number of allocatable completion queues
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*
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* This is a policy decision, not a device limit.
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*/
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#define ARBEL_MAX_CQS 8
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/** An Arbel completion queue */
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struct arbel_completion_queue {
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/** Consumer counter doorbell record number */
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unsigned int ci_doorbell_idx;
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/** Arm queue doorbell record number */
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unsigned int arm_doorbell_idx;
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/** Completion queue entries */
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union arbelprm_completion_entry *cqe;
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/** Size of completion queue */
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size_t cqe_size;
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};
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/** An Arbel resource bitmask */
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typedef uint32_t arbel_bitmask_t;
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/** Size of an Arbel resource bitmask */
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#define ARBEL_BITMASK_SIZE(max_entries) \
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( ( (max_entries) + ( 8 * sizeof ( arbel_bitmask_t ) ) - 1 ) / \
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( 8 * sizeof ( arbel_bitmask_t ) ) )
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/** An Arbel device */
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struct arbel {
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/** PCI configuration registers */
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void *config;
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/** PCI user Access Region */
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void *uar;
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/** Command input mailbox */
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void *mailbox_in;
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/** Command output mailbox */
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void *mailbox_out;
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/** Firmware area in external memory */
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userptr_t firmware_area;
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/** ICM size */
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size_t icm_len;
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/** ICM AUX size */
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size_t icm_aux_len;
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/** ICM area */
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userptr_t icm;
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/** Doorbell records */
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union arbelprm_doorbell_record *db_rec;
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/** Reserved LKey
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*
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* Used to get unrestricted memory access.
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*/
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unsigned long reserved_lkey;
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/** Completion queue in-use bitmask */
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arbel_bitmask_t cq_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_CQS ) ];
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/** Queue pair in-use bitmask */
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arbel_bitmask_t qp_inuse[ ARBEL_BITMASK_SIZE ( ARBEL_MAX_QPS ) ];
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/** Device limits */
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struct arbel_dev_limits limits;
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};
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/** Global protection domain */
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#define ARBEL_GLOBAL_PD 0x123456
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/** Memory key prefix */
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#define ARBEL_MKEY_PREFIX 0x77000000UL
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/*
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* HCA commands
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*
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*/
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#define ARBEL_HCR_BASE 0x80680
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#define ARBEL_HCR_REG(x) ( ARBEL_HCR_BASE + 4 * (x) )
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#define ARBEL_HCR_MAX_WAIT_MS 2000
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#define ARBEL_MBOX_ALIGN 4096
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#define ARBEL_MBOX_SIZE 512
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/* HCA command is split into
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*
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* bits 11:0 Opcode
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* bit 12 Input uses mailbox
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* bit 13 Output uses mailbox
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* bits 22:14 Input parameter length (in dwords)
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* bits 31:23 Output parameter length (in dwords)
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*
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* Encoding the information in this way allows us to cut out several
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* parameters to the arbel_command() call.
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*/
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#define ARBEL_HCR_IN_MBOX 0x00001000UL
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#define ARBEL_HCR_OUT_MBOX 0x00002000UL
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#define ARBEL_HCR_OPCODE( _command ) ( (_command) & 0xfff )
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#define ARBEL_HCR_IN_LEN( _command ) ( ( (_command) >> 12 ) & 0x7fc )
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#define ARBEL_HCR_OUT_LEN( _command ) ( ( (_command) >> 21 ) & 0x7fc )
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/** Build HCR command from component parts */
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#define ARBEL_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \
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_out_mbox, _out_len ) \
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( (_opcode) | \
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( (_in_mbox) ? ARBEL_HCR_IN_MBOX : 0 ) | \
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( ( (_in_len) / 4 ) << 14 ) | \
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( (_out_mbox) ? ARBEL_HCR_OUT_MBOX : 0 ) | \
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( ( (_out_len) / 4 ) << 23 ) )
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#define ARBEL_HCR_IN_CMD( _opcode, _in_mbox, _in_len ) \
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ARBEL_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 )
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#define ARBEL_HCR_OUT_CMD( _opcode, _out_mbox, _out_len ) \
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ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len )
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#define ARBEL_HCR_VOID_CMD( _opcode ) \
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ARBEL_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 )
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/*
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* Doorbell record allocation
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*
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* The doorbell record map looks like:
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*
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* ARBEL_MAX_CQS * Arm completion queue doorbell
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* ARBEL_MAX_QPS * Send work request doorbell
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* Group separator
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* ...(empty space)...
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* ARBEL_MAX_QPS * Receive work request doorbell
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* ARBEL_MAX_CQS * Completion queue consumer counter update doorbell
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*/
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#define ARBEL_MAX_DOORBELL_RECORDS 512
|
||||
#define ARBEL_GROUP_SEPARATOR_DOORBELL ( ARBEL_MAX_CQS + ARBEL_MAX_QPS )
|
||||
|
||||
/**
|
||||
* Get arm completion queue doorbell index
|
||||
*
|
||||
* @v cqn_offset Completion queue number offset
|
||||
* @ret doorbell_idx Doorbell index
|
||||
*/
|
||||
static inline unsigned int
|
||||
arbel_cq_arm_doorbell_idx ( unsigned int cqn_offset ) {
|
||||
return cqn_offset;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get send work request doorbell index
|
||||
*
|
||||
* @v qpn_offset Queue pair number offset
|
||||
* @ret doorbell_idx Doorbell index
|
||||
*/
|
||||
static inline unsigned int
|
||||
arbel_send_doorbell_idx ( unsigned int qpn_offset ) {
|
||||
return ( ARBEL_MAX_CQS + qpn_offset );
|
||||
}
|
||||
|
||||
/**
|
||||
* Get receive work request doorbell index
|
||||
*
|
||||
* @v qpn_offset Queue pair number offset
|
||||
* @ret doorbell_idx Doorbell index
|
||||
*/
|
||||
static inline unsigned int
|
||||
arbel_recv_doorbell_idx ( unsigned int qpn_offset ) {
|
||||
return ( ARBEL_MAX_DOORBELL_RECORDS - ARBEL_MAX_CQS - qpn_offset - 1 );
|
||||
}
|
||||
|
||||
/**
|
||||
* Get completion queue consumer counter doorbell index
|
||||
*
|
||||
* @v cqn_offset Completion queue number offset
|
||||
* @ret doorbell_idx Doorbell index
|
||||
*/
|
||||
static inline unsigned int
|
||||
arbel_cq_ci_doorbell_idx ( unsigned int cqn_offset ) {
|
||||
return ( ARBEL_MAX_DOORBELL_RECORDS - cqn_offset - 1 );
|
||||
}
|
||||
|
||||
#endif /* _ARBEL_H */
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
#ifndef _MLX_BITOPS_H
|
||||
#define _MLX_BITOPS_H
|
||||
|
||||
/*
|
||||
* Copyright (C) 2007 Michael Brown <mbrown@fensystems.co.uk>.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Mellanox bit operations
|
||||
*
|
||||
*/
|
||||
|
||||
/* Datatype used to represent a bit in the Mellanox autogenerated headers */
|
||||
typedef unsigned char pseudo_bit_t;
|
||||
|
||||
/**
|
||||
* Wrapper structure for pseudo_bit_t structures
|
||||
*
|
||||
* This structure provides a wrapper around the autogenerated
|
||||
* pseudo_bit_t structures. It has the correct size, and also
|
||||
* encapsulates type information about the underlying pseudo_bit_t
|
||||
* structure, which allows the MLX_FILL etc. macros to work without
|
||||
* requiring explicit type information.
|
||||
*/
|
||||
#define MLX_DECLARE_STRUCT( _structure ) \
|
||||
_structure { \
|
||||
union { \
|
||||
uint8_t bytes[ sizeof ( struct _structure ## _st ) / 8 ]; \
|
||||
uint32_t dwords[ sizeof ( struct _structure ## _st ) / 32 ]; \
|
||||
struct _structure ## _st *dummy[0]; \
|
||||
} u; \
|
||||
}
|
||||
|
||||
/** Get pseudo_bit_t structure type from wrapper structure pointer */
|
||||
#define MLX_PSEUDO_STRUCT( _ptr ) \
|
||||
typeof ( *((_ptr)->u.dummy[0]) )
|
||||
|
||||
/** Bit offset of a field within a pseudo_bit_t structure */
|
||||
#define MLX_BIT_OFFSET( _structure_st, _field ) \
|
||||
offsetof ( _structure_st, _field )
|
||||
|
||||
/** Dword offset of a field within a pseudo_bit_t structure */
|
||||
#define MLX_DWORD_OFFSET( _structure_st, _field ) \
|
||||
( MLX_BIT_OFFSET ( _structure_st, _field ) / 32 )
|
||||
|
||||
/** Dword bit offset of a field within a pseudo_bit_t structure
|
||||
*
|
||||
* Yes, using mod-32 would work, but would lose the check for the
|
||||
* error of specifying a mismatched field name and dword index.
|
||||
*/
|
||||
#define MLX_DWORD_BIT_OFFSET( _structure_st, _index, _field ) \
|
||||
( MLX_BIT_OFFSET ( _structure_st, _field ) - ( 32 * (_index) ) )
|
||||
|
||||
/** Bit width of a field within a pseudo_bit_t structure */
|
||||
#define MLX_BIT_WIDTH( _structure_st, _field ) \
|
||||
sizeof ( ( ( _structure_st * ) NULL )->_field )
|
||||
|
||||
/** Bit mask for a field within a pseudo_bit_t structure */
|
||||
#define MLX_BIT_MASK( _structure_st, _field ) \
|
||||
( ( ~( ( uint32_t ) 0 ) ) >> \
|
||||
( 32 - MLX_BIT_WIDTH ( _structure_st, _field ) ) )
|
||||
|
||||
/*
|
||||
* Assemble native-endian dword from named fields and values
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_ASSEMBLE_1( _structure_st, _index, _field, _value ) \
|
||||
( (_value) << MLX_DWORD_BIT_OFFSET ( _structure_st, _index, _field ) )
|
||||
|
||||
#define MLX_ASSEMBLE_2( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_1 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_3( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_2 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_4( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_3 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_5( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_4 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_ASSEMBLE_6( _structure_st, _index, _field, _value, ... ) \
|
||||
( MLX_ASSEMBLE_1 ( _structure_st, _index, _field, _value ) | \
|
||||
MLX_ASSEMBLE_5 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
/*
|
||||
* Build native-endian (positive) dword bitmasks from named fields
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_MASK_1( _structure_st, _index, _field ) \
|
||||
( MLX_BIT_MASK ( _structure_st, _field ) << \
|
||||
MLX_DWORD_BIT_OFFSET ( _structure_st, _index, _field ) )
|
||||
|
||||
#define MLX_MASK_2( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_1 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_3( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_2 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_4( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_3 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_5( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_4 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_MASK_6( _structure_st, _index, _field, ... ) \
|
||||
( MLX_MASK_1 ( _structure_st, _index, _field ) | \
|
||||
MLX_MASK_5 ( _structure_st, _index, __VA_ARGS__ ) )
|
||||
|
||||
/*
|
||||
* Populate big-endian dwords from named fields and values
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_FILL( _ptr, _index, _assembled ) \
|
||||
do { \
|
||||
uint32_t *__ptr = &(_ptr)->u.dwords[(_index)]; \
|
||||
uint32_t __assembled = (_assembled); \
|
||||
*__ptr = cpu_to_be32 ( __assembled ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define MLX_FILL_1( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_1 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_2( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_2 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_3( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_3 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_4( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_4 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_5( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_5 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
#define MLX_FILL_6( _ptr, _index, ... ) \
|
||||
MLX_FILL ( _ptr, _index, MLX_ASSEMBLE_6 ( MLX_PSEUDO_STRUCT ( _ptr ),\
|
||||
_index, __VA_ARGS__ ) )
|
||||
|
||||
/*
|
||||
* Modify big-endian dword using named field and value
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_SET( _ptr, _field, _value ) \
|
||||
do { \
|
||||
unsigned int __index = \
|
||||
MLX_DWORD_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \
|
||||
uint32_t *__ptr = &(_ptr)->u.dwords[__index]; \
|
||||
uint32_t __value = be32_to_cpu ( *__ptr ); \
|
||||
__value &= ~( MLX_MASK_1 ( MLX_PSEUDO_STRUCT ( _ptr ), \
|
||||
__index, _field ) ); \
|
||||
__value |= MLX_ASSEMBLE_1 ( MLX_PSEUDO_STRUCT ( _ptr ), \
|
||||
__index, _field, _value ); \
|
||||
*__ptr = cpu_to_be32 ( __value ); \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* Extract value of named field
|
||||
*
|
||||
*/
|
||||
|
||||
#define MLX_GET( _ptr, _field ) \
|
||||
( { \
|
||||
unsigned int __index = \
|
||||
MLX_DWORD_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \
|
||||
uint32_t *__ptr = &(_ptr)->u.dwords[__index]; \
|
||||
uint32_t __value = be32_to_cpu ( *__ptr ); \
|
||||
__value >>= \
|
||||
MLX_DWORD_BIT_OFFSET ( MLX_PSEUDO_STRUCT ( _ptr ), \
|
||||
__index, _field ); \
|
||||
__value &= \
|
||||
MLX_BIT_MASK ( MLX_PSEUDO_STRUCT ( _ptr ), _field ); \
|
||||
__value; \
|
||||
} )
|
||||
|
||||
#endif /* _MLX_BITOPS_H */
|
||||
Reference in New Issue