Moved functions that we want to keep to drivers/bus/pci.c
This commit is contained in:
Michael Brown
parent
2ebc56f334
commit
7172d4abfb
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@ -192,146 +192,4 @@ void scan_pci_bus(int type, struct pci_device *dev)
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}
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/*
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* Set device to be a busmaster in case BIOS neglected to do so.
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* Also adjust PCI latency timer to a reasonable value, 32.
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*/
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void adjust_pci_device(struct pci_device *p)
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{
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unsigned short new_command, pci_command;
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unsigned char pci_latency;
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pcibios_read_config_word(p->bus, p->devfn, PCI_COMMAND, &pci_command);
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new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
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if (pci_command != new_command) {
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#if DEBUG > 0
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printf(
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"The PCI BIOS has not enabled this device!\n"
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"Updating PCI command %hX->%hX. pci_bus %hhX pci_device_fn %hhX\n",
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pci_command, new_command, p->bus, p->devfn);
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#endif
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pcibios_write_config_word(p->bus, p->devfn, PCI_COMMAND, new_command);
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}
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pcibios_read_config_byte(p->bus, p->devfn, PCI_LATENCY_TIMER, &pci_latency);
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if (pci_latency < 32) {
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#if DEBUG > 0
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printf("PCI latency timer (CFLT) is unreasonably low at %d. Setting to 32 clocks.\n",
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pci_latency);
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#endif
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pcibios_write_config_byte(p->bus, p->devfn, PCI_LATENCY_TIMER, 32);
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}
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}
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/*
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* Find the start of a pci resource.
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*/
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unsigned long pci_bar_start(struct pci_device *dev, unsigned int index)
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{
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uint32_t lo, hi;
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unsigned long bar;
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pci_read_config_dword(dev, index, &lo);
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if (lo & PCI_BASE_ADDRESS_SPACE_IO) {
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bar = lo & PCI_BASE_ADDRESS_IO_MASK;
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} else {
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bar = 0;
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if ((lo & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_read_config_dword(dev, index + 4, &hi);
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if (hi) {
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#if ULONG_MAX > 0xffffffff
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bar = hi;
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bar <<=32;
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#else
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printf("Unhandled 64bit BAR\n");
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return -1UL;
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#endif
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}
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}
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bar |= lo & PCI_BASE_ADDRESS_MEM_MASK;
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}
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return bar + pcibios_bus_base(dev->bus);
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}
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/*
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* Find the size of a pci resource.
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*/
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unsigned long pci_bar_size(struct pci_device *dev, unsigned int bar)
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{
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uint32_t start, size;
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/* Save the original bar */
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pci_read_config_dword(dev, bar, &start);
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/* Compute which bits can be set */
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pci_write_config_dword(dev, bar, ~0);
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pci_read_config_dword(dev, bar, &size);
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/* Restore the original size */
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pci_write_config_dword(dev, bar, start);
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/* Find the significant bits */
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if (start & PCI_BASE_ADDRESS_SPACE_IO) {
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size &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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size &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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/* Find the lowest bit set */
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size = size & ~(size - 1);
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return size;
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}
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/**
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* pci_find_capability - query for devices' capabilities
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* @dev: PCI device to query
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* @cap: capability code
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*
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* Tell if a device supports a given PCI capability.
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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*
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* %PCI_CAP_ID_PM Power Management
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*
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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*
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* %PCI_CAP_ID_VPD Vital Product Data
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*
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* %PCI_CAP_ID_SLOTID Slot Identification
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*
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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*
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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*/
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int pci_find_capability(struct pci_device *dev, int cap)
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{
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uint16_t status;
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uint8_t pos, id;
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uint8_t hdr_type;
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int ttl = 48;
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pci_read_config_word(dev, PCI_STATUS, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
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switch (hdr_type & 0x7F) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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default:
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pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos);
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pci_read_config_byte(dev, PCI_CB_CAPABILITY_LIST, &pos);
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break;
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}
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while (ttl-- && pos >= 0x40) {
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pos &= ~3;
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pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id);
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#if DEBUG > 0
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printf("Capability: %d\n", id);
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#endif
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos);
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}
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return 0;
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}
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#endif /* CONFIG_PCI */
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