[pci] Add support for PCI Enhanced Allocation
Some embedded devices have immovable BARs, which are described via a PCI Enhanced Allocation capability. Signed-off-by: Michael Brown <mcb30@ipxe.org>
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Michael Brown
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/*
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* Copyright (C) 2016 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <errno.h>
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#include <ipxe/pci.h>
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#include <ipxe/pciea.h>
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/** @file
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*
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* PCI Enhanced Allocation
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*
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*/
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/**
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* Locate PCI Enhanced Allocation BAR equivalent entry
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*
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* @v pci PCI device
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* @v bei BAR equivalent indicator
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* @ret offset PCI Enhanced Allocation entry offset, or negative error
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*/
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static int pciea_offset ( struct pci_device *pci, unsigned int bei ) {
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uint8_t entries;
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uint32_t desc;
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unsigned int i;
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int offset;
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/* Locate Enhanced Allocation capability */
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offset = pci_find_capability ( pci, PCI_CAP_ID_EA );
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if ( offset < 0 )
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return offset;
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/* Get number of entries */
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pci_read_config_byte ( pci, ( offset + PCIEA_ENTRIES ), &entries );
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entries &= PCIEA_ENTRIES_MASK;
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/* Locate first entry */
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offset += PCIEA_FIRST;
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/* Search for a matching entry */
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for ( i = 0 ; i < entries ; i++ ) {
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/* Read entry descriptor */
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pci_read_config_dword ( pci, offset, &desc );
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/* Check for a matching entry */
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if ( ( desc & PCIEA_DESC_ENABLED ) &&
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( bei == PCIEA_DESC_BEI ( desc ) ) )
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return offset;
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/* Move to next entry */
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offset += ( ( PCIEA_DESC_SIZE ( desc ) + 1 ) << 2 );
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}
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return -ENOENT;
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}
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/**
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* Read PCI Enhanced Allocation BAR equivalent value
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*
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* @v pci PCI device
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* @v bei BAR equivalent indicator
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* @v low_offset Offset to low dword of value
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* @ret value BAR equivalent value
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*/
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static unsigned long pciea_bar_value ( struct pci_device *pci, unsigned int bei,
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unsigned int low_offset ) {
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uint32_t low;
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uint32_t high;
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int offset;
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/* Locate Enhanced Allocation offset for this BEI */
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offset = pciea_offset ( pci, bei );
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if ( offset < 0 )
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return 0;
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/* Read BAR equivalent */
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offset += low_offset;
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pci_read_config_dword ( pci, offset, &low );
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if ( low & PCIEA_LOW_ATTR_64BIT ) {
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offset += PCIEA_LOW_HIGH;
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pci_read_config_dword ( pci, offset, &high );
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if ( high ) {
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if ( sizeof ( unsigned long ) > sizeof ( uint32_t ) ) {
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return ( ( ( uint64_t ) high << 32 ) | low );
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} else {
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DBGC ( pci, PCI_FMT " unhandled 64-bit EA BAR "
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"%08x%08x\n",
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PCI_ARGS ( pci ), high, low );
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return 0;
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}
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}
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}
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return low;
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}
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/**
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* Find the start of a PCI Enhanced Allocation BAR equivalent
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*
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* @v pci PCI device
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* @v bei BAR equivalent indicator
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* @ret start BAR start address
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*
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* If the address exceeds the size of an unsigned long (i.e. if a
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* 64-bit BAR has a non-zero high dword on a 32-bit machine), the
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* return value will be zero.
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*/
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unsigned long pciea_bar_start ( struct pci_device *pci, unsigned int bei ) {
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unsigned long base;
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base = pciea_bar_value ( pci, bei, PCIEA_LOW_BASE );
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return ( base & ~PCIEA_LOW_ATTR_MASK );
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}
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/**
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* Find the size of a PCI Enhanced Allocation BAR equivalent
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*
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* @v pci PCI device
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* @v bei BAR equivalent indicator
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* @ret size BAR size
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*/
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unsigned long pciea_bar_size ( struct pci_device *pci, unsigned int bei ) {
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unsigned long limit;
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limit = pciea_bar_value ( pci, bei, PCIEA_LOW_LIMIT );
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return ( limit ? ( ( limit | PCIEA_LOW_ATTR_MASK ) + 1 ) : 0 );
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}
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@ -189,6 +189,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define ERRFILE_golan ( ERRFILE_DRIVER | 0x007d0000 )
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#define ERRFILE_flexboot_nodnic ( ERRFILE_DRIVER | 0x007e0000 )
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#define ERRFILE_virtio_pci ( ERRFILE_DRIVER | 0x007f0000 )
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#define ERRFILE_pciea ( ERRFILE_DRIVER | 0x00c00000 )
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#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
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#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )
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@ -94,6 +94,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define PCI_CAP_ID_VPD 0x03 /**< Vital product data */
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#define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */
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#define PCI_CAP_ID_EXP 0x10 /**< PCI Express */
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#define PCI_CAP_ID_EA 0x14 /**< Enhanced Allocation */
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/** Next capability */
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#define PCI_CAP_NEXT 0x01
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@ -0,0 +1,70 @@
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#ifndef _IPXE_PCIEA_H
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#define _IPXE_PCIEA_H
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/** @file
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*
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* PCI Enhanced Allocation
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/pci.h>
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/** Number of entries */
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#define PCIEA_ENTRIES 2
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#define PCIEA_ENTRIES_MASK 0x3f
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/** First entry */
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#define PCIEA_FIRST 4
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/** Entry descriptor */
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#define PCIEA_DESC 0
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/** Entry size */
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#define PCIEA_DESC_SIZE(desc) ( ( (desc) >> 0 ) & 0x7 )
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/** BAR equivalent indicator */
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#define PCIEA_DESC_BEI(desc) ( ( (desc) >> 4 ) & 0xf )
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/** BAR equivalent indicators */
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enum pciea_bei {
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PCIEA_BEI_BAR_0 = 0, /**< Standard BAR 0 */
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PCIEA_BEI_BAR_1 = 1, /**< Standard BAR 1 */
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PCIEA_BEI_BAR_2 = 2, /**< Standard BAR 2 */
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PCIEA_BEI_BAR_3 = 3, /**< Standard BAR 3 */
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PCIEA_BEI_BAR_4 = 4, /**< Standard BAR 4 */
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PCIEA_BEI_BAR_5 = 5, /**< Standard BAR 5 */
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PCIEA_BEI_ROM = 8, /**< Expansion ROM BAR */
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PCIEA_BEI_VF_BAR_0 = 9, /**< Virtual function BAR 0 */
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PCIEA_BEI_VF_BAR_1 = 10, /**< Virtual function BAR 1 */
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PCIEA_BEI_VF_BAR_2 = 11, /**< Virtual function BAR 2 */
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PCIEA_BEI_VF_BAR_3 = 12, /**< Virtual function BAR 3 */
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PCIEA_BEI_VF_BAR_4 = 13, /**< Virtual function BAR 4 */
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PCIEA_BEI_VF_BAR_5 = 14, /**< Virtual function BAR 5 */
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};
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/** Entry is enabled */
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#define PCIEA_DESC_ENABLED 0x80000000UL
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/** Base address low dword */
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#define PCIEA_LOW_BASE 4
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/** Limit low dword */
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#define PCIEA_LOW_LIMIT 8
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/** BAR is 64-bit */
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#define PCIEA_LOW_ATTR_64BIT 0x00000002UL
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/** Low dword attribute bit mask */
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#define PCIEA_LOW_ATTR_MASK 0x00000003UL
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/** Offset to high dwords */
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#define PCIEA_LOW_HIGH 8
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extern unsigned long pciea_bar_start ( struct pci_device *pci,
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unsigned int bei );
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extern unsigned long pciea_bar_size ( struct pci_device *pci,
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unsigned int bei );
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#endif /* _IPXE_PCIEA_H */
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