[romprefix] Further sanity checks for the PCI 3 runtime segment address
This extends the sanity checks on the runtime segment address provided
in %bx, first implemented in commit 5600955
.
We now allow the ROM to be placed anywhere above a000:0000 (rather
than c000:0000, as before), since this is the region allowed by the
PCI 3 spec. If the BIOS asks us to place the runtime image such that
it would overlap with the init-time image (which is explicitly
prohibited by the PCI 3 spec), then we assume that the BIOS is faulty
and ignore the provided runtime segment address.
Testing on a SuperMicro BIOS providing overlapping segment addresses
shows that ignoring the provided runtime segment address is safe to do
in these circumstances.
This commit is contained in:
parent
1bc2adea9a
commit
621101c36a
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@ -190,11 +190,11 @@ init:
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stc
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movw $0xb101, %ax
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int $0x1a
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jc 1f
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jc no_pci3
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cmpl $PCI_SIGNATURE, %edx
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jne 1f
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jne no_pci3
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testb %ah, %ah
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jnz 1f
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jnz no_pci3
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movw $init_message_pci, %si
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xorw %di, %di
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call print_message
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@ -205,20 +205,33 @@ init:
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movb %bl, %al
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call print_hex_byte
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cmpb $3, %bh
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jb 1f
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jb no_pci3
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/* PCI >=3.0: leave %gs as-is if sane */
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movw %gs, %ax
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cmpw $0xc000, %ax
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jae 2f
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/* PCI 3.0 with insane %gs value: print error and ignore %gs */
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cmpw $0xa000, %ax /* Insane if %gs < 0xa000 */
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jb pci3_insane
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movw %cs, %bx /* Sane if %cs == %gs */
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cmpw %bx, %ax
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je 1f
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movzbw romheader_size, %cx /* Sane if %cs+len <= %gs */
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shlw $5, %cx
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addw %cx, %bx
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cmpw %bx, %ax
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jae 1f
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movw %cs, %bx /* Sane if %gs+len <= %cs */
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addw %cx, %ax
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cmpw %bx, %ax
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jbe 1f
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pci3_insane: /* PCI 3.0 with insane %gs value: print error and ignore %gs */
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movb $'!', %al
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call print_character
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movw %gs, %ax
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call print_hex_word
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1: /* PCI <3.0: set %gs (runtime segment) = %cs (init-time segment) */
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no_pci3:
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/* PCI <3.0: set %gs (runtime segment) = %cs (init-time segment) */
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pushw %cs
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popw %gs
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2: popl %edi
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1: popl %edi
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popl %edx
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popl %ebx
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