[igb] Add igb driver
This commit adds an igb (Intel GigaBit) driver based on Intel source
code available at:
http://sourceforge.net/projects/e1000/
which is upstream source for the Linux kernel e1000 drivers, and
should support some PCIe e1000 variants.
Signed-off-by: Marty Connor <mdc@etherboot.org>
This commit is contained in:
Marty Connor
parent
be5392c93a
commit
5e829de055
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@ -60,6 +60,7 @@ SRCDIRS += drivers/bus
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SRCDIRS += drivers/net
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SRCDIRS += drivers/net/e1000
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SRCDIRS += drivers/net/e1000e
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SRCDIRS += drivers/net/igb
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SRCDIRS += drivers/net/phantom
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SRCDIRS += drivers/net/rtl818x
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SRCDIRS += drivers/net/ath5k
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@ -0,0 +1,32 @@
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/*******************************************************************************
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2008 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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FILE_LICENCE ( GPL2_ONLY );
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REQUIRE_OBJECT(igb_main);
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REQUIRE_OBJECT(igb_82575);
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@ -0,0 +1,324 @@
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2009 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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FILE_LICENCE ( GPL2_ONLY );
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/* Linux PRO/1000 Ethernet Driver main header file */
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#ifndef _IGB_H_
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#define _IGB_H_
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#include "igb_api.h"
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extern int igb_probe ( struct pci_device *pdev, const struct pci_device_id *ent);
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extern void igb_remove ( struct pci_device *pdev );
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struct igb_adapter;
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/* Interrupt defines */
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#define IGB_START_ITR 648 /* ~6000 ints/sec */
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/* Interrupt modes, as used by the IntMode paramter */
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#define IGB_INT_MODE_LEGACY 0
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#define IGB_INT_MODE_MSI 1
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#define IGB_INT_MODE_MSIX 2
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#define HW_PERF
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/* TX/RX descriptor defines */
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#define IGB_DEFAULT_TXD 256
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#define IGB_MIN_TXD 80
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#define IGB_MAX_TXD 4096
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#define IGB_DEFAULT_RXD 256
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#define IGB_MIN_RXD 80
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#define IGB_MAX_RXD 4096
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#define IGB_MIN_ITR_USECS 10 /* 100k irq/sec */
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#define IGB_MAX_ITR_USECS 8191 /* 120 irq/sec */
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#define NON_Q_VECTORS 1
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#define MAX_Q_VECTORS 8
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/* Transmit and receive queues */
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#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
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(hw->mac.type > e1000_82575 ? 8 : 4))
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#define IGB_ABS_MAX_TX_QUEUES 8
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#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
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#define IGB_MAX_VF_MC_ENTRIES 30
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#define IGB_MAX_VF_FUNCTIONS 8
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#define IGB_MAX_VFTA_ENTRIES 128
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#define IGB_MAX_UTA_ENTRIES 128
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#define MAX_EMULATION_MAC_ADDRS 16
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#define OUI_LEN 3
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struct vf_data_storage {
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unsigned char vf_mac_addresses[ETH_ALEN];
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u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
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u16 num_vf_mc_hashes;
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u16 default_vf_vlan_id;
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u16 vlans_enabled;
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unsigned char em_mac_addresses[MAX_EMULATION_MAC_ADDRS * ETH_ALEN];
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u32 uta_table_copy[IGB_MAX_UTA_ENTRIES];
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u32 flags;
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unsigned long last_nack;
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};
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#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
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#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
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#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
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/* RX descriptor control thresholds.
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* PTHRESH - MAC will consider prefetch if it has fewer than this number of
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* descriptors available in its onboard memory.
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* Setting this to 0 disables RX descriptor prefetch.
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* HTHRESH - MAC will only prefetch if there are at least this many descriptors
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* available in host memory.
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* If PTHRESH is 0, this should also be 0.
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* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
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* descriptors until either it has this many to write back, or the
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* ITR timer expires.
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*/
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#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
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#define IGB_RX_HTHRESH 8
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#define IGB_RX_WTHRESH 1
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#define IGB_TX_PTHRESH 8
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#define IGB_TX_HTHRESH 1
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#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
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adapter->msix_entries) ? 0 : 16)
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/* this is the size past which hardware will drop packets when setting LPE=0 */
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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
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/* Supported Rx Buffer Sizes */
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#define IGB_RXBUFFER_128 128 /* Used for packet split */
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#define IGB_RXBUFFER_256 256 /* Used for packet split */
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#define IGB_RXBUFFER_512 512
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#define IGB_RXBUFFER_1024 1024
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#define IGB_RXBUFFER_2048 2048
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#define IGB_RXBUFFER_4096 4096
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#define IGB_RXBUFFER_8192 8192
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#define IGB_RXBUFFER_16384 16384
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/* Packet Buffer allocations */
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#define IGB_PBA_BYTES_SHIFT 0xA
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#define IGB_TX_HEAD_ADDR_SHIFT 7
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#define IGB_PBA_TX_MASK 0xFFFF0000
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#define IGB_FC_PAUSE_TIME 0x0680 /* 858 usec */
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/* How many Tx Descriptors do we need to call netif_wake_queue ? */
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#define IGB_TX_QUEUE_WAKE 32
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define AUTO_ALL_MODES 0
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#define IGB_EEPROM_APME 0x0400
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#ifndef IGB_MASTER_SLAVE
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/* Switch to override PHY master/slave setting */
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#define IGB_MASTER_SLAVE e1000_ms_hw_default
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#endif
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#define IGB_MNG_VLAN_NONE -1
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer */
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struct igb_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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dma_addr_t page_dma;
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union {
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/* TX */
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struct {
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unsigned long time_stamp;
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u16 length;
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u16 next_to_watch;
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};
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#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT
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/* RX */
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struct {
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unsigned long page_offset;
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struct page *page;
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};
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#endif
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};
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};
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struct igb_queue_stats {
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u64 packets;
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u64 bytes;
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};
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struct igb_q_vector {
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struct igb_adapter *adapter; /* backlink */
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struct igb_ring *rx_ring;
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struct igb_ring *tx_ring;
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#if 0
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struct napi_struct napi;
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#endif
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u32 eims_value;
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u16 cpu;
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u16 itr_val;
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u8 set_itr;
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u8 itr_shift;
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void __iomem *itr_register;
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#if 0
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char name[IFNAMSIZ + 9];
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#endif
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#ifndef HAVE_NETDEV_NAPI_LIST
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struct net_device poll_dev;
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#endif
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};
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struct igb_ring {
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struct igb_q_vector *q_vector; /* backlink to q_vector */
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struct pci_dev *pdev; /* pci device for dma mapping */
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dma_addr_t dma; /* phys address of the ring */
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void *desc; /* descriptor ring memory */
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unsigned int size; /* length of desc. ring in bytes */
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u16 count; /* number of desc. in the ring */
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u16 next_to_use;
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u16 next_to_clean;
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u8 queue_index;
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u8 reg_idx;
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void __iomem *head;
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void __iomem *tail;
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struct igb_buffer *buffer_info; /* array of buffer info structs */
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unsigned int total_bytes;
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unsigned int total_packets;
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struct igb_queue_stats stats;
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union {
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/* TX */
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struct {
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unsigned int restart_queue;
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u32 ctx_idx;
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bool detect_tx_hung;
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};
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/* RX */
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struct {
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u64 hw_csum_err;
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u64 hw_csum_good;
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u32 rx_buffer_len;
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u16 rx_ps_hdr_size;
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bool rx_csum;
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#ifdef IGB_LRO
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struct net_lro_mgr lro_mgr;
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bool lro_used;
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#endif
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};
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};
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};
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#define IGB_ADVTXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
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#define IGB_DESC_UNUSED(R) \
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((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->next_to_clean - (R)->next_to_use - 1)
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#define E1000_RX_DESC_ADV(R, i) \
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(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
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#define E1000_TX_DESC_ADV(R, i) \
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(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
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#define E1000_TX_CTXTDESC_ADV(R, i) \
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(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
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#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
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#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
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#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
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#define MAX_MSIX_COUNT 10
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/* board specific private data structure */
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/* board specific private data structure */
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struct igb_adapter {
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/* OS defined structs */
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struct net_device *netdev;
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struct pci_device *pdev;
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struct net_device_stats net_stats;
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/* structs defined in e1000_hw.h */
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struct e1000_hw hw;
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struct e1000_phy_info phy_info;
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u32 min_frame_size;
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u32 max_frame_size;
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u32 wol;
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u32 pba;
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u32 max_hw_frame_size;
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bool fc_autoneg;
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unsigned int flags;
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unsigned int flags2;
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#define NUM_TX_DESC 8
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#define NUM_RX_DESC 8
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struct io_buffer *tx_iobuf[NUM_TX_DESC];
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struct io_buffer *rx_iobuf[NUM_RX_DESC];
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struct e1000_tx_desc *tx_base;
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struct e1000_rx_desc *rx_base;
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uint32_t tx_ring_size;
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uint32_t rx_ring_size;
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uint32_t tx_head;
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uint32_t tx_tail;
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uint32_t tx_fill_ctr;
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uint32_t rx_curr;
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uint32_t ioaddr;
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uint32_t irqno;
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uint32_t tx_int_delay;
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uint32_t tx_abs_int_delay;
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uint32_t txd_cmd;
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};
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#define IGB_FLAG_HAS_MSI (1 << 0)
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#define IGB_FLAG_MSI_ENABLE (1 << 1)
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#define IGB_FLAG_DCA_ENABLED (1 << 3)
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#define IGB_FLAG_LLI_PUSH (1 << 4)
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#define IGB_FLAG_IN_NETPOLL (1 << 5)
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#define IGB_FLAG_QUAD_PORT_A (1 << 6)
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#define IGB_FLAG_QUEUE_PAIRS (1 << 7)
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#define IGB_82576_TSYNC_SHIFT 19
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#endif /* _IGB_H_ */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,442 @@
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2009 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
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*******************************************************************************/
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FILE_LICENCE ( GPL2_ONLY );
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#ifndef _IGB_82575_H_
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#define _IGB_82575_H_
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#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
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(ID_LED_DEF1_DEF2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_OFF1_ON2))
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/*
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* Receive Address Register Count
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* Number of high/low register pairs in the RAR. The RAR (Receive Address
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* Registers) holds the directed and multicast addresses that we monitor.
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* These entries are also used for MAC-based filtering.
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*/
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/*
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* For 82576, there are an additional set of RARs that begin at an offset
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* separate from the first set of RARs.
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*/
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#define E1000_RAR_ENTRIES_82575 16
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#define E1000_RAR_ENTRIES_82576 24
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struct e1000_adv_data_desc {
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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union {
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u32 data;
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struct {
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u32 datalen :16; /* Data buffer length */
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u32 rsvd :4;
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u32 dtyp :4; /* Descriptor type */
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u32 dcmd :8; /* Descriptor command */
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} config;
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} lower;
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union {
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u32 data;
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struct {
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u32 status :4; /* Descriptor status */
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u32 idx :4;
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u32 popts :6; /* Packet Options */
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u32 paylen :18; /* Payload length */
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} options;
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} upper;
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};
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#define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */
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#define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */
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#define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */
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#define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */
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#define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */
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#define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */
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#define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */
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#define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */
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#define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */
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#define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */
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#define E1000_ADV_DCMD_RS 0x8 /* Report Status */
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#define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */
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#define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */
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/* Extended Device Control */
|
||||
#define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */
|
||||
|
||||
struct e1000_adv_context_desc {
|
||||
union {
|
||||
u32 ip_config;
|
||||
struct {
|
||||
u32 iplen :9;
|
||||
u32 maclen :7;
|
||||
u32 vlan_tag :16;
|
||||
} fields;
|
||||
} ip_setup;
|
||||
u32 seq_num;
|
||||
union {
|
||||
u64 l4_config;
|
||||
struct {
|
||||
u32 mkrloc :9;
|
||||
u32 tucmd :11;
|
||||
u32 dtyp :4;
|
||||
u32 adv :8;
|
||||
u32 rsvd :4;
|
||||
u32 idx :4;
|
||||
u32 l4len :8;
|
||||
u32 mss :16;
|
||||
} fields;
|
||||
} l4_setup;
|
||||
};
|
||||
|
||||
/* SRRCTL bit definitions */
|
||||
#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
|
||||
#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
|
||||
#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
|
||||
#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
|
||||
#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
|
||||
#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
|
||||
#define E1000_SRRCTL_DROP_EN 0x80000000
|
||||
|
||||
#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
|
||||
#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
|
||||
|
||||
#define E1000_TX_HEAD_WB_ENABLE 0x1
|
||||
#define E1000_TX_SEQNUM_WB_ENABLE 0x2
|
||||
|
||||
#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
|
||||
#define E1000_MRQC_ENABLE_VMDQ 0x00000003
|
||||
#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
|
||||
#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
|
||||
#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
|
||||
|
||||
#define E1000_VMRCTL_MIRROR_PORT_SHIFT 8
|
||||
#define E1000_VMRCTL_MIRROR_DSTPORT_MASK (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
|
||||
#define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0)
|
||||
#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE (1 << 1)
|
||||
#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
|
||||
|
||||
#define E1000_EICR_TX_QUEUE ( \
|
||||
E1000_EICR_TX_QUEUE0 | \
|
||||
E1000_EICR_TX_QUEUE1 | \
|
||||
E1000_EICR_TX_QUEUE2 | \
|
||||
E1000_EICR_TX_QUEUE3)
|
||||
|
||||
#define E1000_EICR_RX_QUEUE ( \
|
||||
E1000_EICR_RX_QUEUE0 | \
|
||||
E1000_EICR_RX_QUEUE1 | \
|
||||
E1000_EICR_RX_QUEUE2 | \
|
||||
E1000_EICR_RX_QUEUE3)
|
||||
|
||||
#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
|
||||
#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
|
||||
|
||||
#define EIMS_ENABLE_MASK ( \
|
||||
E1000_EIMS_RX_QUEUE | \
|
||||
E1000_EIMS_TX_QUEUE | \
|
||||
E1000_EIMS_TCP_TIMER | \
|
||||
E1000_EIMS_OTHER)
|
||||
|
||||
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
|
||||
#define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
|
||||
#define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
|
||||
#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
|
||||
#define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
|
||||
#define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
|
||||
#define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
|
||||
#define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
|
||||
#define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
|
||||
#define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
|
||||
#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
|
||||
|
||||
/* Receive Descriptor - Advanced */
|
||||
union e1000_adv_rx_desc {
|
||||
struct {
|
||||
__le64 pkt_addr; /* Packet buffer address */
|
||||
__le64 hdr_addr; /* Header buffer address */
|
||||
} read;
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
__le16 pkt_info; /*RSS type, Pkt type*/
|
||||
__le16 hdr_info; /* Split Header,
|
||||
* header buffer len*/
|
||||
} hs_rss;
|
||||
} lo_dword;
|
||||
union {
|
||||
__le32 rss; /* RSS Hash */
|
||||
struct {
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
} csum_ip;
|
||||
} hi_dword;
|
||||
} lower;
|
||||
struct {
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length; /* Packet length */
|
||||
__le16 vlan; /* VLAN tag */
|
||||
} upper;
|
||||
} wb; /* writeback */
|
||||
};
|
||||
|
||||
#define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
|
||||
#define E1000_RXDADV_RSSTYPE_SHIFT 12
|
||||
#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
|
||||
#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
|
||||
#define E1000_RXDADV_SPLITHEADER_EN 0x00001000
|
||||
#define E1000_RXDADV_SPH 0x8000
|
||||
#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
|
||||
#define E1000_RXDADV_ERR_HBO 0x00800000
|
||||
|
||||
/* RSS Hash results */
|
||||
#define E1000_RXDADV_RSSTYPE_NONE 0x00000000
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4 0x00000002
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6 0x00000005
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
|
||||
#define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
|
||||
#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
|
||||
|
||||
/* RSS Packet Types as indicated in the receive descriptor */
|
||||
#define E1000_RXDADV_PKTTYPE_NONE 0x00000000
|
||||
#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */
|
||||
#define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
|
||||
#define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
|
||||
|
||||
#define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
|
||||
#define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
|
||||
#define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
|
||||
#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
|
||||
|
||||
/* LinkSec results */
|
||||
/* Security Processing bit Indication */
|
||||
#define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
|
||||
#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
|
||||
|
||||
#define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
|
||||
#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000
|
||||
|
||||
/* Transmit Descriptor - Advanced */
|
||||
union e1000_adv_tx_desc {
|
||||
struct {
|
||||
__le64 buffer_addr; /* Address of descriptor's data buf */
|
||||
__le32 cmd_type_len;
|
||||
__le32 olinfo_status;
|
||||
} read;
|
||||
struct {
|
||||
__le64 rsvd; /* Reserved */
|
||||
__le32 nxtseq_seed;
|
||||
__le32 status;
|
||||
} wb;
|
||||
};
|
||||
|
||||
/* Adv Transmit Descriptor Config Masks */
|
||||
#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
|
||||
#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
|
||||
#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
|
||||
#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
|
||||
#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
|
||||
#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
|
||||
#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
|
||||
#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
|
||||
#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
|
||||
#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on packet */
|
||||
#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
|
||||
#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */
|
||||
#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
|
||||
#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
|
||||
#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
|
||||
#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
|
||||
|
||||
/* Context descriptors */
|
||||
struct e1000_adv_tx_context_desc {
|
||||
__le32 vlan_macip_lens;
|
||||
__le32 seqnum_seed;
|
||||
__le32 type_tucmd_mlhl;
|
||||
__le32 mss_l4len_idx;
|
||||
};
|
||||
|
||||
#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
|
||||
#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
|
||||
#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
|
||||
#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
|
||||
#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
|
||||
/* IPSec Encrypt Enable for ESP */
|
||||
#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
|
||||
#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
|
||||
#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
|
||||
#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
|
||||
/* Adv ctxt IPSec SA IDX mask */
|
||||
#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF
|
||||
/* Adv ctxt IPSec ESP len mask */
|
||||
#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF
|
||||
|
||||
/* Additional Transmit Descriptor Control definitions */
|
||||
#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
|
||||
#define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
|
||||
/* Tx Queue Arbitration Priority 0=low, 1=high */
|
||||
#define E1000_TXDCTL_PRIORITY 0x08000000
|
||||
|
||||
/* Additional Receive Descriptor Control definitions */
|
||||
#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
|
||||
#define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */
|
||||
|
||||
/* Direct Cache Access (DCA) definitions */
|
||||
#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
|
||||
#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
|
||||
|
||||
#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
|
||||
#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
|
||||
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
|
||||
#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
|
||||
#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
|
||||
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
|
||||
#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
|
||||
|
||||
#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
|
||||
#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
|
||||
#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
|
||||
#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
|
||||
|
||||
/* Additional interrupt register bit definitions */
|
||||
#define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */
|
||||
#define E1000_IMS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
|
||||
#define E1000_ICS_LSECPNS E1000_ICR_LSECPNS /* PN threshold - server */
|
||||
|
||||
/* ETQF register bit definitions */
|
||||
#define E1000_ETQF_FILTER_ENABLE (1 << 26)
|
||||
#define E1000_ETQF_IMM_INT (1 << 29)
|
||||
#define E1000_ETQF_1588 (1 << 30)
|
||||
#define E1000_ETQF_QUEUE_ENABLE (1 << 31)
|
||||
/*
|
||||
* ETQF filter list: one static filter per filter consumer. This is
|
||||
* to avoid filter collisions later. Add new filters
|
||||
* here!!
|
||||
*
|
||||
* Current filters:
|
||||
* EAPOL 802.1x (0x888e): Filter 0
|
||||
*/
|
||||
#define E1000_ETQF_FILTER_EAPOL 0
|
||||
|
||||
#define E1000_FTQF_VF_BP 0x00008000
|
||||
#define E1000_FTQF_1588_TIME_STAMP 0x08000000
|
||||
#define E1000_FTQF_MASK 0xF0000000
|
||||
#define E1000_FTQF_MASK_PROTO_BP 0x10000000
|
||||
#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
|
||||
#define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000
|
||||
#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
|
||||
|
||||
#define E1000_NVM_APME_82575 0x0400
|
||||
#define MAX_NUM_VFS 8
|
||||
|
||||
#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
|
||||
#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
|
||||
#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
|
||||
#define E1000_DTXSWC_LLE_SHIFT 16
|
||||
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
|
||||
|
||||
/* Easy defines for setting default pool, would normally be left a zero */
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
|
||||
#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
|
||||
|
||||
/* Other useful VMD_CTL register defines */
|
||||
#define E1000_VT_CTL_IGNORE_MAC (1 << 28)
|
||||
#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
|
||||
#define E1000_VT_CTL_VM_REPL_EN (1 << 30)
|
||||
|
||||
/* Per VM Offload register setup */
|
||||
#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
|
||||
#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
|
||||
#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
|
||||
#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
|
||||
#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
|
||||
#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
|
||||
#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
|
||||
#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
|
||||
#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
|
||||
#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
|
||||
|
||||
#define E1000_VLVF_ARRAY_SIZE 32
|
||||
#define E1000_VLVF_VLANID_MASK 0x00000FFF
|
||||
#define E1000_VLVF_POOLSEL_SHIFT 12
|
||||
#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
|
||||
#define E1000_VLVF_LVLAN 0x00100000
|
||||
#define E1000_VLVF_VLANID_ENABLE 0x80000000
|
||||
|
||||
#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
|
||||
|
||||
#define E1000_IOVCTL 0x05BBC
|
||||
#define E1000_IOVCTL_REUSE_VFQ 0x00000001
|
||||
|
||||
#define E1000_RPLOLR_STRVLAN 0x40000000
|
||||
#define E1000_RPLOLR_STRCRC 0x80000000
|
||||
|
||||
#define E1000_DTXCTL_8023LL 0x0004
|
||||
#define E1000_DTXCTL_VLAN_ADDED 0x0008
|
||||
#define E1000_DTXCTL_OOS_ENABLE 0x0010
|
||||
#define E1000_DTXCTL_MDP_EN 0x0020
|
||||
#define E1000_DTXCTL_SPOOF_INT 0x0040
|
||||
|
||||
#define ALL_QUEUES 0xFFFF
|
||||
|
||||
/* RX packet buffer size defines */
|
||||
#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
|
||||
void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
|
||||
void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
|
||||
|
||||
#endif /* _IGB_82575_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,166 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#ifndef _IGB_API_H_
|
||||
#define _IGB_API_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <gpxe/io.h>
|
||||
#include <errno.h>
|
||||
#include <byteswap.h>
|
||||
#include <gpxe/pci.h>
|
||||
#include <gpxe/malloc.h>
|
||||
#include <gpxe/if_ether.h>
|
||||
#include <gpxe/ethernet.h>
|
||||
#include <gpxe/iobuf.h>
|
||||
#include <gpxe/netdevice.h>
|
||||
|
||||
#include "igb_hw.h"
|
||||
|
||||
extern void igb_init_function_pointers_82575(struct e1000_hw *hw) __attribute__((weak));
|
||||
extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw) __attribute__((weak));
|
||||
extern void igb_init_function_pointers_vf(struct e1000_hw *hw) __attribute__((weak));
|
||||
extern void igb_shutdown_fiber_serdes_link(struct e1000_hw *hw) __attribute__((weak));
|
||||
|
||||
s32 igb_set_mac_type(struct e1000_hw *hw);
|
||||
s32 igb_setup_init_funcs(struct e1000_hw *hw, bool init_device);
|
||||
s32 igb_init_mac_params(struct e1000_hw *hw);
|
||||
s32 igb_init_nvm_params(struct e1000_hw *hw);
|
||||
s32 igb_init_phy_params(struct e1000_hw *hw);
|
||||
s32 igb_init_mbx_params(struct e1000_hw *hw);
|
||||
s32 igb_get_bus_info(struct e1000_hw *hw);
|
||||
void igb_clear_vfta(struct e1000_hw *hw);
|
||||
void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
|
||||
s32 igb_force_mac_fc(struct e1000_hw *hw);
|
||||
s32 igb_check_for_link(struct e1000_hw *hw);
|
||||
s32 igb_reset_hw(struct e1000_hw *hw);
|
||||
s32 igb_init_hw(struct e1000_hw *hw);
|
||||
s32 igb_setup_link(struct e1000_hw *hw);
|
||||
s32 igb_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
|
||||
u16 *duplex);
|
||||
s32 igb_disable_pcie_master(struct e1000_hw *hw);
|
||||
void igb_config_collision_dist(struct e1000_hw *hw);
|
||||
void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
|
||||
void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
|
||||
u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
|
||||
void igb_update_mc_addr_list(struct e1000_hw *hw,
|
||||
u8 *mc_addr_list, u32 mc_addr_count);
|
||||
s32 igb_setup_led(struct e1000_hw *hw);
|
||||
s32 igb_cleanup_led(struct e1000_hw *hw);
|
||||
s32 igb_check_reset_block(struct e1000_hw *hw);
|
||||
s32 igb_blink_led(struct e1000_hw *hw);
|
||||
s32 igb_led_on(struct e1000_hw *hw);
|
||||
s32 igb_led_off(struct e1000_hw *hw);
|
||||
s32 igb_id_led_init(struct e1000_hw *hw);
|
||||
void igb_reset_adaptive(struct e1000_hw *hw);
|
||||
void igb_update_adaptive(struct e1000_hw *hw);
|
||||
#if 0
|
||||
s32 igb_get_cable_length(struct e1000_hw *hw);
|
||||
#endif
|
||||
s32 igb_validate_mdi_setting(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
|
||||
u32 offset, u8 data);
|
||||
s32 igb_get_phy_info(struct e1000_hw *hw);
|
||||
void igb_release_phy(struct e1000_hw *hw);
|
||||
s32 igb_acquire_phy(struct e1000_hw *hw);
|
||||
s32 igb_phy_hw_reset(struct e1000_hw *hw);
|
||||
s32 igb_phy_commit(struct e1000_hw *hw);
|
||||
void igb_power_up_phy(struct e1000_hw *hw);
|
||||
void igb_power_down_phy(struct e1000_hw *hw);
|
||||
s32 igb_read_mac_addr(struct e1000_hw *hw);
|
||||
s32 igb_read_pba_num(struct e1000_hw *hw, u32 *part_num);
|
||||
void igb_reload_nvm(struct e1000_hw *hw);
|
||||
s32 igb_update_nvm_checksum(struct e1000_hw *hw);
|
||||
s32 igb_validate_nvm_checksum(struct e1000_hw *hw);
|
||||
s32 igb_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
|
||||
s32 igb_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
|
||||
u16 *data);
|
||||
s32 igb_wait_autoneg(struct e1000_hw *hw);
|
||||
s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
|
||||
s32 igb_set_d0_lplu_state(struct e1000_hw *hw, bool active);
|
||||
bool igb_check_mng_mode(struct e1000_hw *hw);
|
||||
bool igb_enable_tx_pkt_filtering(struct e1000_hw *hw);
|
||||
s32 igb_mng_enable_host_if(struct e1000_hw *hw);
|
||||
s32 igb_mng_host_if_write(struct e1000_hw *hw,
|
||||
u8 *buffer, u16 length, u16 offset, u8 *sum);
|
||||
s32 igb_mng_write_cmd_header(struct e1000_hw *hw,
|
||||
struct e1000_host_mng_command_header *hdr);
|
||||
s32 igb_mng_write_dhcp_info(struct e1000_hw * hw,
|
||||
u8 *buffer, u16 length);
|
||||
|
||||
/*
|
||||
* TBI_ACCEPT macro definition:
|
||||
*
|
||||
* This macro requires:
|
||||
* adapter = a pointer to struct e1000_hw
|
||||
* status = the 8 bit status field of the Rx descriptor with EOP set
|
||||
* error = the 8 bit error field of the Rx descriptor with EOP set
|
||||
* length = the sum of all the length fields of the Rx descriptors that
|
||||
* make up the current frame
|
||||
* last_byte = the last byte of the frame DMAed by the hardware
|
||||
* max_frame_length = the maximum frame length we want to accept.
|
||||
* min_frame_length = the minimum frame length we want to accept.
|
||||
*
|
||||
* This macro is a conditional that should be used in the interrupt
|
||||
* handler's Rx processing routine when RxErrors have been detected.
|
||||
*
|
||||
* Typical use:
|
||||
* ...
|
||||
* if (TBI_ACCEPT) {
|
||||
* accept_frame = true;
|
||||
* e1000_tbi_adjust_stats(adapter, MacAddress);
|
||||
* frame_length--;
|
||||
* } else {
|
||||
* accept_frame = false;
|
||||
* }
|
||||
* ...
|
||||
*/
|
||||
|
||||
/* The carrier extension symbol, as received by the NIC. */
|
||||
#define CARRIER_EXTENSION 0x0F
|
||||
|
||||
#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \
|
||||
(e1000_tbi_sbp_enabled_82543(a) && \
|
||||
(((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
|
||||
((last_byte) == CARRIER_EXTENSION) && \
|
||||
(((status) & E1000_RXD_STAT_VP) ? \
|
||||
(((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
|
||||
((length) <= (max_frame_size + 1))) : \
|
||||
(((length) > min_frame_size) && \
|
||||
((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
|
||||
|
||||
#endif /* _IGB_API_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,697 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#ifndef _IGB_HW_H_
|
||||
#define _IGB_HW_H_
|
||||
|
||||
#include "igb_osdep.h"
|
||||
#include "igb_regs.h"
|
||||
#include "igb_defines.h"
|
||||
|
||||
struct e1000_hw;
|
||||
|
||||
#define E1000_DEV_ID_82576 0x10C9
|
||||
#define E1000_DEV_ID_82576_FIBER 0x10E6
|
||||
#define E1000_DEV_ID_82576_SERDES 0x10E7
|
||||
#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
|
||||
#define E1000_DEV_ID_82576_NS 0x150A
|
||||
#define E1000_DEV_ID_82576_NS_SERDES 0x1518
|
||||
#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
|
||||
#define E1000_DEV_ID_82575EB_COPPER 0x10A7
|
||||
#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
|
||||
#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
|
||||
#define E1000_REVISION_0 0
|
||||
#define E1000_REVISION_1 1
|
||||
#define E1000_REVISION_2 2
|
||||
#define E1000_REVISION_3 3
|
||||
#define E1000_REVISION_4 4
|
||||
|
||||
#define E1000_FUNC_0 0
|
||||
#define E1000_FUNC_1 1
|
||||
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
|
||||
|
||||
enum e1000_mac_type {
|
||||
e1000_undefined = 0,
|
||||
e1000_82575,
|
||||
e1000_82576,
|
||||
e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
|
||||
};
|
||||
|
||||
enum e1000_media_type {
|
||||
e1000_media_type_unknown = 0,
|
||||
e1000_media_type_copper = 1,
|
||||
e1000_media_type_fiber = 2,
|
||||
e1000_media_type_internal_serdes = 3,
|
||||
e1000_num_media_types
|
||||
};
|
||||
|
||||
enum e1000_nvm_type {
|
||||
e1000_nvm_unknown = 0,
|
||||
e1000_nvm_none,
|
||||
e1000_nvm_eeprom_spi,
|
||||
e1000_nvm_flash_hw,
|
||||
e1000_nvm_flash_sw
|
||||
};
|
||||
|
||||
enum e1000_nvm_override {
|
||||
e1000_nvm_override_none = 0,
|
||||
e1000_nvm_override_spi_small,
|
||||
e1000_nvm_override_spi_large,
|
||||
};
|
||||
|
||||
enum e1000_phy_type {
|
||||
e1000_phy_unknown = 0,
|
||||
e1000_phy_none,
|
||||
e1000_phy_m88,
|
||||
e1000_phy_igp,
|
||||
e1000_phy_igp_2,
|
||||
e1000_phy_gg82563,
|
||||
e1000_phy_igp_3,
|
||||
e1000_phy_ife,
|
||||
e1000_phy_vf,
|
||||
};
|
||||
|
||||
enum e1000_bus_type {
|
||||
e1000_bus_type_unknown = 0,
|
||||
e1000_bus_type_pci,
|
||||
e1000_bus_type_pcix,
|
||||
e1000_bus_type_pci_express,
|
||||
e1000_bus_type_reserved
|
||||
};
|
||||
|
||||
enum e1000_bus_speed {
|
||||
e1000_bus_speed_unknown = 0,
|
||||
e1000_bus_speed_33,
|
||||
e1000_bus_speed_66,
|
||||
e1000_bus_speed_100,
|
||||
e1000_bus_speed_120,
|
||||
e1000_bus_speed_133,
|
||||
e1000_bus_speed_2500,
|
||||
e1000_bus_speed_5000,
|
||||
e1000_bus_speed_reserved
|
||||
};
|
||||
|
||||
enum e1000_bus_width {
|
||||
e1000_bus_width_unknown = 0,
|
||||
e1000_bus_width_pcie_x1,
|
||||
e1000_bus_width_pcie_x2,
|
||||
e1000_bus_width_pcie_x4 = 4,
|
||||
e1000_bus_width_pcie_x8 = 8,
|
||||
e1000_bus_width_32,
|
||||
e1000_bus_width_64,
|
||||
e1000_bus_width_reserved
|
||||
};
|
||||
|
||||
enum e1000_1000t_rx_status {
|
||||
e1000_1000t_rx_status_not_ok = 0,
|
||||
e1000_1000t_rx_status_ok,
|
||||
e1000_1000t_rx_status_undefined = 0xFF
|
||||
};
|
||||
|
||||
enum e1000_rev_polarity {
|
||||
e1000_rev_polarity_normal = 0,
|
||||
e1000_rev_polarity_reversed,
|
||||
e1000_rev_polarity_undefined = 0xFF
|
||||
};
|
||||
|
||||
enum e1000_fc_mode {
|
||||
e1000_fc_none = 0,
|
||||
e1000_fc_rx_pause,
|
||||
e1000_fc_tx_pause,
|
||||
e1000_fc_full,
|
||||
e1000_fc_default = 0xFF
|
||||
};
|
||||
|
||||
enum e1000_ms_type {
|
||||
e1000_ms_hw_default = 0,
|
||||
e1000_ms_force_master,
|
||||
e1000_ms_force_slave,
|
||||
e1000_ms_auto
|
||||
};
|
||||
|
||||
enum e1000_smart_speed {
|
||||
e1000_smart_speed_default = 0,
|
||||
e1000_smart_speed_on,
|
||||
e1000_smart_speed_off
|
||||
};
|
||||
|
||||
enum e1000_serdes_link_state {
|
||||
e1000_serdes_link_down = 0,
|
||||
e1000_serdes_link_autoneg_progress,
|
||||
e1000_serdes_link_autoneg_complete,
|
||||
e1000_serdes_link_forced_up
|
||||
};
|
||||
|
||||
/* Receive Descriptor */
|
||||
struct e1000_rx_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
__le16 length; /* Length of data DMAed into data buffer */
|
||||
__le16 csum; /* Packet checksum */
|
||||
u8 status; /* Descriptor status */
|
||||
u8 errors; /* Descriptor Errors */
|
||||
__le16 special;
|
||||
};
|
||||
|
||||
/* Receive Descriptor - Extended */
|
||||
union e1000_rx_desc_extended {
|
||||
struct {
|
||||
__le64 buffer_addr;
|
||||
__le64 reserved;
|
||||
} read;
|
||||
struct {
|
||||
struct {
|
||||
__le32 mrq; /* Multiple Rx Queues */
|
||||
union {
|
||||
__le32 rss; /* RSS Hash */
|
||||
struct {
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
} csum_ip;
|
||||
} hi_dword;
|
||||
} lower;
|
||||
struct {
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length;
|
||||
__le16 vlan; /* VLAN tag */
|
||||
} upper;
|
||||
} wb; /* writeback */
|
||||
};
|
||||
|
||||
#define MAX_PS_BUFFERS 4
|
||||
/* Receive Descriptor - Packet Split */
|
||||
union e1000_rx_desc_packet_split {
|
||||
struct {
|
||||
/* one buffer for protocol header(s), three data buffers */
|
||||
__le64 buffer_addr[MAX_PS_BUFFERS];
|
||||
} read;
|
||||
struct {
|
||||
struct {
|
||||
__le32 mrq; /* Multiple Rx Queues */
|
||||
union {
|
||||
__le32 rss; /* RSS Hash */
|
||||
struct {
|
||||
__le16 ip_id; /* IP id */
|
||||
__le16 csum; /* Packet Checksum */
|
||||
} csum_ip;
|
||||
} hi_dword;
|
||||
} lower;
|
||||
struct {
|
||||
__le32 status_error; /* ext status/error */
|
||||
__le16 length0; /* length of buffer 0 */
|
||||
__le16 vlan; /* VLAN tag */
|
||||
} middle;
|
||||
struct {
|
||||
__le16 header_status;
|
||||
__le16 length[3]; /* length of buffers 1-3 */
|
||||
} upper;
|
||||
__le64 reserved;
|
||||
} wb; /* writeback */
|
||||
};
|
||||
|
||||
/* Transmit Descriptor */
|
||||
struct e1000_tx_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
__le16 length; /* Data buffer length */
|
||||
u8 cso; /* Checksum offset */
|
||||
u8 cmd; /* Descriptor control */
|
||||
} flags;
|
||||
} lower;
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
u8 status; /* Descriptor status */
|
||||
u8 css; /* Checksum start */
|
||||
__le16 special;
|
||||
} fields;
|
||||
} upper;
|
||||
};
|
||||
|
||||
/* Offload Context Descriptor */
|
||||
struct e1000_context_desc {
|
||||
union {
|
||||
__le32 ip_config;
|
||||
struct {
|
||||
u8 ipcss; /* IP checksum start */
|
||||
u8 ipcso; /* IP checksum offset */
|
||||
__le16 ipcse; /* IP checksum end */
|
||||
} ip_fields;
|
||||
} lower_setup;
|
||||
union {
|
||||
__le32 tcp_config;
|
||||
struct {
|
||||
u8 tucss; /* TCP checksum start */
|
||||
u8 tucso; /* TCP checksum offset */
|
||||
__le16 tucse; /* TCP checksum end */
|
||||
} tcp_fields;
|
||||
} upper_setup;
|
||||
__le32 cmd_and_length;
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
u8 status; /* Descriptor status */
|
||||
u8 hdr_len; /* Header length */
|
||||
__le16 mss; /* Maximum segment size */
|
||||
} fields;
|
||||
} tcp_seg_setup;
|
||||
};
|
||||
|
||||
/* Offload data descriptor */
|
||||
struct e1000_data_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's buffer address */
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
__le16 length; /* Data buffer length */
|
||||
u8 typ_len_ext;
|
||||
u8 cmd;
|
||||
} flags;
|
||||
} lower;
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
u8 status; /* Descriptor status */
|
||||
u8 popts; /* Packet Options */
|
||||
__le16 special;
|
||||
} fields;
|
||||
} upper;
|
||||
};
|
||||
|
||||
/* Statistics counters collected by the MAC */
|
||||
struct e1000_hw_stats {
|
||||
u64 crcerrs;
|
||||
u64 algnerrc;
|
||||
u64 symerrs;
|
||||
u64 rxerrc;
|
||||
u64 mpc;
|
||||
u64 scc;
|
||||
u64 ecol;
|
||||
u64 mcc;
|
||||
u64 latecol;
|
||||
u64 colc;
|
||||
u64 dc;
|
||||
u64 tncrs;
|
||||
u64 sec;
|
||||
u64 cexterr;
|
||||
u64 rlec;
|
||||
u64 xonrxc;
|
||||
u64 xontxc;
|
||||
u64 xoffrxc;
|
||||
u64 xofftxc;
|
||||
u64 fcruc;
|
||||
u64 prc64;
|
||||
u64 prc127;
|
||||
u64 prc255;
|
||||
u64 prc511;
|
||||
u64 prc1023;
|
||||
u64 prc1522;
|
||||
u64 gprc;
|
||||
u64 bprc;
|
||||
u64 mprc;
|
||||
u64 gptc;
|
||||
u64 gorc;
|
||||
u64 gotc;
|
||||
u64 rnbc;
|
||||
u64 ruc;
|
||||
u64 rfc;
|
||||
u64 roc;
|
||||
u64 rjc;
|
||||
u64 mgprc;
|
||||
u64 mgpdc;
|
||||
u64 mgptc;
|
||||
u64 tor;
|
||||
u64 tot;
|
||||
u64 tpr;
|
||||
u64 tpt;
|
||||
u64 ptc64;
|
||||
u64 ptc127;
|
||||
u64 ptc255;
|
||||
u64 ptc511;
|
||||
u64 ptc1023;
|
||||
u64 ptc1522;
|
||||
u64 mptc;
|
||||
u64 bptc;
|
||||
u64 tsctc;
|
||||
u64 tsctfc;
|
||||
u64 iac;
|
||||
u64 icrxptc;
|
||||
u64 icrxatc;
|
||||
u64 ictxptc;
|
||||
u64 ictxatc;
|
||||
u64 ictxqec;
|
||||
u64 ictxqmtc;
|
||||
u64 icrxdmtc;
|
||||
u64 icrxoc;
|
||||
u64 cbtmpc;
|
||||
u64 htdpmc;
|
||||
u64 cbrdpc;
|
||||
u64 cbrmpc;
|
||||
u64 rpthc;
|
||||
u64 hgptc;
|
||||
u64 htcbdpc;
|
||||
u64 hgorc;
|
||||
u64 hgotc;
|
||||
u64 lenerrs;
|
||||
u64 scvpc;
|
||||
u64 hrmpc;
|
||||
u64 doosync;
|
||||
};
|
||||
|
||||
|
||||
struct e1000_phy_stats {
|
||||
u32 idle_errors;
|
||||
u32 receive_errors;
|
||||
};
|
||||
|
||||
struct e1000_host_mng_dhcp_cookie {
|
||||
u32 signature;
|
||||
u8 status;
|
||||
u8 reserved0;
|
||||
u16 vlan_id;
|
||||
u32 reserved1;
|
||||
u16 reserved2;
|
||||
u8 reserved3;
|
||||
u8 checksum;
|
||||
};
|
||||
|
||||
/* Host Interface "Rev 1" */
|
||||
struct e1000_host_command_header {
|
||||
u8 command_id;
|
||||
u8 command_length;
|
||||
u8 command_options;
|
||||
u8 checksum;
|
||||
};
|
||||
|
||||
#define E1000_HI_MAX_DATA_LENGTH 252
|
||||
struct e1000_host_command_info {
|
||||
struct e1000_host_command_header command_header;
|
||||
u8 command_data[E1000_HI_MAX_DATA_LENGTH];
|
||||
};
|
||||
|
||||
/* Host Interface "Rev 2" */
|
||||
struct e1000_host_mng_command_header {
|
||||
u8 command_id;
|
||||
u8 checksum;
|
||||
u16 reserved1;
|
||||
u16 reserved2;
|
||||
u16 command_length;
|
||||
};
|
||||
|
||||
#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
|
||||
struct e1000_host_mng_command_info {
|
||||
struct e1000_host_mng_command_header command_header;
|
||||
u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
|
||||
};
|
||||
|
||||
#include "igb_mac.h"
|
||||
#include "igb_phy.h"
|
||||
#include "igb_nvm.h"
|
||||
#include "igb_manage.h"
|
||||
|
||||
struct e1000_mac_operations {
|
||||
/* Function pointers for the MAC. */
|
||||
s32 (*init_params)(struct e1000_hw *);
|
||||
s32 (*id_led_init)(struct e1000_hw *);
|
||||
s32 (*blink_led)(struct e1000_hw *);
|
||||
s32 (*check_for_link)(struct e1000_hw *);
|
||||
bool (*check_mng_mode)(struct e1000_hw *hw);
|
||||
s32 (*cleanup_led)(struct e1000_hw *);
|
||||
void (*clear_hw_cntrs)(struct e1000_hw *);
|
||||
void (*clear_vfta)(struct e1000_hw *);
|
||||
s32 (*get_bus_info)(struct e1000_hw *);
|
||||
void (*set_lan_id)(struct e1000_hw *);
|
||||
s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
|
||||
s32 (*led_on)(struct e1000_hw *);
|
||||
s32 (*led_off)(struct e1000_hw *);
|
||||
void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
|
||||
s32 (*reset_hw)(struct e1000_hw *);
|
||||
s32 (*init_hw)(struct e1000_hw *);
|
||||
void (*shutdown_serdes)(struct e1000_hw *);
|
||||
s32 (*setup_link)(struct e1000_hw *);
|
||||
s32 (*setup_physical_interface)(struct e1000_hw *);
|
||||
s32 (*setup_led)(struct e1000_hw *);
|
||||
void (*write_vfta)(struct e1000_hw *, u32, u32);
|
||||
void (*mta_set)(struct e1000_hw *, u32);
|
||||
void (*config_collision_dist)(struct e1000_hw *);
|
||||
void (*rar_set)(struct e1000_hw *, u8*, u32);
|
||||
s32 (*read_mac_addr)(struct e1000_hw *);
|
||||
s32 (*validate_mdi_setting)(struct e1000_hw *);
|
||||
s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
|
||||
s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
|
||||
struct e1000_host_mng_command_header*);
|
||||
s32 (*mng_enable_host_if)(struct e1000_hw *);
|
||||
s32 (*wait_autoneg)(struct e1000_hw *);
|
||||
};
|
||||
|
||||
struct e1000_phy_operations {
|
||||
s32 (*init_params)(struct e1000_hw *);
|
||||
s32 (*acquire)(struct e1000_hw *);
|
||||
s32 (*check_polarity)(struct e1000_hw *);
|
||||
s32 (*check_reset_block)(struct e1000_hw *);
|
||||
s32 (*commit)(struct e1000_hw *);
|
||||
#if 0
|
||||
s32 (*force_speed_duplex)(struct e1000_hw *);
|
||||
#endif
|
||||
s32 (*get_cfg_done)(struct e1000_hw *hw);
|
||||
#if 0
|
||||
s32 (*get_cable_length)(struct e1000_hw *);
|
||||
#endif
|
||||
s32 (*get_info)(struct e1000_hw *);
|
||||
s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
|
||||
s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
|
||||
void (*release)(struct e1000_hw *);
|
||||
s32 (*reset)(struct e1000_hw *);
|
||||
s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
|
||||
s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
|
||||
s32 (*write_reg)(struct e1000_hw *, u32, u16);
|
||||
s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
|
||||
void (*power_up)(struct e1000_hw *);
|
||||
void (*power_down)(struct e1000_hw *);
|
||||
};
|
||||
|
||||
struct e1000_nvm_operations {
|
||||
s32 (*init_params)(struct e1000_hw *);
|
||||
s32 (*acquire)(struct e1000_hw *);
|
||||
s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
|
||||
void (*release)(struct e1000_hw *);
|
||||
void (*reload)(struct e1000_hw *);
|
||||
s32 (*update)(struct e1000_hw *);
|
||||
s32 (*valid_led_default)(struct e1000_hw *, u16 *);
|
||||
s32 (*validate)(struct e1000_hw *);
|
||||
s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
|
||||
};
|
||||
|
||||
struct e1000_mac_info {
|
||||
struct e1000_mac_operations ops;
|
||||
u8 addr[6];
|
||||
u8 perm_addr[6];
|
||||
|
||||
enum e1000_mac_type type;
|
||||
|
||||
u32 collision_delta;
|
||||
u32 ledctl_default;
|
||||
u32 ledctl_mode1;
|
||||
u32 ledctl_mode2;
|
||||
u32 mc_filter_type;
|
||||
u32 tx_packet_delta;
|
||||
u32 txcw;
|
||||
|
||||
u16 current_ifs_val;
|
||||
u16 ifs_max_val;
|
||||
u16 ifs_min_val;
|
||||
u16 ifs_ratio;
|
||||
u16 ifs_step_size;
|
||||
u16 mta_reg_count;
|
||||
u16 uta_reg_count;
|
||||
|
||||
/* Maximum size of the MTA register table in all supported adapters */
|
||||
#define MAX_MTA_REG 128
|
||||
u32 mta_shadow[MAX_MTA_REG];
|
||||
u16 rar_entry_count;
|
||||
|
||||
u8 forced_speed_duplex;
|
||||
|
||||
bool adaptive_ifs;
|
||||
bool arc_subsystem_valid;
|
||||
bool asf_firmware_present;
|
||||
bool autoneg;
|
||||
bool autoneg_failed;
|
||||
bool get_link_status;
|
||||
bool in_ifs_mode;
|
||||
enum e1000_serdes_link_state serdes_link_state;
|
||||
bool serdes_has_link;
|
||||
bool tx_pkt_filtering;
|
||||
};
|
||||
|
||||
struct e1000_phy_info {
|
||||
struct e1000_phy_operations ops;
|
||||
enum e1000_phy_type type;
|
||||
|
||||
enum e1000_1000t_rx_status local_rx;
|
||||
enum e1000_1000t_rx_status remote_rx;
|
||||
enum e1000_ms_type ms_type;
|
||||
enum e1000_ms_type original_ms_type;
|
||||
enum e1000_rev_polarity cable_polarity;
|
||||
enum e1000_smart_speed smart_speed;
|
||||
|
||||
u32 addr;
|
||||
u32 id;
|
||||
u32 reset_delay_us; /* in usec */
|
||||
u32 revision;
|
||||
|
||||
enum e1000_media_type media_type;
|
||||
|
||||
u16 autoneg_advertised;
|
||||
u16 autoneg_mask;
|
||||
u16 cable_length;
|
||||
u16 max_cable_length;
|
||||
u16 min_cable_length;
|
||||
|
||||
u8 mdix;
|
||||
|
||||
bool disable_polarity_correction;
|
||||
bool is_mdix;
|
||||
bool polarity_correction;
|
||||
bool reset_disable;
|
||||
bool speed_downgraded;
|
||||
bool autoneg_wait_to_complete;
|
||||
};
|
||||
|
||||
struct e1000_nvm_info {
|
||||
struct e1000_nvm_operations ops;
|
||||
enum e1000_nvm_type type;
|
||||
enum e1000_nvm_override override;
|
||||
|
||||
u32 flash_bank_size;
|
||||
u32 flash_base_addr;
|
||||
|
||||
u16 word_size;
|
||||
u16 delay_usec;
|
||||
u16 address_bits;
|
||||
u16 opcode_bits;
|
||||
u16 page_size;
|
||||
};
|
||||
|
||||
struct e1000_bus_info {
|
||||
enum e1000_bus_type type;
|
||||
enum e1000_bus_speed speed;
|
||||
enum e1000_bus_width width;
|
||||
|
||||
u16 func;
|
||||
u16 pci_cmd_word;
|
||||
};
|
||||
|
||||
struct e1000_fc_info {
|
||||
u32 high_water; /* Flow control high-water mark */
|
||||
u32 low_water; /* Flow control low-water mark */
|
||||
u16 pause_time; /* Flow control pause timer */
|
||||
bool send_xon; /* Flow control send XON */
|
||||
bool strict_ieee; /* Strict IEEE mode */
|
||||
enum e1000_fc_mode current_mode; /* FC mode in effect */
|
||||
enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
|
||||
};
|
||||
|
||||
struct e1000_mbx_operations {
|
||||
s32 (*init_params)(struct e1000_hw *hw);
|
||||
s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
|
||||
s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
|
||||
s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
|
||||
s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
|
||||
s32 (*check_for_msg)(struct e1000_hw *, u16);
|
||||
s32 (*check_for_ack)(struct e1000_hw *, u16);
|
||||
s32 (*check_for_rst)(struct e1000_hw *, u16);
|
||||
};
|
||||
|
||||
struct e1000_mbx_stats {
|
||||
u32 msgs_tx;
|
||||
u32 msgs_rx;
|
||||
|
||||
u32 acks;
|
||||
u32 reqs;
|
||||
u32 rsts;
|
||||
};
|
||||
|
||||
struct e1000_mbx_info {
|
||||
struct e1000_mbx_operations ops;
|
||||
struct e1000_mbx_stats stats;
|
||||
u32 timeout;
|
||||
u32 usec_delay;
|
||||
u16 size;
|
||||
};
|
||||
|
||||
struct e1000_dev_spec_82575 {
|
||||
bool sgmii_active;
|
||||
bool global_device_reset;
|
||||
};
|
||||
|
||||
struct e1000_dev_spec_vf {
|
||||
u32 vf_number;
|
||||
u32 v2p_mailbox;
|
||||
};
|
||||
|
||||
|
||||
struct e1000_hw {
|
||||
void *back;
|
||||
|
||||
u8 __iomem *hw_addr;
|
||||
u8 __iomem *flash_address;
|
||||
unsigned long io_base;
|
||||
|
||||
struct e1000_mac_info mac;
|
||||
struct e1000_fc_info fc;
|
||||
struct e1000_phy_info phy;
|
||||
struct e1000_nvm_info nvm;
|
||||
struct e1000_bus_info bus;
|
||||
struct e1000_mbx_info mbx;
|
||||
struct e1000_host_mng_dhcp_cookie mng_cookie;
|
||||
|
||||
union {
|
||||
struct e1000_dev_spec_82575 _82575;
|
||||
struct e1000_dev_spec_vf vf;
|
||||
} dev_spec;
|
||||
|
||||
u16 device_id;
|
||||
u16 subsystem_vendor_id;
|
||||
u16 subsystem_device_id;
|
||||
u16 vendor_id;
|
||||
|
||||
u8 revision_id;
|
||||
};
|
||||
|
||||
#include "igb_82575.h"
|
||||
|
||||
/* These functions must be implemented by drivers */
|
||||
s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
|
||||
s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
|
||||
|
||||
#endif /* _IGB_HW_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,82 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#ifndef _IGB_MAC_H_
|
||||
#define _IGB_MAC_H_
|
||||
|
||||
/*
|
||||
* Functions that should not be called directly from drivers but can be used
|
||||
* by other files in this 'shared code'
|
||||
*/
|
||||
void igb_init_mac_ops_generic(struct e1000_hw *hw);
|
||||
s32 igb_blink_led_generic(struct e1000_hw *hw);
|
||||
s32 igb_check_for_copper_link_generic(struct e1000_hw *hw);
|
||||
s32 igb_check_for_fiber_link_generic(struct e1000_hw *hw);
|
||||
s32 igb_check_for_serdes_link_generic(struct e1000_hw *hw);
|
||||
s32 igb_cleanup_led_generic(struct e1000_hw *hw);
|
||||
s32 igb_config_fc_after_link_up_generic(struct e1000_hw *hw);
|
||||
s32 igb_disable_pcie_master_generic(struct e1000_hw *hw);
|
||||
s32 igb_force_mac_fc_generic(struct e1000_hw *hw);
|
||||
s32 igb_get_auto_rd_done_generic(struct e1000_hw *hw);
|
||||
s32 igb_get_bus_info_pcie_generic(struct e1000_hw *hw);
|
||||
void igb_set_lan_id_single_port(struct e1000_hw *hw);
|
||||
s32 igb_get_hw_semaphore_generic(struct e1000_hw *hw);
|
||||
s32 igb_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
|
||||
u16 *duplex);
|
||||
s32 igb_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
|
||||
u16 *speed, u16 *duplex);
|
||||
s32 igb_id_led_init_generic(struct e1000_hw *hw);
|
||||
s32 igb_led_on_generic(struct e1000_hw *hw);
|
||||
s32 igb_led_off_generic(struct e1000_hw *hw);
|
||||
void igb_update_mc_addr_list_generic(struct e1000_hw *hw,
|
||||
u8 *mc_addr_list, u32 mc_addr_count);
|
||||
s32 igb_set_fc_watermarks_generic(struct e1000_hw *hw);
|
||||
s32 igb_setup_fiber_serdes_link_generic(struct e1000_hw *hw);
|
||||
s32 igb_setup_led_generic(struct e1000_hw *hw);
|
||||
s32 igb_setup_link_generic(struct e1000_hw *hw);
|
||||
s32 igb_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
|
||||
u32 offset, u8 data);
|
||||
|
||||
u32 igb_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);
|
||||
|
||||
void igb_clear_hw_cntrs_base_generic(struct e1000_hw *hw);
|
||||
void igb_clear_vfta_generic(struct e1000_hw *hw);
|
||||
void igb_config_collision_dist_generic(struct e1000_hw *hw);
|
||||
void igb_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);
|
||||
void igb_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
|
||||
void igb_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
|
||||
void igb_put_hw_semaphore_generic(struct e1000_hw *hw);
|
||||
void igb_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
|
||||
s32 igb_check_alt_mac_addr_generic(struct e1000_hw *hw);
|
||||
void igb_reset_adaptive_generic(struct e1000_hw *hw);
|
||||
void igb_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);
|
||||
void igb_update_adaptive_generic(struct e1000_hw *hw);
|
||||
void igb_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
|
||||
|
||||
#endif /* _IGB_MAC_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,388 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#include "igb.h"
|
||||
|
||||
#if 0
|
||||
|
||||
static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
|
||||
|
||||
/**
|
||||
* e1000_calculate_checksum - Calculate checksum for buffer
|
||||
* @buffer: pointer to EEPROM
|
||||
* @length: size of EEPROM to calculate a checksum for
|
||||
*
|
||||
* Calculates the checksum for some buffer on a specified length. The
|
||||
* checksum calculated is returned.
|
||||
**/
|
||||
static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
|
||||
{
|
||||
u32 i;
|
||||
u8 sum = 0;
|
||||
|
||||
DEBUGFUNC("igb_calculate_checksum");
|
||||
|
||||
if (!buffer)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < length; i++)
|
||||
sum += buffer[i];
|
||||
|
||||
return (u8) (0 - sum);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_enable_host_if_generic - Checks host interface is enabled
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
|
||||
*
|
||||
* This function checks whether the HOST IF is enabled for command operation
|
||||
* and also checks whether the previous command is completed. It busy waits
|
||||
* in case of previous command is not completed.
|
||||
**/
|
||||
s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 hicr;
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
u8 i;
|
||||
|
||||
DEBUGFUNC("igb_mng_enable_host_if_generic");
|
||||
|
||||
/* Check that the host interface is enabled. */
|
||||
hicr = E1000_READ_REG(hw, E1000_HICR);
|
||||
if ((hicr & E1000_HICR_EN) == 0) {
|
||||
DEBUGOUT("E1000_HOST_EN bit disabled.\n");
|
||||
ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
goto out;
|
||||
}
|
||||
/* check the previous command is completed */
|
||||
for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
|
||||
hicr = E1000_READ_REG(hw, E1000_HICR);
|
||||
if (!(hicr & E1000_HICR_C))
|
||||
break;
|
||||
msec_delay_irq(1);
|
||||
}
|
||||
|
||||
if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
|
||||
DEBUGOUT("Previous command timeout failed .\n");
|
||||
ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_check_mng_mode_generic - Generic check management mode
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Reads the firmware semaphore register and returns true (>0) if
|
||||
* manageability is enabled, else false (0).
|
||||
**/
|
||||
bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 fwsm;
|
||||
|
||||
DEBUGFUNC("igb_check_mng_mode_generic");
|
||||
|
||||
fwsm = E1000_READ_REG(hw, E1000_FWSM);
|
||||
|
||||
return (fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Enables packet filtering on transmit packets if manageability is enabled
|
||||
* and host interface is enabled.
|
||||
**/
|
||||
bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
|
||||
u32 *buffer = (u32 *)&hw->mng_cookie;
|
||||
u32 offset;
|
||||
s32 ret_val, hdr_csum, csum;
|
||||
u8 i, len;
|
||||
bool tx_filter = true;
|
||||
|
||||
DEBUGFUNC("igb_enable_tx_pkt_filtering_generic");
|
||||
|
||||
/* No manageability, no filtering */
|
||||
if (!hw->mac.ops.check_mng_mode(hw)) {
|
||||
tx_filter = false;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we can't read from the host interface for whatever
|
||||
* reason, disable filtering.
|
||||
*/
|
||||
ret_val = hw->mac.ops.mng_enable_host_if(hw);
|
||||
if (ret_val != E1000_SUCCESS) {
|
||||
tx_filter = false;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Read in the header. Length and offset are in dwords. */
|
||||
len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
|
||||
offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
|
||||
for (i = 0; i < len; i++) {
|
||||
*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
|
||||
E1000_HOST_IF,
|
||||
offset + i);
|
||||
}
|
||||
hdr_csum = hdr->checksum;
|
||||
hdr->checksum = 0;
|
||||
csum = e1000_calculate_checksum((u8 *)hdr,
|
||||
E1000_MNG_DHCP_COOKIE_LENGTH);
|
||||
/*
|
||||
* If either the checksums or signature don't match, then
|
||||
* the cookie area isn't considered valid, in which case we
|
||||
* take the safe route of assuming Tx filtering is enabled.
|
||||
*/
|
||||
if (hdr_csum != csum)
|
||||
goto out;
|
||||
if (hdr->signature != E1000_IAMT_SIGNATURE)
|
||||
goto out;
|
||||
|
||||
/* Cookie area is valid, make the final check for filtering. */
|
||||
if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
|
||||
tx_filter = false;
|
||||
|
||||
out:
|
||||
hw->mac.tx_pkt_filtering = tx_filter;
|
||||
return tx_filter;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
|
||||
* @hw: pointer to the HW structure
|
||||
* @buffer: pointer to the host interface
|
||||
* @length: size of the buffer
|
||||
*
|
||||
* Writes the DHCP information to the host interface.
|
||||
**/
|
||||
s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
|
||||
u16 length)
|
||||
{
|
||||
struct e1000_host_mng_command_header hdr;
|
||||
s32 ret_val;
|
||||
u32 hicr;
|
||||
|
||||
DEBUGFUNC("igb_mng_write_dhcp_info_generic");
|
||||
|
||||
hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
|
||||
hdr.command_length = length;
|
||||
hdr.reserved1 = 0;
|
||||
hdr.reserved2 = 0;
|
||||
hdr.checksum = 0;
|
||||
|
||||
/* Enable the host interface */
|
||||
ret_val = hw->mac.ops.mng_enable_host_if(hw);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Populate the host interface with the contents of "buffer". */
|
||||
ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
|
||||
sizeof(hdr), &(hdr.checksum));
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Write the manageability command header */
|
||||
ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Tell the ARC a new command is pending. */
|
||||
hicr = E1000_READ_REG(hw, E1000_HICR);
|
||||
E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_write_cmd_header_generic - Writes manageability command header
|
||||
* @hw: pointer to the HW structure
|
||||
* @hdr: pointer to the host interface command header
|
||||
*
|
||||
* Writes the command header after does the checksum calculation.
|
||||
**/
|
||||
s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
|
||||
struct e1000_host_mng_command_header *hdr)
|
||||
{
|
||||
u16 i, length = sizeof(struct e1000_host_mng_command_header);
|
||||
|
||||
DEBUGFUNC("igb_mng_write_cmd_header_generic");
|
||||
|
||||
/* Write the whole command header structure with new checksum. */
|
||||
|
||||
hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
|
||||
|
||||
length >>= 2;
|
||||
/* Write the relevant command block into the ram area. */
|
||||
for (i = 0; i < length; i++) {
|
||||
E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
|
||||
*((u32 *) hdr + i));
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
}
|
||||
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_mng_host_if_write_generic - Write to the manageability host interface
|
||||
* @hw: pointer to the HW structure
|
||||
* @buffer: pointer to the host interface buffer
|
||||
* @length: size of the buffer
|
||||
* @offset: location in the buffer to write to
|
||||
* @sum: sum of the data (not checksum)
|
||||
*
|
||||
* This function writes the buffer content at the offset given on the host if.
|
||||
* It also does alignment considerations to do the writes in most efficient
|
||||
* way. Also fills up the sum of the buffer in *buffer parameter.
|
||||
**/
|
||||
s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
|
||||
u16 length, u16 offset, u8 *sum)
|
||||
{
|
||||
u8 *tmp;
|
||||
u8 *bufptr = buffer;
|
||||
u32 data = 0;
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
u16 remaining, i, j, prev_bytes;
|
||||
|
||||
DEBUGFUNC("igb_mng_host_if_write_generic");
|
||||
|
||||
/* sum = only sum of the data and it is not checksum */
|
||||
|
||||
if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
|
||||
ret_val = -E1000_ERR_PARAM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
tmp = (u8 *)&data;
|
||||
prev_bytes = offset & 0x3;
|
||||
offset >>= 2;
|
||||
|
||||
if (prev_bytes) {
|
||||
data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
|
||||
for (j = prev_bytes; j < sizeof(u32); j++) {
|
||||
*(tmp + j) = *bufptr++;
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
|
||||
length -= j - prev_bytes;
|
||||
offset++;
|
||||
}
|
||||
|
||||
remaining = length & 0x3;
|
||||
length -= remaining;
|
||||
|
||||
/* Calculate length in DWORDs */
|
||||
length >>= 2;
|
||||
|
||||
/*
|
||||
* The device driver writes the relevant command block into the
|
||||
* ram area.
|
||||
*/
|
||||
for (i = 0; i < length; i++) {
|
||||
for (j = 0; j < sizeof(u32); j++) {
|
||||
*(tmp + j) = *bufptr++;
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
|
||||
E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
|
||||
data);
|
||||
}
|
||||
if (remaining) {
|
||||
for (j = 0; j < sizeof(u32); j++) {
|
||||
if (j < remaining)
|
||||
*(tmp + j) = *bufptr++;
|
||||
else
|
||||
*(tmp + j) = 0;
|
||||
|
||||
*sum += *(tmp + j);
|
||||
}
|
||||
E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_enable_mng_pass_thru - Enable processing of ARP's
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Verifies the hardware needs to allow ARPs to be processed by the host.
|
||||
**/
|
||||
bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
|
||||
{
|
||||
u32 manc;
|
||||
u32 fwsm, factps;
|
||||
bool ret_val = false;
|
||||
|
||||
DEBUGFUNC("igb_enable_mng_pass_thru");
|
||||
|
||||
if (!hw->mac.asf_firmware_present)
|
||||
goto out;
|
||||
|
||||
manc = E1000_READ_REG(hw, E1000_MANC);
|
||||
|
||||
if (!(manc & E1000_MANC_RCV_TCO_EN) ||
|
||||
!(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
|
||||
goto out;
|
||||
|
||||
if (hw->mac.arc_subsystem_valid) {
|
||||
fwsm = E1000_READ_REG(hw, E1000_FWSM);
|
||||
factps = E1000_READ_REG(hw, E1000_FACTPS);
|
||||
|
||||
if (!(factps & E1000_FACTPS_MNGCG) &&
|
||||
((fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
|
||||
ret_val = true;
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
if ((manc & E1000_MANC_SMBUS_EN) &&
|
||||
!(manc & E1000_MANC_ASF_EN)) {
|
||||
ret_val = true;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#ifndef _IGB_MANAGE_H_
|
||||
#define _IGB_MANAGE_H_
|
||||
|
||||
bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
|
||||
bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
|
||||
s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
|
||||
s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
|
||||
u16 length, u16 offset, u8 *sum);
|
||||
s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
|
||||
struct e1000_host_mng_command_header *hdr);
|
||||
s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
|
||||
u8 *buffer, u16 length);
|
||||
bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
|
||||
|
||||
enum e1000_mng_mode {
|
||||
e1000_mng_mode_none = 0,
|
||||
e1000_mng_mode_asf,
|
||||
e1000_mng_mode_pt,
|
||||
e1000_mng_mode_ipmi,
|
||||
e1000_mng_mode_host_if_only
|
||||
};
|
||||
|
||||
#define E1000_FACTPS_MNGCG 0x20000000
|
||||
|
||||
#define E1000_FWSM_MODE_MASK 0xE
|
||||
#define E1000_FWSM_MODE_SHIFT 1
|
||||
|
||||
#define E1000_MNG_IAMT_MODE 0x3
|
||||
#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
|
||||
#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
|
||||
#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
|
||||
#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
|
||||
#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
|
||||
|
||||
#define E1000_VFTA_ENTRY_SHIFT 5
|
||||
#define E1000_VFTA_ENTRY_MASK 0x7F
|
||||
#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
|
||||
|
||||
#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
|
||||
#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
|
||||
#define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
|
||||
|
||||
#define E1000_HICR_EN 0x01 /* Enable bit - RO */
|
||||
/* Driver sets this bit when done to put command in RAM */
|
||||
#define E1000_HICR_C 0x02
|
||||
#define E1000_HICR_SV 0x04 /* Status Validity */
|
||||
#define E1000_HICR_FW_RESET_ENABLE 0x40
|
||||
#define E1000_HICR_FW_RESET 0x80
|
||||
|
||||
/* Intel(R) Active Management Technology signature */
|
||||
#define E1000_IAMT_SIGNATURE 0x544D4149
|
||||
|
||||
#endif /* _IGB_MANAGE_H_ */
|
||||
|
|
@ -0,0 +1,627 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#include "igb.h"
|
||||
|
||||
static void igb_stop_nvm(struct e1000_hw *hw);
|
||||
static void igb_reload_nvm_generic(struct e1000_hw *hw);
|
||||
|
||||
/**
|
||||
* igb_init_nvm_ops_generic - Initialize NVM function pointers
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Setups up the function pointers to no-op functions
|
||||
**/
|
||||
void igb_init_nvm_ops_generic(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_nvm_info *nvm = &hw->nvm;
|
||||
DEBUGFUNC("igb_init_nvm_ops_generic");
|
||||
|
||||
/* Initialize function pointers */
|
||||
nvm->ops.reload = igb_reload_nvm_generic;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_raise_eec_clk - Raise EEPROM clock
|
||||
* @hw: pointer to the HW structure
|
||||
* @eecd: pointer to the EEPROM
|
||||
*
|
||||
* Enable/Raise the EEPROM clock bit.
|
||||
**/
|
||||
static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
|
||||
{
|
||||
*eecd = *eecd | E1000_EECD_SK;
|
||||
E1000_WRITE_REG(hw, E1000_EECD, *eecd);
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
usec_delay(hw->nvm.delay_usec);
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_lower_eec_clk - Lower EEPROM clock
|
||||
* @hw: pointer to the HW structure
|
||||
* @eecd: pointer to the EEPROM
|
||||
*
|
||||
* Clear/Lower the EEPROM clock bit.
|
||||
**/
|
||||
static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
|
||||
{
|
||||
*eecd = *eecd & ~E1000_EECD_SK;
|
||||
E1000_WRITE_REG(hw, E1000_EECD, *eecd);
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
usec_delay(hw->nvm.delay_usec);
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_shift_out_eec_bits - Shift data bits our to the EEPROM
|
||||
* @hw: pointer to the HW structure
|
||||
* @data: data to send to the EEPROM
|
||||
* @count: number of bits to shift out
|
||||
*
|
||||
* We need to shift 'count' bits out to the EEPROM. So, the value in the
|
||||
* "data" parameter will be shifted out to the EEPROM one bit at a time.
|
||||
* In order to do this, "data" must be broken down into bits.
|
||||
**/
|
||||
static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
|
||||
{
|
||||
struct e1000_nvm_info *nvm = &hw->nvm;
|
||||
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
u32 mask;
|
||||
|
||||
DEBUGFUNC("igb_shift_out_eec_bits");
|
||||
|
||||
mask = 0x01 << (count - 1);
|
||||
if (nvm->type == e1000_nvm_eeprom_spi)
|
||||
eecd |= E1000_EECD_DO;
|
||||
|
||||
do {
|
||||
eecd &= ~E1000_EECD_DI;
|
||||
|
||||
if (data & mask)
|
||||
eecd |= E1000_EECD_DI;
|
||||
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
|
||||
usec_delay(nvm->delay_usec);
|
||||
|
||||
igb_raise_eec_clk(hw, &eecd);
|
||||
igb_lower_eec_clk(hw, &eecd);
|
||||
|
||||
mask >>= 1;
|
||||
} while (mask);
|
||||
|
||||
eecd &= ~E1000_EECD_DI;
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_shift_in_eec_bits - Shift data bits in from the EEPROM
|
||||
* @hw: pointer to the HW structure
|
||||
* @count: number of bits to shift in
|
||||
*
|
||||
* In order to read a register from the EEPROM, we need to shift 'count' bits
|
||||
* in from the EEPROM. Bits are "shifted in" by raising the clock input to
|
||||
* the EEPROM (setting the SK bit), and then reading the value of the data out
|
||||
* "DO" bit. During this "shifting in" process the data in "DI" bit should
|
||||
* always be clear.
|
||||
**/
|
||||
static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
|
||||
{
|
||||
u32 eecd;
|
||||
u32 i;
|
||||
u16 data;
|
||||
|
||||
DEBUGFUNC("igb_shift_in_eec_bits");
|
||||
|
||||
eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
|
||||
eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
|
||||
data = 0;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
data <<= 1;
|
||||
igb_raise_eec_clk(hw, &eecd);
|
||||
|
||||
eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
|
||||
eecd &= ~E1000_EECD_DI;
|
||||
if (eecd & E1000_EECD_DO)
|
||||
data |= 1;
|
||||
|
||||
igb_lower_eec_clk(hw, &eecd);
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
|
||||
* @hw: pointer to the HW structure
|
||||
* @ee_reg: EEPROM flag for polling
|
||||
*
|
||||
* Polls the EEPROM status bit for either read or write completion based
|
||||
* upon the value of 'ee_reg'.
|
||||
**/
|
||||
s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
|
||||
{
|
||||
u32 attempts = 100000;
|
||||
u32 i, reg = 0;
|
||||
s32 ret_val = -E1000_ERR_NVM;
|
||||
|
||||
DEBUGFUNC("igb_poll_eerd_eewr_done");
|
||||
|
||||
for (i = 0; i < attempts; i++) {
|
||||
if (ee_reg == E1000_NVM_POLL_READ)
|
||||
reg = E1000_READ_REG(hw, E1000_EERD);
|
||||
else
|
||||
reg = E1000_READ_REG(hw, E1000_EEWR);
|
||||
|
||||
if (reg & E1000_NVM_RW_REG_DONE) {
|
||||
ret_val = E1000_SUCCESS;
|
||||
break;
|
||||
}
|
||||
|
||||
usec_delay(5);
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_acquire_nvm_generic - Generic request for access to EEPROM
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Set the EEPROM access request bit and wait for EEPROM access grant bit.
|
||||
* Return successful if access grant bit set, else clear the request for
|
||||
* EEPROM access and return -E1000_ERR_NVM (-1).
|
||||
**/
|
||||
s32 igb_acquire_nvm_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
|
||||
DEBUGFUNC("igb_acquire_nvm_generic");
|
||||
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
|
||||
eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
|
||||
while (timeout) {
|
||||
if (eecd & E1000_EECD_GNT)
|
||||
break;
|
||||
usec_delay(5);
|
||||
eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if (!timeout) {
|
||||
eecd &= ~E1000_EECD_REQ;
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
||||
DEBUGOUT("Could not acquire NVM grant\n");
|
||||
ret_val = -E1000_ERR_NVM;
|
||||
}
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_standby_nvm - Return EEPROM to standby state
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Return the EEPROM to a standby state.
|
||||
**/
|
||||
static void igb_standby_nvm(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_nvm_info *nvm = &hw->nvm;
|
||||
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
|
||||
DEBUGFUNC("igb_standby_nvm");
|
||||
|
||||
if (nvm->type == e1000_nvm_eeprom_spi) {
|
||||
/* Toggle CS to flush commands */
|
||||
eecd |= E1000_EECD_CS;
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
usec_delay(nvm->delay_usec);
|
||||
eecd &= ~E1000_EECD_CS;
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
usec_delay(nvm->delay_usec);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_stop_nvm - Terminate EEPROM command
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Terminates the current command by inverting the EEPROM's chip select pin.
|
||||
**/
|
||||
static void igb_stop_nvm(struct e1000_hw *hw)
|
||||
{
|
||||
u32 eecd;
|
||||
|
||||
DEBUGFUNC("igb_stop_nvm");
|
||||
|
||||
eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
if (hw->nvm.type == e1000_nvm_eeprom_spi) {
|
||||
/* Pull CS high */
|
||||
eecd |= E1000_EECD_CS;
|
||||
igb_lower_eec_clk(hw, &eecd);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_release_nvm_generic - Release exclusive access to EEPROM
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Stop any current commands to the EEPROM and clear the EEPROM request bit.
|
||||
**/
|
||||
void igb_release_nvm_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 eecd;
|
||||
|
||||
DEBUGFUNC("igb_release_nvm_generic");
|
||||
|
||||
igb_stop_nvm(hw);
|
||||
|
||||
eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
eecd &= ~E1000_EECD_REQ;
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_ready_nvm_eeprom - Prepares EEPROM for read/write
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Setups the EEPROM for reading and writing.
|
||||
**/
|
||||
static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_nvm_info *nvm = &hw->nvm;
|
||||
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
u16 timeout = 0;
|
||||
u8 spi_stat_reg;
|
||||
|
||||
DEBUGFUNC("igb_ready_nvm_eeprom");
|
||||
|
||||
if (nvm->type == e1000_nvm_eeprom_spi) {
|
||||
/* Clear SK and CS */
|
||||
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
|
||||
E1000_WRITE_REG(hw, E1000_EECD, eecd);
|
||||
usec_delay(1);
|
||||
timeout = NVM_MAX_RETRY_SPI;
|
||||
|
||||
/*
|
||||
* Read "Status Register" repeatedly until the LSB is cleared.
|
||||
* The EEPROM will signal that the command has been completed
|
||||
* by clearing bit 0 of the internal status register. If it's
|
||||
* not cleared within 'timeout', then error out.
|
||||
*/
|
||||
while (timeout) {
|
||||
igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
|
||||
hw->nvm.opcode_bits);
|
||||
spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
|
||||
if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
|
||||
break;
|
||||
|
||||
usec_delay(5);
|
||||
igb_standby_nvm(hw);
|
||||
timeout--;
|
||||
}
|
||||
|
||||
if (!timeout) {
|
||||
DEBUGOUT("SPI NVM Status error\n");
|
||||
ret_val = -E1000_ERR_NVM;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_read_nvm_eerd - Reads EEPROM using EERD register
|
||||
* @hw: pointer to the HW structure
|
||||
* @offset: offset of word in the EEPROM to read
|
||||
* @words: number of words to read
|
||||
* @data: word read from the EEPROM
|
||||
*
|
||||
* Reads a 16 bit word from the EEPROM using the EERD register.
|
||||
**/
|
||||
s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
||||
{
|
||||
struct e1000_nvm_info *nvm = &hw->nvm;
|
||||
u32 i, eerd = 0;
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
|
||||
DEBUGFUNC("igb_read_nvm_eerd");
|
||||
|
||||
/*
|
||||
* A check for invalid values: offset too large, too many words,
|
||||
* too many words for the offset, and not enough words.
|
||||
*/
|
||||
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
|
||||
(words == 0)) {
|
||||
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
||||
ret_val = -E1000_ERR_NVM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < words; i++) {
|
||||
eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
|
||||
E1000_NVM_RW_REG_START;
|
||||
|
||||
E1000_WRITE_REG(hw, E1000_EERD, eerd);
|
||||
ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
|
||||
if (ret_val)
|
||||
break;
|
||||
|
||||
data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
|
||||
E1000_NVM_RW_REG_DATA);
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_write_nvm_spi - Write to EEPROM using SPI
|
||||
* @hw: pointer to the HW structure
|
||||
* @offset: offset within the EEPROM to be written to
|
||||
* @words: number of words to write
|
||||
* @data: 16 bit word(s) to be written to the EEPROM
|
||||
*
|
||||
* Writes data to EEPROM at offset using SPI interface.
|
||||
*
|
||||
* If e1000_update_nvm_checksum is not called after this function , the
|
||||
* EEPROM will most likely contain an invalid checksum.
|
||||
**/
|
||||
s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
|
||||
{
|
||||
struct e1000_nvm_info *nvm = &hw->nvm;
|
||||
s32 ret_val;
|
||||
u16 widx = 0;
|
||||
|
||||
DEBUGFUNC("igb_write_nvm_spi");
|
||||
|
||||
/*
|
||||
* A check for invalid values: offset too large, too many words,
|
||||
* and not enough words.
|
||||
*/
|
||||
if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
|
||||
(words == 0)) {
|
||||
DEBUGOUT("nvm parameter(s) out of bounds\n");
|
||||
ret_val = -E1000_ERR_NVM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret_val = nvm->ops.acquire(hw);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
while (widx < words) {
|
||||
u8 write_opcode = NVM_WRITE_OPCODE_SPI;
|
||||
|
||||
ret_val = igb_ready_nvm_eeprom(hw);
|
||||
if (ret_val)
|
||||
goto release;
|
||||
|
||||
igb_standby_nvm(hw);
|
||||
|
||||
/* Send the WRITE ENABLE command (8 bit opcode) */
|
||||
igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
|
||||
nvm->opcode_bits);
|
||||
|
||||
igb_standby_nvm(hw);
|
||||
|
||||
/*
|
||||
* Some SPI eeproms use the 8th address bit embedded in the
|
||||
* opcode
|
||||
*/
|
||||
if ((nvm->address_bits == 8) && (offset >= 128))
|
||||
write_opcode |= NVM_A8_OPCODE_SPI;
|
||||
|
||||
/* Send the Write command (8-bit opcode + addr) */
|
||||
igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
|
||||
igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
|
||||
nvm->address_bits);
|
||||
|
||||
/* Loop to allow for up to whole page write of eeprom */
|
||||
while (widx < words) {
|
||||
u16 word_out = data[widx];
|
||||
word_out = (word_out >> 8) | (word_out << 8);
|
||||
igb_shift_out_eec_bits(hw, word_out, 16);
|
||||
widx++;
|
||||
|
||||
if ((((offset + widx) * 2) % nvm->page_size) == 0) {
|
||||
igb_standby_nvm(hw);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
msec_delay(10);
|
||||
release:
|
||||
nvm->ops.release(hw);
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_read_pba_num_generic - Read device part number
|
||||
* @hw: pointer to the HW structure
|
||||
* @pba_num: pointer to device part number
|
||||
*
|
||||
* Reads the product board assembly (PBA) number from the EEPROM and stores
|
||||
* the value in pba_num.
|
||||
**/
|
||||
s32 igb_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
|
||||
{
|
||||
s32 ret_val;
|
||||
u16 nvm_data;
|
||||
|
||||
DEBUGFUNC("igb_read_pba_num_generic");
|
||||
|
||||
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("NVM Read Error\n");
|
||||
goto out;
|
||||
}
|
||||
*pba_num = (u32)(nvm_data << 16);
|
||||
|
||||
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("NVM Read Error\n");
|
||||
goto out;
|
||||
}
|
||||
*pba_num |= nvm_data;
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_read_mac_addr_generic - Read device MAC address
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Reads the device MAC address from the EEPROM and stores the value.
|
||||
* Since devices with two ports use the same EEPROM, we increment the
|
||||
* last bit in the MAC address for the second port.
|
||||
**/
|
||||
s32 igb_read_mac_addr_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 rar_high;
|
||||
u32 rar_low;
|
||||
u16 i;
|
||||
|
||||
rar_high = E1000_READ_REG(hw, E1000_RAH(0));
|
||||
rar_low = E1000_READ_REG(hw, E1000_RAL(0));
|
||||
|
||||
for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
|
||||
hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
|
||||
|
||||
for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
|
||||
hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
|
||||
|
||||
for (i = 0; i < ETH_ADDR_LEN; i++)
|
||||
hw->mac.addr[i] = hw->mac.perm_addr[i];
|
||||
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_validate_nvm_checksum_generic - Validate EEPROM checksum
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
|
||||
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
|
||||
**/
|
||||
s32 igb_validate_nvm_checksum_generic(struct e1000_hw *hw)
|
||||
{
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
u16 checksum = 0;
|
||||
u16 i, nvm_data;
|
||||
|
||||
DEBUGFUNC("igb_validate_nvm_checksum_generic");
|
||||
|
||||
for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
|
||||
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("NVM Read Error\n");
|
||||
goto out;
|
||||
}
|
||||
checksum += nvm_data;
|
||||
}
|
||||
|
||||
if (checksum != (u16) NVM_SUM) {
|
||||
DEBUGOUT("NVM Checksum Invalid\n");
|
||||
ret_val = -E1000_ERR_NVM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_update_nvm_checksum_generic - Update EEPROM checksum
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
|
||||
* up to the checksum. Then calculates the EEPROM checksum and writes the
|
||||
* value to the EEPROM.
|
||||
**/
|
||||
s32 igb_update_nvm_checksum_generic(struct e1000_hw *hw)
|
||||
{
|
||||
s32 ret_val;
|
||||
u16 checksum = 0;
|
||||
u16 i, nvm_data;
|
||||
|
||||
DEBUGFUNC("igb_update_nvm_checksum");
|
||||
|
||||
for (i = 0; i < NVM_CHECKSUM_REG; i++) {
|
||||
ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("NVM Read Error while updating checksum.\n");
|
||||
goto out;
|
||||
}
|
||||
checksum += nvm_data;
|
||||
}
|
||||
checksum = (u16) NVM_SUM - checksum;
|
||||
ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("NVM Write Error while updating checksum.\n");
|
||||
}
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_reload_nvm_generic - Reloads EEPROM
|
||||
* @hw: pointer to the HW structure
|
||||
*
|
||||
* Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
|
||||
* extended control register.
|
||||
**/
|
||||
static void igb_reload_nvm_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 ctrl_ext;
|
||||
|
||||
DEBUGFUNC("igb_reload_nvm_generic");
|
||||
|
||||
usec_delay(10);
|
||||
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
|
||||
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
|
||||
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#ifndef _IGB_NVM_H_
|
||||
#define _IGB_NVM_H_
|
||||
|
||||
void igb_init_nvm_ops_generic(struct e1000_hw *hw);
|
||||
s32 igb_acquire_nvm_generic(struct e1000_hw *hw);
|
||||
|
||||
s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
|
||||
s32 igb_read_mac_addr_generic(struct e1000_hw *hw);
|
||||
s32 igb_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
|
||||
s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
|
||||
u16 *data);
|
||||
s32 igb_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
|
||||
s32 igb_validate_nvm_checksum_generic(struct e1000_hw *hw);
|
||||
s32 igb_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
|
||||
u16 words, u16 *data);
|
||||
s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
|
||||
u16 *data);
|
||||
s32 igb_update_nvm_checksum_generic(struct e1000_hw *hw);
|
||||
void igb_release_nvm_generic(struct e1000_hw *hw);
|
||||
|
||||
#define E1000_STM_OPCODE 0xDB00
|
||||
|
||||
#endif /* _IGB_NVM_H_ */
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
/* glue for the OS independent part of e1000
|
||||
* includes register access macros
|
||||
*/
|
||||
|
||||
#ifndef _IGB_OSDEP_H_
|
||||
#define _IGB_OSDEP_H_
|
||||
|
||||
/* Begin OS Dependencies */
|
||||
|
||||
#define u8 unsigned char
|
||||
#define bool boolean_t
|
||||
#define dma_addr_t unsigned long
|
||||
#define __le16 uint16_t
|
||||
#define __le32 uint32_t
|
||||
#define __le64 uint64_t
|
||||
|
||||
#define __iomem
|
||||
#define __devinit
|
||||
|
||||
#define msleep(x) mdelay(x)
|
||||
|
||||
#define ETH_FCS_LEN 4
|
||||
|
||||
typedef int spinlock_t;
|
||||
typedef enum {
|
||||
false = 0,
|
||||
true = 1
|
||||
} boolean_t;
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#define usec_delay(x) udelay(x)
|
||||
#define msec_delay(x) mdelay(x)
|
||||
#define msec_delay_irq(x) mdelay(x)
|
||||
|
||||
/* End OS Dependencies */
|
||||
|
||||
#define PCI_COMMAND_REGISTER PCI_COMMAND
|
||||
#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
|
||||
#define ETH_ADDR_LEN ETH_ALEN
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
#define E1000_BIG_ENDIAN __BIG_ENDIAN
|
||||
#endif
|
||||
|
||||
|
||||
#define DEBUGOUT(S) if (0) { printf(S); }
|
||||
#define DEBUGOUT1(S, A...) if (0) { printf(S, A); }
|
||||
|
||||
#define DEBUGFUNC(F) DEBUGOUT(F "\n")
|
||||
#define DEBUGOUT2 DEBUGOUT1
|
||||
#define DEBUGOUT3 DEBUGOUT2
|
||||
#define DEBUGOUT7 DEBUGOUT3
|
||||
|
||||
#define E1000_REGISTER(a, reg) (reg)
|
||||
|
||||
#define E1000_WRITE_REG(a, reg, value) do { \
|
||||
writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))); } while (0)
|
||||
|
||||
#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) do { \
|
||||
writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))); } while (0);
|
||||
|
||||
#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
|
||||
readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
|
||||
#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
|
||||
writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
|
||||
readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
|
||||
|
||||
#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
|
||||
writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
|
||||
|
||||
#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
|
||||
readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
|
||||
|
||||
#define E1000_WRITE_REG_IO(a, reg, offset) do { \
|
||||
outl(reg, ((a)->io_base)); \
|
||||
outl(offset, ((a)->io_base + 4)); } while (0)
|
||||
|
||||
#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
|
||||
|
||||
#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
|
||||
writel((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
|
||||
writew((value), ((a)->flash_address + reg)))
|
||||
|
||||
#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
|
||||
|
||||
#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
|
||||
|
||||
#endif /* _IGB_OSDEP_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,171 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#ifndef _IGB_PHY_H_
|
||||
#define _IGB_PHY_H_
|
||||
|
||||
void igb_init_phy_ops_generic(struct e1000_hw *hw);
|
||||
s32 igb_check_downshift_generic(struct e1000_hw *hw);
|
||||
s32 igb_check_polarity_m88(struct e1000_hw *hw);
|
||||
s32 igb_check_polarity_igp(struct e1000_hw *hw);
|
||||
s32 igb_check_polarity_ife(struct e1000_hw *hw);
|
||||
s32 igb_check_reset_block_generic(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_autoneg(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_setup_igp(struct e1000_hw *hw);
|
||||
s32 igb_copper_link_setup_m88(struct e1000_hw *hw);
|
||||
#if 0
|
||||
s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_ife(struct e1000_hw *hw);
|
||||
#endif
|
||||
#if 0
|
||||
s32 igb_get_cable_length_m88(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_igp_2(struct e1000_hw *hw);
|
||||
#endif
|
||||
s32 igb_get_cfg_done_generic(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_id(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_igp(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_m88(struct e1000_hw *hw);
|
||||
s32 igb_phy_sw_reset_generic(struct e1000_hw *hw);
|
||||
#if 0
|
||||
void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
|
||||
#endif
|
||||
s32 igb_phy_hw_reset_generic(struct e1000_hw *hw);
|
||||
s32 igb_phy_reset_dsp_generic(struct e1000_hw *hw);
|
||||
s32 igb_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
|
||||
s32 igb_setup_copper_link_generic(struct e1000_hw *hw);
|
||||
s32 igb_wait_autoneg_generic(struct e1000_hw *hw);
|
||||
s32 igb_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_phy_reset_dsp(struct e1000_hw *hw);
|
||||
s32 igb_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
|
||||
u32 usec_interval, bool *success);
|
||||
s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
|
||||
enum e1000_phy_type igb_get_phy_type_from_id(u32 phy_id);
|
||||
s32 igb_determine_phy_address(struct e1000_hw *hw);
|
||||
void igb_power_up_phy_copper(struct e1000_hw *hw);
|
||||
void igb_power_down_phy_copper(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
|
||||
#define E1000_MAX_PHY_ADDR 4
|
||||
|
||||
/* IGP01E1000 Specific Registers */
|
||||
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
|
||||
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
|
||||
#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
|
||||
#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
|
||||
#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
|
||||
#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
|
||||
#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
|
||||
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
|
||||
#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
|
||||
#define IGP_PAGE_SHIFT 5
|
||||
#define PHY_REG_MASK 0x1F
|
||||
|
||||
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
|
||||
#define IGP01E1000_PHY_POLARITY_MASK 0x0078
|
||||
|
||||
#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
|
||||
#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
|
||||
|
||||
#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
|
||||
|
||||
/* Enable flexible speed on link-up */
|
||||
#define IGP01E1000_GMII_FLEX_SPD 0x0010
|
||||
#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
|
||||
|
||||
#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
|
||||
#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
|
||||
#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
|
||||
|
||||
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
|
||||
|
||||
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
|
||||
#define IGP01E1000_PSSR_MDIX 0x0800
|
||||
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
|
||||
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
|
||||
|
||||
#define IGP02E1000_PHY_CHANNEL_NUM 4
|
||||
#define IGP02E1000_PHY_AGC_A 0x11B1
|
||||
#define IGP02E1000_PHY_AGC_B 0x12B1
|
||||
#define IGP02E1000_PHY_AGC_C 0x14B1
|
||||
#define IGP02E1000_PHY_AGC_D 0x18B1
|
||||
|
||||
#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
|
||||
#define IGP02E1000_AGC_LENGTH_MASK 0x7F
|
||||
#define IGP02E1000_AGC_RANGE 15
|
||||
|
||||
#define IGP03E1000_PHY_MISC_CTRL 0x1B
|
||||
#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
|
||||
|
||||
#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
|
||||
|
||||
#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
|
||||
#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
|
||||
#define E1000_KMRNCTRLSTA_REN 0x00200000
|
||||
#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
|
||||
#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
|
||||
#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
|
||||
#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
|
||||
|
||||
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
|
||||
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
|
||||
#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
|
||||
#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
|
||||
|
||||
/* IFE PHY Extended Status Control */
|
||||
#define IFE_PESC_POLARITY_REVERSED 0x0100
|
||||
|
||||
/* IFE PHY Special Control */
|
||||
#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
|
||||
#define IFE_PSC_FORCE_POLARITY 0x0020
|
||||
#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
|
||||
|
||||
/* IFE PHY Special Control and LED Control */
|
||||
#define IFE_PSCL_PROBE_MODE 0x0020
|
||||
#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
|
||||
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
|
||||
|
||||
/* IFE PHY MDIX Control */
|
||||
#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
|
||||
#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
|
||||
#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
|
||||
|
||||
#endif /* _IGB_PHY_H_ */
|
||||
|
|
@ -0,0 +1,486 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel(R) Gigabit Ethernet Linux driver
|
||||
Copyright(c) 2007-2009 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
version 2, as published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
The full GNU General Public License is included in this distribution in
|
||||
the file called "COPYING".
|
||||
|
||||
Contact Information:
|
||||
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
|
||||
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
FILE_LICENCE ( GPL2_ONLY );
|
||||
|
||||
#ifndef _IGB_REGS_H_
|
||||
#define _IGB_REGS_H_
|
||||
|
||||
#define E1000_CTRL 0x00000 /* Device Control - RW */
|
||||
#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
|
||||
#define E1000_STATUS 0x00008 /* Device Status - RO */
|
||||
#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
|
||||
#define E1000_EERD 0x00014 /* EEPROM Read - RW */
|
||||
#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
|
||||
#define E1000_FLA 0x0001C /* Flash Access - RW */
|
||||
#define E1000_MDIC 0x00020 /* MDI Control - RW */
|
||||
#define E1000_SCTL 0x00024 /* SerDes Control - RW */
|
||||
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
|
||||
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
|
||||
#define E1000_FEXT 0x0002C /* Future Extended - RW */
|
||||
#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
|
||||
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
|
||||
#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
|
||||
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
|
||||
#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
|
||||
#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
|
||||
#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
|
||||
#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
|
||||
#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
|
||||
#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
|
||||
#define E1000_RCTL 0x00100 /* Rx Control - RW */
|
||||
#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
|
||||
#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
|
||||
#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
|
||||
#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
|
||||
#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
|
||||
#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
|
||||
#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
|
||||
#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
|
||||
#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
|
||||
#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
|
||||
#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
|
||||
#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
|
||||
#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
|
||||
#define E1000_TCTL 0x00400 /* Tx Control - RW */
|
||||
#define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
|
||||
#define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
|
||||
#define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
|
||||
#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
|
||||
#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
|
||||
#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
|
||||
#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
|
||||
#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
|
||||
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
||||
#define E1000_PBS 0x01008 /* Packet Buffer Size */
|
||||
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
|
||||
#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
|
||||
#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
|
||||
#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
|
||||
#define E1000_FLSWCTL 0x01030 /* FLASH control register */
|
||||
#define E1000_FLSWDATA 0x01034 /* FLASH data register */
|
||||
#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
|
||||
#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
|
||||
#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
|
||||
#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
|
||||
#define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */
|
||||
#define E1000_SWDSTS 0x01044 /* SW Device Status - RW */
|
||||
#define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
|
||||
#define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
|
||||
#define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */
|
||||
#define E1000_ICR_V2 0x01500 /* Interrupt Cause - new location - RC */
|
||||
#define E1000_ICS_V2 0x01504 /* Interrupt Cause Set - new location - WO */
|
||||
#define E1000_IMS_V2 0x01508 /* Interrupt Mask Set/Read - new location - RW */
|
||||
#define E1000_IMC_V2 0x0150C /* Interrupt Mask Clear - new location - WO */
|
||||
#define E1000_IAM_V2 0x01510 /* Interrupt Ack Auto Mask - new location - RW */
|
||||
#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
|
||||
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
|
||||
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
|
||||
#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
|
||||
#define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
|
||||
#define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
|
||||
#define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
|
||||
/* Split and Replication Rx Control - RW */
|
||||
#define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
|
||||
#define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
|
||||
#define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
|
||||
#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
|
||||
#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
|
||||
#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */
|
||||
#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
|
||||
#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
|
||||
#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
|
||||
/*
|
||||
* Convenience macros
|
||||
*
|
||||
* Note: "_n" is the queue number of the register to be written to.
|
||||
*
|
||||
* Example usage:
|
||||
* E1000_RDBAL_REG(current_rx_queue)
|
||||
*/
|
||||
#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
|
||||
(0x0C000 + ((_n) * 0x40)))
|
||||
#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
|
||||
(0x0C004 + ((_n) * 0x40)))
|
||||
#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
|
||||
(0x0C008 + ((_n) * 0x40)))
|
||||
#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
|
||||
(0x0C00C + ((_n) * 0x40)))
|
||||
#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
|
||||
(0x0C010 + ((_n) * 0x40)))
|
||||
#define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
|
||||
(0x0C014 + ((_n) * 0x40)))
|
||||
#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
|
||||
#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
|
||||
(0x0C018 + ((_n) * 0x40)))
|
||||
#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
|
||||
(0x0C028 + ((_n) * 0x40)))
|
||||
#define E1000_RQDPC(_n) ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
|
||||
(0x0C030 + ((_n) * 0x40)))
|
||||
#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
|
||||
(0x0E000 + ((_n) * 0x40)))
|
||||
#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
|
||||
(0x0E004 + ((_n) * 0x40)))
|
||||
#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
|
||||
(0x0E008 + ((_n) * 0x40)))
|
||||
#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
|
||||
(0x0E010 + ((_n) * 0x40)))
|
||||
#define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
|
||||
(0x0E014 + ((_n) * 0x40)))
|
||||
#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
|
||||
#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
|
||||
(0x0E018 + ((_n) * 0x40)))
|
||||
#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
|
||||
(0x0E028 + ((_n) * 0x40)))
|
||||
#define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
|
||||
(0x0E038 + ((_n) * 0x40)))
|
||||
#define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
|
||||
(0x0E03C + ((_n) * 0x40)))
|
||||
#define E1000_TARC(_n) (0x03840 + ((_n) * 0x100))
|
||||
#define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
|
||||
#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
|
||||
#define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
|
||||
#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
|
||||
#define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
|
||||
#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
|
||||
(0x054E0 + ((_i - 16) * 8)))
|
||||
#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
|
||||
(0x054E4 + ((_i - 16) * 8)))
|
||||
#define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
|
||||
#define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
|
||||
#define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
|
||||
#define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
|
||||
#define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
|
||||
#define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
|
||||
#define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */
|
||||
#define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Packet Buffer DWORD (_n) */
|
||||
#define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
|
||||
#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
|
||||
#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
|
||||
#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
|
||||
#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
|
||||
#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
|
||||
#define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */
|
||||
#define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */
|
||||
#define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */
|
||||
#define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */
|
||||
#define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */
|
||||
#define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
|
||||
#define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
|
||||
#define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
|
||||
#define E1000_DTXMXSZRQ 0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
|
||||
#define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
|
||||
#define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
|
||||
#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
|
||||
#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
|
||||
#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
|
||||
#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
|
||||
#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
|
||||
#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
|
||||
#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
|
||||
#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
|
||||
#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
|
||||
#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
|
||||
#define E1000_COLC 0x04028 /* Collision Count - R/clr */
|
||||
#define E1000_DC 0x04030 /* Defer Count - R/clr */
|
||||
#define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
|
||||
#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
|
||||
#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
|
||||
#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
|
||||
#define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
|
||||
#define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
|
||||
#define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
|
||||
#define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
|
||||
#define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
|
||||
#define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
|
||||
#define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
|
||||
#define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
|
||||
#define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
|
||||
#define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
|
||||
#define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
|
||||
#define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
|
||||
#define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
|
||||
#define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
|
||||
#define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
|
||||
#define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
|
||||
#define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
|
||||
#define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
|
||||
#define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
|
||||
#define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
|
||||
#define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
|
||||
#define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
|
||||
#define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
|
||||
#define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
|
||||
#define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
|
||||
#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
|
||||
#define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
|
||||
#define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
|
||||
#define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
|
||||
#define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
|
||||
#define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
|
||||
#define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
|
||||
#define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
|
||||
#define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
|
||||
#define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
|
||||
#define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
|
||||
#define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
|
||||
#define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
|
||||
#define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
|
||||
#define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
|
||||
#define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
|
||||
#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
|
||||
#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
|
||||
#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
|
||||
#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
|
||||
#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
|
||||
#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
|
||||
#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */
|
||||
#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
|
||||
#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */
|
||||
#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
|
||||
#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
|
||||
|
||||
#define E1000_LSECTXUT 0x04300 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */
|
||||
#define E1000_LSECTXPKTE 0x04304 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */
|
||||
#define E1000_LSECTXPKTP 0x04308 /* LinkSec Protected Tx Packet Count - OutPktsProtected */
|
||||
#define E1000_LSECTXOCTE 0x0430C /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */
|
||||
#define E1000_LSECTXOCTP 0x04310 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */
|
||||
#define E1000_LSECRXUT 0x04314 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */
|
||||
#define E1000_LSECRXOCTD 0x0431C /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */
|
||||
#define E1000_LSECRXOCTV 0x04320 /* LinkSec Rx Octets Validated - InOctetsValidated */
|
||||
#define E1000_LSECRXBAD 0x04324 /* LinkSec Rx Bad Tag - InPktsBadTag */
|
||||
#define E1000_LSECRXNOSCI 0x04328 /* LinkSec Rx Packet No SCI Count - InPktsNoSci */
|
||||
#define E1000_LSECRXUNSCI 0x0432C /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */
|
||||
#define E1000_LSECRXUNCH 0x04330 /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */
|
||||
#define E1000_LSECRXDELAY 0x04340 /* LinkSec Rx Delayed Packet Count - InPktsDelayed */
|
||||
#define E1000_LSECRXLATE 0x04350 /* LinkSec Rx Late Packets Count - InPktsLate */
|
||||
#define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* LinkSec Rx Packet OK Count - InPktsOk */
|
||||
#define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* LinkSec Rx Invalid Count - InPktsInvalid */
|
||||
#define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* LinkSec Rx Not Valid Count - InPktsNotValid */
|
||||
#define E1000_LSECRXUNSA 0x043C0 /* LinkSec Rx Unused SA Count - InPktsUnusedSa */
|
||||
#define E1000_LSECRXNUSA 0x043D0 /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */
|
||||
#define E1000_LSECTXCAP 0x0B000 /* LinkSec Tx Capabilities Register - RO */
|
||||
#define E1000_LSECRXCAP 0x0B300 /* LinkSec Rx Capabilities Register - RO */
|
||||
#define E1000_LSECTXCTRL 0x0B004 /* LinkSec Tx Control - RW */
|
||||
#define E1000_LSECRXCTRL 0x0B304 /* LinkSec Rx Control - RW */
|
||||
#define E1000_LSECTXSCL 0x0B008 /* LinkSec Tx SCI Low - RW */
|
||||
#define E1000_LSECTXSCH 0x0B00C /* LinkSec Tx SCI High - RW */
|
||||
#define E1000_LSECTXSA 0x0B010 /* LinkSec Tx SA0 - RW */
|
||||
#define E1000_LSECTXPN0 0x0B018 /* LinkSec Tx SA PN 0 - RW */
|
||||
#define E1000_LSECTXPN1 0x0B01C /* LinkSec Tx SA PN 1 - RW */
|
||||
#define E1000_LSECRXSCL 0x0B3D0 /* LinkSec Rx SCI Low - RW */
|
||||
#define E1000_LSECRXSCH 0x0B3E0 /* LinkSec Rx SCI High - RW */
|
||||
#define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 0 - WO */
|
||||
#define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 1 - WO */
|
||||
#define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
|
||||
#define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
|
||||
/*
|
||||
* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
|
||||
* key - RW.
|
||||
*/
|
||||
#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
|
||||
|
||||
#define E1000_SSVPC 0x041A0 /* Switch Security Violation Packet Count */
|
||||
#define E1000_IPSCTRL 0xB430 /* IpSec Control Register */
|
||||
#define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */
|
||||
#define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */
|
||||
#define E1000_IPSRXIPADDR(_n) (0x0B420+ (0x04 * (_n))) /* IPSec Rx IPv4/v6 Address - RW */
|
||||
#define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) /* IPSec Rx 128-bit Key - RW */
|
||||
#define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */
|
||||
#define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */
|
||||
#define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) /* IPSec Tx 128-bit Key - RW */
|
||||
#define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */
|
||||
#define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */
|
||||
#define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
|
||||
#define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
|
||||
#define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
|
||||
#define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */
|
||||
#define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
|
||||
#define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */
|
||||
#define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */
|
||||
#define E1000_RPTHC 0x04104 /* Rx Packets To Host */
|
||||
#define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */
|
||||
#define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */
|
||||
#define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
|
||||
#define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
|
||||
#define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
|
||||
#define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
|
||||
#define E1000_LENERRS 0x04138 /* Length Errors Count */
|
||||
#define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
|
||||
#define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */
|
||||
#define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
|
||||
#define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
|
||||
#define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
|
||||
#define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
|
||||
#define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */
|
||||
#define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
|
||||
#define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
|
||||
#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
|
||||
#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
|
||||
#define E1000_RA 0x05400 /* Receive Address - RW Array */
|
||||
#define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */
|
||||
#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
|
||||
#define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
|
||||
#define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */
|
||||
#define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
|
||||
#define E1000_WUC 0x05800 /* Wakeup Control - RW */
|
||||
#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
|
||||
#define E1000_WUS 0x05810 /* Wakeup Status - RO */
|
||||
#define E1000_MANC 0x05820 /* Management Control - RW */
|
||||
#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
|
||||
#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
|
||||
#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
|
||||
#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
|
||||
#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
|
||||
#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
|
||||
#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
|
||||
#define E1000_HOST_IF 0x08800 /* Host Interface */
|
||||
#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
|
||||
#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
|
||||
#define E1000_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */
|
||||
#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */
|
||||
|
||||
|
||||
#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
|
||||
#define E1000_MDPHYA 0x0003C /* PHY address - RW */
|
||||
#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
|
||||
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
|
||||
#define E1000_CCMCTL 0x05B48 /* CCM Control Register */
|
||||
#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
|
||||
#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
|
||||
#define E1000_GCR 0x05B00 /* PCI-Ex Control */
|
||||
#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
|
||||
#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
|
||||
#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
|
||||
#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
|
||||
#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
|
||||
#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
|
||||
#define E1000_SWSM 0x05B50 /* SW Semaphore */
|
||||
#define E1000_FWSM 0x05B54 /* FW Semaphore */
|
||||
#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
|
||||
#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
|
||||
#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
|
||||
#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
|
||||
#define E1000_HICR 0x08F00 /* Host Interface Control */
|
||||
|
||||
/* RSS registers */
|
||||
#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
|
||||
#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
|
||||
#define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
|
||||
#define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/
|
||||
#define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
|
||||
#define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
|
||||
* (_i) - RW */
|
||||
#define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
|
||||
* low reg - RW */
|
||||
#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
|
||||
* upper reg - RW */
|
||||
#define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
|
||||
* message reg - RW */
|
||||
#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
|
||||
* vector ctrl reg - RW */
|
||||
#define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */
|
||||
#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
|
||||
#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
|
||||
#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
|
||||
#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
|
||||
/* VT Registers */
|
||||
#define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */
|
||||
#define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
|
||||
#define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
|
||||
#define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */
|
||||
#define E1000_VFRE 0x00C8C /* VF Receive Enables */
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||||
#define E1000_VFTE 0x00C90 /* VF Transmit Enables */
|
||||
#define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
|
||||
#define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
|
||||
#define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
|
||||
#define E1000_UTA 0x0A000 /* Unicast Table Array - RW */
|
||||
#define E1000_IOVTCL 0x05BBC /* IOV Control Register */
|
||||
#define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */
|
||||
/* These act per VF so an array friendly macro is used */
|
||||
#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
|
||||
#define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))
|
||||
#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
|
||||
#define E1000_VFVMBMEM(_n) (0x00800 + (_n))
|
||||
#define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))
|
||||
#define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
|
||||
* Filter - RW */
|
||||
/* Time Sync */
|
||||
#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
|
||||
#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
|
||||
#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
|
||||
#define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
|
||||
#define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
|
||||
#define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */
|
||||
#define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */
|
||||
#define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
|
||||
#define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
|
||||
#define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
|
||||
#define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
|
||||
#define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
|
||||
|
||||
/* Filtering Registers */
|
||||
#define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
|
||||
#define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
|
||||
#define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
|
||||
#define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
|
||||
#define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
|
||||
#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
|
||||
#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
|
||||
|
||||
#define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */
|
||||
#define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */
|
||||
#define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */
|
||||
#define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */
|
||||
#define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */
|
||||
#define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) /* Tx Desc plane TC Rate-scheduler config */
|
||||
#define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Config */
|
||||
#define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Config */
|
||||
#define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler Status */
|
||||
#define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler MMW */
|
||||
#define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Status */
|
||||
#define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) /* Tx Packet plane TC Rate-scheduler MMW */
|
||||
#define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Status */
|
||||
#define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler MMW */
|
||||
#define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) /* Tx Desc plane VM Rate-Scheduler MMW*/
|
||||
#define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) /* Tx BCN Rate-Scheduler MMW */
|
||||
#define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */
|
||||
#define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */
|
||||
#define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */
|
||||
#define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */
|
||||
#define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */
|
||||
#define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */
|
||||
#define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */
|
||||
#define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */
|
||||
#define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */
|
||||
#define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */
|
||||
#define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */
|
||||
#define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */
|
||||
#define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */
|
||||
#define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */
|
||||
|
||||
#endif /* _IGB_REGS_H_ */
|
||||
|
|
@ -120,6 +120,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
|
|||
#define ERRFILE_vxge_main ( ERRFILE_DRIVER | 0x00550000 )
|
||||
#define ERRFILE_vxge_config ( ERRFILE_DRIVER | 0x00560000 )
|
||||
#define ERRFILE_vxge_traffic ( ERRFILE_DRIVER | 0x00570000 )
|
||||
#define ERRFILE_igb_main ( ERRFILE_DRIVER | 0x00580000 )
|
||||
|
||||
#define ERRFILE_scsi ( ERRFILE_DRIVER | 0x00700000 )
|
||||
#define ERRFILE_arbel ( ERRFILE_DRIVER | 0x00710000 )
|
||||
|
|
|
|||
Reference in New Issue