[thunderx] Add driver for Cavium ThunderX SoC NICs
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
parent
3c61e11fe1
commit
4775dd3835
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#ifndef _THUNDERX_H
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#define _THUNDERX_H
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/** @file
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*
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* Cavium ThunderX Ethernet driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/list.h>
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#include <ipxe/netdevice.h>
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#include <ipxe/uaccess.h>
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/******************************************************************************
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*
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* Address space
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*
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******************************************************************************
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*/
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/** Size of a cache line */
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#define TXNIC_LINE_SIZE 128
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/** Virtual function BAR size */
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#define TXNIC_VF_BAR_SIZE 0x200000UL
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/** Physical function BAR size */
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#define TXNIC_PF_BAR_SIZE 0x40000000UL
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/** BGX BAR size */
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#define TXNIC_BGX_BAR_SIZE 0x400000UL
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/** Maximum number of BGX Ethernet interfaces (per node) */
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#define TXNIC_NUM_BGX 2
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/** Maximum number of Logical MACs (per BGX) */
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#define TXNIC_NUM_LMAC 4
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/** Maximum number of destination MAC addresses (per BGX) */
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#define TXNIC_NUM_DMAC 32
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/** Maximum number of steering rules (per BGX) */
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#define TXNIC_NUM_STEERING 8
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/**
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* Calculate node ID
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*
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* @v addr PCI BAR base address
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* @ret node Node ID
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*/
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static inline unsigned int txnic_address_node ( uint64_t addr ) {
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/* Node ID is in bits [45:44] of the hardcoded BAR address */
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return ( ( addr >> 44 ) & 0x3 );
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}
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/**
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* Calculate BGX Ethernet interface index
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*
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* @v addr PCI BAR base address
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* @ret index Index
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*/
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static inline unsigned int txnic_address_bgx ( uint64_t addr ) {
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/* Index is in bit 24 of the hardcoded BAR address */
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return ( ( addr >> 24 ) & 0x1 );
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}
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/******************************************************************************
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*
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* Send queue
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*
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******************************************************************************
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*/
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/** Send queue configuration */
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#define TXNIC_QS_SQ_CFG(q) ( ( (q) << 18 ) | 0x010800 )
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#define TXNIC_QS_SQ_CFG_ENA ( 1ULL << 19 )
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#define TXNIC_QS_SQ_CFG_RESET ( 1ULL << 17 )
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#define TXNIC_QS_SQ_CFG_QSIZE(sz) ( ( ( uint64_t ) (sz) ) << 8 )
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#define TXNIC_QS_SQ_CFG_QSIZE_1K \
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TXNIC_QS_SQ_CFG_QSIZE ( 0 )
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/** Send queue base address */
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#define TXNIC_QS_SQ_BASE(q) ( ( (q) << 18 ) | 0x010820 )
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/** Send queue head pointer */
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#define TXNIC_QS_SQ_HEAD(q) ( ( (q) << 18 ) | 0x010828 )
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/** Send queue tail pointer */
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#define TXNIC_QS_SQ_TAIL(q) ( ( (q) << 18 ) | 0x010830 )
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/** Send queue doorbell */
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#define TXNIC_QS_SQ_DOOR(q) ( ( (q) << 18 ) | 0x010838 )
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/** Send queue status */
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#define TXNIC_QS_SQ_STATUS(q) ( ( (q) << 18 ) | 0x010840 )
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#define TXNIC_QS_SQ_STATUS_STOPPED ( 1ULL << 21 )
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/** Maximum time to wait for a send queue to stop
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*
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* This is a policy decision.
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*/
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#define TXNIC_SQ_STOP_MAX_WAIT_MS 100
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/** A send header subdescriptor */
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struct txnic_send_header {
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/** Total length */
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uint32_t total;
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/** Unused */
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uint8_t unused_a[2];
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/** Subdescriptor count */
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uint8_t subdcnt;
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/** Flags */
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uint8_t flags;
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/** Unused */
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uint8_t unused_b[8];
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} __attribute__ (( packed ));
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/** Flags for send header subdescriptor
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*
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* These comprise SUBDC=0x1 and PNC=0x1.
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*/
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#define TXNIC_SEND_HDR_FLAGS 0x14
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/** A send gather subdescriptor */
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struct txnic_send_gather {
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/** Size */
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uint16_t size;
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/** Unused */
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uint8_t unused[5];
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/** Flags */
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uint8_t flags;
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/** Address */
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uint64_t addr;
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} __attribute__ (( packed ));
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/** Flags for send gather subdescriptor
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*
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* These comprise SUBDC=0x4 and LD_TYPE=0x0.
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*/
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#define TXNIC_SEND_GATHER_FLAGS 0x40
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/** A send queue entry
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*
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* Each send queue entry comprises a single send header subdescriptor
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* and a single send gather subdescriptor.
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*/
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struct txnic_sqe {
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/** Send header descriptor */
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struct txnic_send_header hdr;
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/** Send gather descriptor */
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struct txnic_send_gather gather;
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} __attribute__ (( packed ));
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/** Number of subdescriptors per send queue entry */
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#define TXNIC_SQE_SUBDESCS ( sizeof ( struct txnic_sqe ) / \
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sizeof ( struct txnic_send_header ) )
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/** Number of send queue entries
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*
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* The minimum send queue size is 1024 entries.
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*/
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#define TXNIC_SQES ( 1024 / TXNIC_SQE_SUBDESCS )
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/** Send queue maximum fill level
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*
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* This is a policy decision.
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*/
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#define TXNIC_SQ_FILL 32
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/** Send queue alignment */
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#define TXNIC_SQ_ALIGN TXNIC_LINE_SIZE
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/** Send queue stride */
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#define TXNIC_SQ_STRIDE sizeof ( struct txnic_sqe )
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/** Send queue size */
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#define TXNIC_SQ_SIZE ( TXNIC_SQES * TXNIC_SQ_STRIDE )
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/** A send queue */
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struct txnic_sq {
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/** Producer counter */
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unsigned int prod;
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/** Consumer counter */
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unsigned int cons;
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/** Send queue entries */
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userptr_t sqe;
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};
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/******************************************************************************
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*
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* Receive queue
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*
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******************************************************************************
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*/
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/** Receive queue configuration */
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#define TXNIC_QS_RQ_CFG(q) ( ( (q) << 18 ) | 0x010600 )
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#define TXNIC_QS_RQ_CFG_ENA ( 1ULL << 1 )
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/** Maximum time to wait for a receive queue to disable
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*
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* This is a policy decision.
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*/
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#define TXNIC_RQ_DISABLE_MAX_WAIT_MS 100
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/** Receive buffer descriptor ring configuration */
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#define TXNIC_QS_RBDR_CFG(q) ( ( (q) << 18 ) | 0x010c00 )
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#define TXNIC_QS_RBDR_CFG_ENA ( 1ULL << 44 )
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#define TXNIC_QS_RBDR_CFG_RESET ( 1ULL << 43 )
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#define TXNIC_QS_RBDR_CFG_QSIZE(sz) ( ( ( uint64_t ) (sz) ) << 32 )
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#define TXNIC_QS_RBDR_CFG_QSIZE_8K \
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TXNIC_QS_RBDR_CFG_QSIZE ( 0 )
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#define TXNIC_QS_RBDR_CFG_LINES(sz) ( ( ( uint64_t ) (sz) ) << 0 )
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/** Receive buffer descriptor ring base address */
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#define TXNIC_QS_RBDR_BASE(q) ( ( (q) << 18 ) | 0x010c20 )
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/** Receive buffer descriptor ring head pointer */
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#define TXNIC_QS_RBDR_HEAD(q) ( ( (q) << 18 ) | 0x010c28 )
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/** Receive buffer descriptor ring tail pointer */
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#define TXNIC_QS_RBDR_TAIL(q) ( ( (q) << 18 ) | 0x010c30 )
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/** Receive buffer descriptor ring doorbell */
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#define TXNIC_QS_RBDR_DOOR(q) ( ( (q) << 18 ) | 0x010c38 )
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/** Receive buffer descriptor ring status 0 */
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#define TXNIC_QS_RBDR_STATUS0(q) ( ( (q) << 18 ) | 0x010c40 )
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/** A receive buffer descriptor ring entry */
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struct txnic_rbdr_entry {
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/** Address */
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uint64_t addr;
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} __attribute__ (( packed ));
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/** A receive queue entry */
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struct txnic_rqe {
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/** Receive buffer descriptor ring entry */
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struct txnic_rbdr_entry rbdre;
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} __attribute__ (( packed ));
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/** Number of receive queue entries
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*
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* The minimum receive queue size is 8192 entries.
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*/
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#define TXNIC_RQES 8192
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/** Receive queue maximum fill level
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*
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* This is a policy decision. Must not exceed TXNIC_RQES.
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*/
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#define TXNIC_RQ_FILL 32
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/** Receive queue entry size
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*
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* This is a policy decision.
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*/
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#define TXNIC_RQE_SIZE ( ( ETH_DATA_ALIGN + ETH_FRAME_LEN + \
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4 /* VLAN */ + TXNIC_LINE_SIZE - 1 ) \
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& ~( TXNIC_LINE_SIZE - 1 ) )
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/** Receive queue alignment */
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#define TXNIC_RQ_ALIGN TXNIC_LINE_SIZE
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/** Receive queue stride */
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#define TXNIC_RQ_STRIDE sizeof ( struct txnic_rqe )
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/** Receive queue size */
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#define TXNIC_RQ_SIZE ( TXNIC_RQES * TXNIC_RQ_STRIDE )
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/** A receive queue */
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struct txnic_rq {
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/** Producer counter */
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unsigned int prod;
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/** Consumer counter */
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unsigned int cons;
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/** Receive queue entries */
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userptr_t rqe;
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/** I/O buffers */
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struct io_buffer *iobuf[TXNIC_RQ_FILL];
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};
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/******************************************************************************
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*
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* Completion queue
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*
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******************************************************************************
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*/
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/** Completion queue configuration */
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#define TXNIC_QS_CQ_CFG(q) ( ( (q) << 18 ) | 0x010400 )
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#define TXNIC_QS_CQ_CFG_ENA ( 1ULL << 42 )
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#define TXNIC_QS_CQ_CFG_RESET ( 1ULL << 41 )
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#define TXNIC_QS_CQ_CFG_QSIZE(sz) ( ( ( uint64_t ) (sz) ) << 32 )
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#define TXNIC_QS_CQ_CFG_QSIZE_256 \
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TXNIC_QS_CQ_CFG_QSIZE ( 7 )
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/** Maximum time to wait for a completion queue to disable
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*
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* This is a policy decision.
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*/
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#define TXNIC_CQ_DISABLE_MAX_WAIT_MS 100
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/** Completion queue base address */
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#define TXNIC_QS_CQ_BASE(q) ( ( (q) << 18 ) | 0x010420 )
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/** Completion queue head pointer */
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#define TXNIC_QS_CQ_HEAD(q) ( ( (q) << 18 ) | 0x010428 )
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/** Completion queue tail pointer */
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#define TXNIC_QS_CQ_TAIL(q) ( ( (q) << 18 ) | 0x010430 )
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/** Completion queue doorbell */
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#define TXNIC_QS_CQ_DOOR(q) ( ( (q) << 18 ) | 0x010438 )
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/** Completion queue status */
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#define TXNIC_QS_CQ_STATUS(q) ( ( (q) << 18 ) | 0x010440 )
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#define TXNIC_QS_CQ_STATUS_QCOUNT(status) \
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( ( (status) >> 0 ) & 0xffff )
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/** Completion queue status 2 */
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#define TXNIC_QS_CQ_STATUS2(q) ( ( (q) << 18 ) | 0x010448 )
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/** A send completion queue entry */
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struct txnic_cqe_send {
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/** Status */
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uint8_t send_status;
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/** Unused */
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uint8_t unused[4];
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/** Send queue entry pointer */
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uint16_t sqe_ptr;
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/** Type */
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uint8_t cqe_type;
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} __attribute__ (( packed ));
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/** Send completion queue entry type */
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#define TXNIC_CQE_TYPE_SEND 0x80
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/** A receive completion queue entry */
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struct txnic_cqe_rx {
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/** Error opcode */
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uint8_t errop;
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/** Unused */
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uint8_t unused_a[6];
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/** Type */
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uint8_t cqe_type;
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/** Unused */
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uint8_t unused_b[1];
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/** Padding */
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uint8_t apad;
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/** Unused */
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uint8_t unused_c[4];
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/** Length */
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uint16_t len;
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} __attribute__ (( packed ));
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/** Receive completion queue entry type */
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#define TXNIC_CQE_TYPE_RX 0x20
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/** Applied padding */
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#define TXNIC_CQE_RX_APAD_LEN( apad ) ( (apad) >> 5 )
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/** Completion queue entry common fields */
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struct txnic_cqe_common {
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/** Unused */
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uint8_t unused_a[7];
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/** Type */
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uint8_t cqe_type;
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} __attribute__ (( packed ));
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/** A completion queue entry */
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union txnic_cqe {
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/** Common fields */
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struct txnic_cqe_common common;
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/** Send completion */
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struct txnic_cqe_send send;
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/** Receive completion */
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struct txnic_cqe_rx rx;
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};
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/** Number of completion queue entries
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*
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* The minimum completion queue size is 256 entries.
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*/
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#define TXNIC_CQES 256
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/** Completion queue alignment */
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#define TXNIC_CQ_ALIGN 512
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/** Completion queue stride */
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#define TXNIC_CQ_STRIDE 512
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/** Completion queue size */
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#define TXNIC_CQ_SIZE ( TXNIC_CQES * TXNIC_CQ_STRIDE )
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/** A completion queue */
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struct txnic_cq {
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/** Consumer counter */
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unsigned int cons;
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/** Completion queue entries */
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userptr_t cqe;
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};
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/******************************************************************************
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*
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* Virtual NIC
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*
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******************************************************************************
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*/
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/** A virtual NIC */
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struct txnic {
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/** Registers */
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void *regs;
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/** Device name (for debugging) */
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const char *name;
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/** Network device */
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struct net_device *netdev;
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/** Send queue */
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struct txnic_sq sq;
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/** Receive queue */
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struct txnic_rq rq;
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/** Completion queue */
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struct txnic_cq cq;
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};
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/******************************************************************************
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*
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* Physical function
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*
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******************************************************************************
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*/
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/** Physical function configuration */
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#define TXNIC_PF_CFG 0x000000
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#define TXNIC_PF_CFG_ENA ( 1ULL << 0 )
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/** Backpressure configuration */
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#define TXNIC_PF_BP_CFG 0x000080
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#define TXNIC_PF_BP_CFG_BP_POLL_ENA ( 1ULL << 6 )
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#define TXNIC_PF_BP_CFG_BP_POLL_DLY(dl) ( ( ( uint64_t ) (dl) ) << 0 )
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#define TXNIC_PF_BP_CFG_BP_POLL_DLY_DEFAULT \
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TXNIC_PF_BP_CFG_BP_POLL_DLY ( 3 )
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/** Interface send configuration */
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#define TXNIC_PF_INTF_SEND_CFG(in) ( ( (in) << 8 ) | 0x000200 )
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#define TXNIC_PF_INTF_SEND_CFG_BLOCK_BGX ( 1ULL << 3 )
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#define TXNIC_PF_INTF_SEND_CFG_BLOCK(bl) ( ( ( uint64_t ) (bl) ) << 0 )
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/** Interface backpressure configuration */
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#define TXNIC_PF_INTF_BP_CFG(in) ( ( (in) << 8 ) | 0x000208 )
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#define TXNIC_PF_INTF_BP_CFG_BP_ENA ( 1ULL << 63 )
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#define TXNIC_PF_INTF_BP_CFG_BP_ID_BGX ( 1ULL << 3 )
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#define TXNIC_PF_INTF_BP_CFG_BP_ID(bp) ( ( ( uint64_t ) (bp) ) << 0 )
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/** Port kind configuration */
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#define TXNIC_PF_PKIND_CFG(pk) ( ( (pk) << 3 ) | 0x000600 )
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#define TXNIC_PF_PKIND_CFG_LENERR_EN ( 1ULL << 33 )
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#define TXNIC_PF_PKIND_CFG_MAXLEN(ct) ( ( ( uint64_t ) (ct) ) << 16 )
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#define TXNIC_PF_PKIND_CFG_MAXLEN_DISABLE \
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TXNIC_PF_PKIND_CFG_MAXLEN ( 0xffff )
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#define TXNIC_PF_PKIND_CFG_MINLEN(ct) ( ( ( uint64_t ) (ct) ) << 0 )
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#define TXNIC_PF_PKIND_CFG_MINLEN_DISABLE \
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TXNIC_PF_PKIND_CFG_MINLEN ( 0x0000 )
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/** Match parse index configuration */
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#define TXNIC_PF_MPI_CFG(ix) ( ( (ix) << 3 ) | 0x210000 )
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#define TXNIC_PF_MPI_CFG_VNIC(vn) ( ( ( uint64_t ) (vn) ) << 24 )
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#define TXNIC_PF_MPI_CFG_RSSI_BASE(ix) ( ( ( uint64_t ) (ix) ) << 0 )
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/** RSS indirection receive queue */
|
||||
#define TXNIC_PF_RSSI_RQ(ix) ( ( (ix) << 3 ) | 0x220000 )
|
||||
#define TXNIC_PF_RSSI_RQ_RQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 3 )
|
||||
|
||||
/** LMAC registers */
|
||||
#define TXNIC_PF_LMAC(lm) ( ( (lm) << 3 ) | 0x240000 )
|
||||
|
||||
/** LMAC configuration */
|
||||
#define TXNIC_PF_LMAC_CFG 0x000000
|
||||
#define TXNIC_PF_LMAC_CFG_ADJUST(ad) ( ( ( uint64_t ) (ad) ) << 8 )
|
||||
#define TXNIC_PF_LMAC_CFG_ADJUST_DEFAULT \
|
||||
TXNIC_PF_LMAC_CFG_ADJUST ( 6 )
|
||||
#define TXNIC_PF_LMAC_CFG_MIN_PKT_SIZE(sz) ( ( ( uint64_t ) (sz) ) << 0 )
|
||||
|
||||
/** LMAC configuration 2 */
|
||||
#define TXNIC_PF_LMAC_CFG2 0x000100
|
||||
#define TXNIC_PF_LMAC_CFG2_MAX_PKT_SIZE(sz) ( ( ( uint64_t ) (sz) ) << 0 )
|
||||
|
||||
/** LMAC credit */
|
||||
#define TXNIC_PF_LMAC_CREDIT 0x004000
|
||||
#define TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT(ct) ( ( ( uint64_t ) (ct) ) << 12 )
|
||||
#define TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT_DEFAULT \
|
||||
TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT ( 192 )
|
||||
#define TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT(ct) ( ( ( uint64_t ) (ct) ) << 2 )
|
||||
#define TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT_DEFAULT \
|
||||
TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT ( 511 )
|
||||
#define TXNIC_PF_LMAC_CREDIT_CC_ENABLE ( 1ULL << 1 )
|
||||
|
||||
/** Channel registers */
|
||||
#define TXNIC_PF_CHAN(ch) ( ( (ch) << 3 ) | 0x400000 )
|
||||
|
||||
/** Channel transmit configuration */
|
||||
#define TXNIC_PF_CHAN_TX_CFG 0x000000
|
||||
#define TXNIC_PF_CHAN_TX_CFG_BP_ENA ( 1ULL << 0 )
|
||||
|
||||
/** Channel receive configuration */
|
||||
#define TXNIC_PF_CHAN_RX_CFG 0x020000
|
||||
#define TXNIC_PF_CHAN_RX_CFG_CPI_BASE(ix) ( ( ( uint64_t ) (ix) ) << 48 )
|
||||
|
||||
/** Channel receive backpressure configuration */
|
||||
#define TXNIC_PF_CHAN_RX_BP_CFG 0x080000
|
||||
#define TXNIC_PF_CHAN_RX_BP_CFG_ENA ( 1ULL << 63 )
|
||||
#define TXNIC_PF_CHAN_RX_BP_CFG_BPID(bp) ( ( ( uint64_t ) (bp) ) << 0 )
|
||||
|
||||
/** Traffic limiter 2 configuration */
|
||||
#define TXNIC_PF_TL2_CFG(tl) ( ( (tl) << 3 ) | 0x500000 )
|
||||
#define TXNIC_PF_TL2_CFG_RR_QUANTUM(rr) ( ( ( uint64_t ) (rr) ) << 0 )
|
||||
#define TXNIC_PF_TL2_CFG_RR_QUANTUM_DEFAULT \
|
||||
TXNIC_PF_TL2_CFG_RR_QUANTUM ( 0x905 )
|
||||
|
||||
/** Traffic limiter 3 configuration */
|
||||
#define TXNIC_PF_TL3_CFG(tl) ( ( (tl) << 3 ) | 0x600000 )
|
||||
#define TXNIC_PF_TL3_CFG_RR_QUANTUM(rr) ( ( ( uint64_t ) (rr) ) << 0 )
|
||||
#define TXNIC_PF_TL3_CFG_RR_QUANTUM_DEFAULT \
|
||||
TXNIC_PF_TL3_CFG_RR_QUANTUM ( 0x905 )
|
||||
|
||||
/** Traffic limiter 3 channel mapping */
|
||||
#define TXNIC_PF_TL3_CHAN(tl) ( ( (tl) << 3 ) | 0x620000 )
|
||||
#define TXNIC_PF_TL3_CHAN_CHAN(ch) ( ( (ch) & 0x7f ) << 0 )
|
||||
|
||||
/** Traffic limiter 4 configuration */
|
||||
#define TXNIC_PF_TL4_CFG(tl) ( ( (tl) << 3 ) | 0x800000 )
|
||||
#define TXNIC_PF_TL4_CFG_SQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 27 )
|
||||
#define TXNIC_PF_TL4_CFG_RR_QUANTUM(rr) ( ( ( uint64_t ) (rr) ) << 0 )
|
||||
#define TXNIC_PF_TL4_CFG_RR_QUANTUM_DEFAULT \
|
||||
TXNIC_PF_TL4_CFG_RR_QUANTUM ( 0x905 )
|
||||
|
||||
/** Queue set registers */
|
||||
#define TXNIC_PF_QS(qs) ( ( (qs) << 21 ) | 0x20000000UL )
|
||||
|
||||
/** Queue set configuration */
|
||||
#define TXNIC_PF_QS_CFG 0x010000
|
||||
#define TXNIC_PF_QS_CFG_ENA ( 1ULL << 31 )
|
||||
#define TXNIC_PF_QS_CFG_VNIC(vn) ( ( ( uint64_t ) (vn) ) << 0 )
|
||||
|
||||
/** Receive queue configuration */
|
||||
#define TXNIC_PF_QS_RQ_CFG(q) ( ( (q) << 18 ) | 0x010400 )
|
||||
#define TXNIC_PF_QS_RQ_CFG_CACHING(cx) ( ( ( uint64_t ) (cx) ) << 26 )
|
||||
#define TXNIC_PF_QS_RQ_CFG_CACHING_ALL \
|
||||
TXNIC_PF_QS_RQ_CFG_CACHING ( 1 )
|
||||
#define TXNIC_PF_QS_RQ_CFG_CQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 19 )
|
||||
#define TXNIC_PF_QS_RQ_CFG_RBDR_CONT_QS(qs) ( ( ( uint64_t ) (qs) ) << 9 )
|
||||
#define TXNIC_PF_QS_RQ_CFG_RBDR_STRT_QS(qs) ( ( ( uint64_t ) (qs) ) << 1 )
|
||||
|
||||
/** Receive queue drop configuration */
|
||||
#define TXNIC_PF_QS_RQ_DROP_CFG(q) ( ( (q) << 18 ) | 0x010420 )
|
||||
|
||||
/** Receive queue backpressure configuration */
|
||||
#define TXNIC_PF_QS_RQ_BP_CFG(q) ( ( (q) << 18 ) | 0x010500 )
|
||||
#define TXNIC_PF_QS_RQ_BP_CFG_RBDR_BP_ENA ( 1ULL << 63 )
|
||||
#define TXNIC_PF_QS_RQ_BP_CFG_CQ_BP_ENA ( 1ULL << 62 )
|
||||
#define TXNIC_PF_QS_RQ_BP_CFG_BPID(bp) ( ( ( uint64_t ) (bp) ) << 0 )
|
||||
|
||||
/** Send queue configuration */
|
||||
#define TXNIC_PF_QS_SQ_CFG(q) ( ( (q) << 18 ) | 0x010c00 )
|
||||
#define TXNIC_PF_QS_SQ_CFG_CQ_QS(qs) ( ( ( uint64_t ) (qs) ) << 3 )
|
||||
|
||||
/** Send queue configuration 2 */
|
||||
#define TXNIC_PF_QS_SQ_CFG2(q) ( ( (q) << 18 ) | 0x010c08 )
|
||||
#define TXNIC_PF_QS_SQ_CFG2_TL4(tl) ( ( ( uint64_t ) (tl) ) << 0 )
|
||||
|
||||
/** A physical function */
|
||||
struct txnic_pf {
|
||||
/** Registers */
|
||||
void *regs;
|
||||
/** PCI device */
|
||||
struct pci_device *pci;
|
||||
/** Node ID */
|
||||
unsigned int node;
|
||||
|
||||
/** Virtual function BAR base */
|
||||
unsigned long vf_membase;
|
||||
/** Virtual function BAR stride */
|
||||
unsigned long vf_stride;
|
||||
|
||||
/** List of physical functions */
|
||||
struct list_head list;
|
||||
/** BGX Ethernet interfaces (if known) */
|
||||
struct txnic_bgx *bgx[TXNIC_NUM_BGX];
|
||||
};
|
||||
|
||||
/**
|
||||
* Calculate virtual NIC index
|
||||
*
|
||||
* @v bgx_idx BGX Ethernet interface index
|
||||
* @v lmac_idx Logical MAC index
|
||||
* @ret vnic_idx Virtual NIC index
|
||||
*/
|
||||
#define TXNIC_VNIC_IDX( bgx_idx, lmac_idx ) \
|
||||
( ( (bgx_idx) * TXNIC_NUM_LMAC ) + (lmac_idx) )
|
||||
|
||||
/**
|
||||
* Calculate BGX Ethernet interface index
|
||||
*
|
||||
* @v vnic_idx Virtual NIC index
|
||||
* @ret bgx_idx BGX Ethernet interface index
|
||||
*/
|
||||
#define TXNIC_BGX_IDX( vnic_idx ) ( (vnic_idx) / TXNIC_NUM_LMAC )
|
||||
|
||||
/**
|
||||
* Calculate logical MAC index
|
||||
*
|
||||
* @v vnic_idx Virtual NIC index
|
||||
* @ret lmac_idx Logical MAC index
|
||||
*/
|
||||
#define TXNIC_LMAC_IDX( vnic_idx ) ( (vnic_idx) % TXNIC_NUM_LMAC )
|
||||
|
||||
/**
|
||||
* Calculate traffic limiter 2 index
|
||||
*
|
||||
* @v vnic_idx Virtual NIC index
|
||||
* @v tl2_idx Traffic limiter 2 index
|
||||
*/
|
||||
#define TXNIC_TL2_IDX( vnic_idx ) ( (vnic_idx) << 3 )
|
||||
|
||||
/**
|
||||
* Calculate traffic limiter 3 index
|
||||
*
|
||||
* @v vnic_idx Virtual NIC index
|
||||
* @v tl3_idx Traffic limiter 3 index
|
||||
*/
|
||||
#define TXNIC_TL3_IDX( vnic_idx ) ( (vnic_idx) << 5 )
|
||||
|
||||
/**
|
||||
* Calculate traffic limiter 4 index
|
||||
*
|
||||
* @v vnic_idx Virtual NIC index
|
||||
* @v tl4_idx Traffic limiter 4 index
|
||||
*/
|
||||
#define TXNIC_TL4_IDX( vnic_idx ) ( (vnic_idx) << 7 )
|
||||
|
||||
/**
|
||||
* Calculate channel index
|
||||
*
|
||||
* @v vnic_idx Virtual NIC index
|
||||
* @v chan_idx Channel index
|
||||
*/
|
||||
#define TXNIC_CHAN_IDX( vnic_idx ) ( ( TXNIC_BGX_IDX (vnic_idx) << 7 ) | \
|
||||
( TXNIC_LMAC_IDX (vnic_idx) << 4 ) )
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* BGX Ethernet interface
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** Per-LMAC registers */
|
||||
#define BGX_LMAC(lm) ( ( (lm) << 20 ) | 0x00000000UL )
|
||||
|
||||
/** CMR configuration */
|
||||
#define BGX_CMR_CONFIG 0x000000
|
||||
#define BGX_CMR_CONFIG_ENABLE ( 1ULL << 15 )
|
||||
#define BGX_CMR_CONFIG_DATA_PKT_RX_EN ( 1ULL << 14 )
|
||||
#define BGX_CMR_CONFIG_DATA_PKT_TX_EN ( 1ULL << 13 )
|
||||
#define BGX_CMR_CONFIG_LMAC_TYPE_GET(config) \
|
||||
( ( (config) >> 8 ) & 0x7 )
|
||||
#define BGX_CMR_CONFIG_LMAC_TYPE_SET(ty) ( ( ( uint64_t ) (ty) ) << 8 )
|
||||
#define BGX_CMR_CONFIG_LANE_TO_SDS(ls) ( ( ( uint64_t ) (ls) ) << 0 )
|
||||
|
||||
/** CMR global configuration */
|
||||
#define BGX_CMR_GLOBAL_CONFIG 0x000008
|
||||
#define BGX_CMR_GLOBAL_CONFIG_FCS_STRIP ( 1ULL << 6 )
|
||||
|
||||
/** CMR receive statistics 0 */
|
||||
#define BGX_CMR_RX_STAT0 0x000070
|
||||
|
||||
/** CMR receive statistics 1 */
|
||||
#define BGX_CMR_RX_STAT1 0x000078
|
||||
|
||||
/** CMR receive statistics 2 */
|
||||
#define BGX_CMR_RX_STAT2 0x000080
|
||||
|
||||
/** CMR receive statistics 3 */
|
||||
#define BGX_CMR_RX_STAT3 0x000088
|
||||
|
||||
/** CMR receive statistics 4 */
|
||||
#define BGX_CMR_RX_STAT4 0x000090
|
||||
|
||||
/** CMR receive statistics 5 */
|
||||
#define BGX_CMR_RX_STAT5 0x000098
|
||||
|
||||
/** CMR receive statistics 6 */
|
||||
#define BGX_CMR_RX_STAT6 0x0000a0
|
||||
|
||||
/** CMR receive statistics 7 */
|
||||
#define BGX_CMR_RX_STAT7 0x0000a8
|
||||
|
||||
/** CMR receive statistics 8 */
|
||||
#define BGX_CMR_RX_STAT8 0x0000b0
|
||||
|
||||
/** CMR receive statistics 9 */
|
||||
#define BGX_CMR_RX_STAT9 0x0000b8
|
||||
|
||||
/** CMR receive statistics 10 */
|
||||
#define BGX_CMR_RX_STAT10 0x0000c0
|
||||
|
||||
/** CMR destination MAC control */
|
||||
#define BGX_CMR_RX_DMAC_CTL 0x0000e8
|
||||
#define BGX_CMR_RX_DMAC_CTL_MCST_MODE(md) ( ( ( uint64_t ) (md) ) << 1 )
|
||||
#define BGX_CMR_RX_DMAC_CTL_MCST_MODE_ACCEPT \
|
||||
BGX_CMR_RX_DMAC_CTL_MCST_MODE ( 1 )
|
||||
#define BGX_CMR_RX_DMAC_CTL_BCST_ACCEPT ( 1ULL << 0 )
|
||||
|
||||
/** CMR destination MAC CAM */
|
||||
#define BGX_CMR_RX_DMAC_CAM(i) ( ( (i) << 3 ) | 0x000200 )
|
||||
|
||||
/** CMR receive steering */
|
||||
#define BGX_CMR_RX_STEERING(i) ( ( (i) << 3 ) | 0x000300 )
|
||||
|
||||
/** CMR backpressure channel mask AND */
|
||||
#define BGX_CMR_CHAN_MSK_AND 0x000450
|
||||
#define BGX_CMR_CHAN_MSK_AND_ALL(count) \
|
||||
( 0xffffffffffffffffULL >> ( 16 * ( 4 - (count) ) ) )
|
||||
|
||||
/** CMR transmit statistics 0 */
|
||||
#define BGX_CMR_TX_STAT0 0x000600
|
||||
|
||||
/** CMR transmit statistics 1 */
|
||||
#define BGX_CMR_TX_STAT1 0x000608
|
||||
|
||||
/** CMR transmit statistics 2 */
|
||||
#define BGX_CMR_TX_STAT2 0x000610
|
||||
|
||||
/** CMR transmit statistics 3 */
|
||||
#define BGX_CMR_TX_STAT3 0x000618
|
||||
|
||||
/** CMR transmit statistics 4 */
|
||||
#define BGX_CMR_TX_STAT4 0x000620
|
||||
|
||||
/** CMR transmit statistics 5 */
|
||||
#define BGX_CMR_TX_STAT5 0x000628
|
||||
|
||||
/** CMR transmit statistics 6 */
|
||||
#define BGX_CMR_TX_STAT6 0x000630
|
||||
|
||||
/** CMR transmit statistics 7 */
|
||||
#define BGX_CMR_TX_STAT7 0x000638
|
||||
|
||||
/** CMR transmit statistics 8 */
|
||||
#define BGX_CMR_TX_STAT8 0x000640
|
||||
|
||||
/** CMR transmit statistics 9 */
|
||||
#define BGX_CMR_TX_STAT9 0x000648
|
||||
|
||||
/** CMR transmit statistics 10 */
|
||||
#define BGX_CMR_TX_STAT10 0x000650
|
||||
|
||||
/** CMR transmit statistics 11 */
|
||||
#define BGX_CMR_TX_STAT11 0x000658
|
||||
|
||||
/** CMR transmit statistics 12 */
|
||||
#define BGX_CMR_TX_STAT12 0x000660
|
||||
|
||||
/** CMR transmit statistics 13 */
|
||||
#define BGX_CMR_TX_STAT13 0x000668
|
||||
|
||||
/** CMR transmit statistics 14 */
|
||||
#define BGX_CMR_TX_STAT14 0x000670
|
||||
|
||||
/** CMR transmit statistics 15 */
|
||||
#define BGX_CMR_TX_STAT15 0x000678
|
||||
|
||||
/** CMR transmit statistics 16 */
|
||||
#define BGX_CMR_TX_STAT16 0x000680
|
||||
|
||||
/** CMR transmit statistics 17 */
|
||||
#define BGX_CMR_TX_STAT17 0x000688
|
||||
|
||||
/** CMR receive logical MACs */
|
||||
#define BGX_CMR_RX_LMACS 0x000468
|
||||
#define BGX_CMR_RX_LMACS_LMACS_GET(lmacs) \
|
||||
( ( (lmacs) >> 0 ) & 0x7 )
|
||||
#define BGX_CMR_RX_LMACS_LMACS_SET(ct) ( ( ( uint64_t ) (ct) ) << 0 )
|
||||
|
||||
/** CMR transmit logical MACs */
|
||||
#define BGX_CMR_TX_LMACS 0x001000
|
||||
#define BGX_CMR_TX_LMACS_LMACS_GET(lmacs) \
|
||||
( ( (lmacs) >> 0 ) & 0x7 )
|
||||
#define BGX_CMR_TX_LMACS_LMACS_SET(ct) ( ( ( uint64_t ) (ct) ) << 0 )
|
||||
|
||||
/** SPU control 1 */
|
||||
#define BGX_SPU_CONTROL1 0x010000
|
||||
#define BGX_SPU_CONTROL1_RESET ( 1ULL << 15 )
|
||||
#define BGX_SPU_CONTROL1_LO_PWR ( 1ULL << 11 )
|
||||
|
||||
/** SPU reset delay */
|
||||
#define BGX_SPU_RESET_DELAY_MS 10
|
||||
|
||||
/** SPU status 1 */
|
||||
#define BGX_SPU_STATUS1 0x010008
|
||||
#define BGX_SPU_STATUS1_FLT ( 1ULL << 7 )
|
||||
#define BGX_SPU_STATUS1_RCV_LNK ( 1ULL << 2 )
|
||||
|
||||
/** SPU status 2 */
|
||||
#define BGX_SPU_STATUS2 0x010020
|
||||
#define BGX_SPU_STATUS2_RCVFLT ( 1ULL << 10 )
|
||||
|
||||
/** SPU BASE-R status 1 */
|
||||
#define BGX_SPU_BR_STATUS1 0x010030
|
||||
#define BGX_SPU_BR_STATUS1_RCV_LNK ( 1ULL << 12 )
|
||||
#define BGX_SPU_BR_STATUS1_HI_BER ( 1ULL << 1 )
|
||||
#define BGX_SPU_BR_STATUS1_BLK_LOCK ( 1ULL << 0 )
|
||||
|
||||
/** SPU BASE-R status 2 */
|
||||
#define BGX_SPU_BR_STATUS2 0x010038
|
||||
#define BGX_SPU_BR_STATUS2_LATCHED_LOCK ( 1ULL << 15 )
|
||||
#define BGX_SPU_BR_STATUS2_LATCHED_BER ( 1ULL << 14 )
|
||||
|
||||
/** SPU BASE-R alignment status */
|
||||
#define BGX_SPU_BR_ALGN_STATUS 0x010050
|
||||
#define BGX_SPU_BR_ALGN_STATUS_ALIGND ( 1ULL << 12 )
|
||||
|
||||
/** SPU BASE-R link training control */
|
||||
#define BGX_SPU_BR_PMD_CONTROL 0x010068
|
||||
#define BGX_SPU_BR_PMD_CONTROL_TRAIN_EN ( 1ULL << 1 )
|
||||
|
||||
/** SPU BASE-R link training status */
|
||||
#define BGX_SPU_BR_PMD_STATUS 0x010070
|
||||
|
||||
/** SPU link partner coefficient update */
|
||||
#define BGX_SPU_BR_PMD_LP_CUP 0x010078
|
||||
|
||||
/** SPU local device coefficient update */
|
||||
#define BGX_SPU_BR_PMD_LD_CUP 0x010088
|
||||
|
||||
/** SPU local device status report */
|
||||
#define BGX_SPU_BR_PMD_LD_REP 0x010090
|
||||
|
||||
/** SPU forward error correction control */
|
||||
#define BGX_SPU_FEC_CONTROL 0x0100a0
|
||||
|
||||
/** SPU autonegotation control */
|
||||
#define BGX_SPU_AN_CONTROL 0x0100c8
|
||||
|
||||
/** SPU autonegotiation status */
|
||||
#define BGX_SPU_AN_STATUS 0x0100d0
|
||||
#define BGX_SPU_AN_STATUS_XNP_STAT ( 1ULL << 7 )
|
||||
#define BGX_SPU_AN_STATUS_PAGE_RX ( 1ULL << 6 )
|
||||
#define BGX_SPU_AN_STATUS_AN_COMPLETE ( 1ULL << 5 )
|
||||
#define BGX_SPU_AN_STATUS_LINK_STATUS ( 1ULL << 2 )
|
||||
#define BGX_SPU_AN_STATUS_LP_AN_ABLE ( 1ULL << 0 )
|
||||
|
||||
/** SPU interrupt */
|
||||
#define BGX_SPU_INT 0x010220
|
||||
#define BGX_SPU_INT_TRAINING_FAIL ( 1ULL << 14 )
|
||||
#define BGX_SPU_INT_TRAINING_DONE ( 1ULL << 13 )
|
||||
#define BGX_SPU_INT_AN_COMPLETE ( 1ULL << 12 )
|
||||
#define BGX_SPU_INT_AN_LINK_GOOD ( 1ULL << 11 )
|
||||
#define BGX_SPU_INT_AN_PAGE_RX ( 1ULL << 10 )
|
||||
#define BGX_SPU_INT_FEC_UNCORR ( 1ULL << 9 )
|
||||
#define BGX_SPU_INT_FEC_CORR ( 1ULL << 8 )
|
||||
#define BGX_SPU_INT_BIP_ERR ( 1ULL << 7 )
|
||||
#define BGX_SPU_INT_DBG_SYNC ( 1ULL << 6 )
|
||||
#define BGX_SPU_INT_ALGNLOS ( 1ULL << 5 )
|
||||
#define BGX_SPU_INT_SYNLOS ( 1ULL << 4 )
|
||||
#define BGX_SPU_INT_BITLCKLS ( 1ULL << 3 )
|
||||
#define BGX_SPU_INT_ERR_BLK ( 1ULL << 2 )
|
||||
#define BGX_SPU_INT_RX_LINK_DOWN ( 1ULL << 1 )
|
||||
#define BGX_SPU_INT_RX_LINK_UP ( 1ULL << 0 )
|
||||
|
||||
/** LMAC types */
|
||||
enum txnic_lmac_types {
|
||||
TXNIC_LMAC_SGMII = 0x0, /**< SGMII/1000BASE-X */
|
||||
TXNIC_LMAC_XAUI = 0x1, /**< 10GBASE-X/XAUI or DXAUI */
|
||||
TXNIC_LMAC_RXAUI = 0x2, /**< Reduced XAUI */
|
||||
TXNIC_LMAC_10G_R = 0x3, /**< 10GBASE-R */
|
||||
TXNIC_LMAC_40G_R = 0x4, /**< 40GBASE-R */
|
||||
};
|
||||
|
||||
/** An LMAC type */
|
||||
struct txnic_lmac_type {
|
||||
/** Name */
|
||||
const char *name;
|
||||
/** Number of LMACs */
|
||||
uint8_t count;
|
||||
/** Lane-to-SDS mapping */
|
||||
uint32_t lane_to_sds;
|
||||
};
|
||||
|
||||
/** An LMAC address */
|
||||
union txnic_lmac_address {
|
||||
struct {
|
||||
uint8_t pad[2];
|
||||
uint8_t raw[ETH_ALEN];
|
||||
} __attribute__ (( packed ));
|
||||
uint64_t be64;
|
||||
};
|
||||
|
||||
/** A Logical MAC (LMAC) */
|
||||
struct txnic_lmac {
|
||||
/** Registers */
|
||||
void *regs;
|
||||
/** Containing BGX Ethernet interface */
|
||||
struct txnic_bgx *bgx;
|
||||
/** Virtual NIC index */
|
||||
unsigned int idx;
|
||||
|
||||
/** MAC address */
|
||||
union txnic_lmac_address mac;
|
||||
|
||||
/** Virtual NIC (if applicable) */
|
||||
struct txnic *vnic;
|
||||
};
|
||||
|
||||
/** A BGX Ethernet interface */
|
||||
struct txnic_bgx {
|
||||
/** Registers */
|
||||
void *regs;
|
||||
/** PCI device */
|
||||
struct pci_device *pci;
|
||||
/** Node ID */
|
||||
unsigned int node;
|
||||
/** BGX index */
|
||||
unsigned int idx;
|
||||
|
||||
/** LMAC type */
|
||||
struct txnic_lmac_type *type;
|
||||
/** Number of LMACs */
|
||||
unsigned int count;
|
||||
/** Link training is in use */
|
||||
int training;
|
||||
|
||||
/** List of BGX Ethernet interfaces */
|
||||
struct list_head list;
|
||||
/** Physical function (if known) */
|
||||
struct txnic_pf *pf;
|
||||
|
||||
/** Logical MACs */
|
||||
struct txnic_lmac lmac[TXNIC_NUM_LMAC];
|
||||
};
|
||||
|
||||
#endif /* _THUNDERX_H */
|
||||
|
|
@ -191,6 +191,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
|
|||
#define ERRFILE_virtio_pci ( ERRFILE_DRIVER | 0x007f0000 )
|
||||
#define ERRFILE_pciea ( ERRFILE_DRIVER | 0x00c00000 )
|
||||
#define ERRFILE_axge ( ERRFILE_DRIVER | 0x00c10000 )
|
||||
#define ERRFILE_thunderx ( ERRFILE_DRIVER | 0x00c20000 )
|
||||
|
||||
#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
|
||||
#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )
|
||||
|
|
|
|||
Reference in New Issue