[phantom] Add support for NetXen Phantom NICs
This commit is contained in:
Michael Brown
parent
227bb05a50
commit
3ad348e55a
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@ -146,6 +146,7 @@ SRCDIRS += image
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SRCDIRS += drivers/bus
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SRCDIRS += drivers/net
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SRCDIRS += drivers/net/e1000
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SRCDIRS += drivers/net/phantom
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SRCDIRS += drivers/block
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SRCDIRS += drivers/nvs
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SRCDIRS += drivers/bitbash
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@ -0,0 +1,192 @@
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#ifndef _NX_BITOPS_H
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#define _NX_BITOPS_H
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/*
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* Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/**
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* @file
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*
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* NetXen bit operations
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*
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*/
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/** Datatype used to represent a bit in the pseudo-structures */
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typedef unsigned char pseudo_bit_t;
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/**
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* Wrapper structure for pseudo_bit_t structures
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*
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* This structure provides a wrapper around pseudo_bit_t structures.
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* It has the correct size, and also encapsulates type information
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* about the underlying pseudo_bit_t-based structure, which allows the
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* NX_FILL etc. macros to work without requiring explicit type
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* information.
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*/
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#define NX_PSEUDO_BIT_STRUCT( _structure ) \
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union { \
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uint8_t bytes[ sizeof ( _structure ) / 8 ]; \
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uint64_t qwords[ sizeof ( _structure ) / 64 ]; \
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_structure *dummy[0]; \
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} u;
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/** Get pseudo_bit_t structure type from wrapper structure pointer */
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#define NX_PSEUDO_STRUCT( _ptr ) \
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typeof ( *((_ptr)->u.dummy[0]) )
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/** Bit offset of a field within a pseudo_bit_t structure */
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#define NX_BIT_OFFSET( _ptr, _field ) \
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offsetof ( NX_PSEUDO_STRUCT ( _ptr ), _field )
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/** Bit width of a field within a pseudo_bit_t structure */
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#define NX_BIT_WIDTH( _ptr, _field ) \
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sizeof ( ( ( NX_PSEUDO_STRUCT ( _ptr ) * ) NULL )->_field )
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/** Qword offset of a field within a pseudo_bit_t structure */
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#define NX_QWORD_OFFSET( _ptr, _field ) \
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( NX_BIT_OFFSET ( _ptr, _field ) / 64 )
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/** Qword bit offset of a field within a pseudo_bit_t structure
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*
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* Yes, using mod-64 would work, but would lose the check for the
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* error of specifying a mismatched field name and qword index.
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*/
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#define NX_QWORD_BIT_OFFSET( _ptr, _index, _field ) \
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( NX_BIT_OFFSET ( _ptr, _field ) - ( 64 * (_index) ) )
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/** Bit mask for a field within a pseudo_bit_t structure */
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#define NX_BIT_MASK( _ptr, _field ) \
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( ( ~( ( uint64_t ) 0 ) ) >> \
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( 64 - NX_BIT_WIDTH ( _ptr, _field ) ) )
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/*
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* Assemble native-endian qword from named fields and values
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*
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*/
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#define NX_ASSEMBLE_1( _ptr, _index, _field, _value ) \
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( ( ( uint64_t) (_value) ) << \
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NX_QWORD_BIT_OFFSET ( _ptr, _index, _field ) )
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#define NX_ASSEMBLE_2( _ptr, _index, _field, _value, ... ) \
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( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
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NX_ASSEMBLE_1 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_ASSEMBLE_3( _ptr, _index, _field, _value, ... ) \
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( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
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NX_ASSEMBLE_2 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_ASSEMBLE_4( _ptr, _index, _field, _value, ... ) \
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( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
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NX_ASSEMBLE_3 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_ASSEMBLE_5( _ptr, _index, _field, _value, ... ) \
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( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
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NX_ASSEMBLE_4 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_ASSEMBLE_6( _ptr, _index, _field, _value, ... ) \
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( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
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NX_ASSEMBLE_5 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_ASSEMBLE_7( _ptr, _index, _field, _value, ... ) \
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( NX_ASSEMBLE_1 ( _ptr, _index, _field, _value ) | \
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NX_ASSEMBLE_6 ( _ptr, _index, __VA_ARGS__ ) )
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/*
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* Build native-endian (positive) qword bitmasks from named fields
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*
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*/
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#define NX_MASK_1( _ptr, _index, _field ) \
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( NX_BIT_MASK ( _ptr, _field ) << \
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NX_QWORD_BIT_OFFSET ( _ptr, _index, _field ) )
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#define NX_MASK_2( _ptr, _index, _field, ... ) \
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( NX_MASK_1 ( _ptr, _index, _field ) | \
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NX_MASK_1 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_MASK_3( _ptr, _index, _field, ... ) \
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( NX_MASK_1 ( _ptr, _index, _field ) | \
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NX_MASK_2 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_MASK_4( _ptr, _index, _field, ... ) \
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( NX_MASK_1 ( _ptr, _index, _field ) | \
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NX_MASK_3 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_MASK_5( _ptr, _index, _field, ... ) \
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( NX_MASK_1 ( _ptr, _index, _field ) | \
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NX_MASK_4 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_MASK_6( _ptr, _index, _field, ... ) \
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( NX_MASK_1 ( _ptr, _index, _field ) | \
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NX_MASK_5 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_MASK_7( _ptr, _index, _field, ... ) \
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( NX_MASK_1 ( _ptr, _index, _field ) | \
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NX_MASK_6 ( _ptr, _index, __VA_ARGS__ ) )
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/*
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* Populate big-endian qwords from named fields and values
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*
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*/
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#define NX_FILL( _ptr, _index, _assembled ) \
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do { \
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uint64_t *__ptr = &(_ptr)->u.qwords[(_index)]; \
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uint64_t __assembled = (_assembled); \
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*__ptr = cpu_to_le64 ( __assembled ); \
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} while ( 0 )
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#define NX_FILL_1( _ptr, _index, ... ) \
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NX_FILL ( _ptr, _index, NX_ASSEMBLE_1 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_FILL_2( _ptr, _index, ... ) \
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NX_FILL ( _ptr, _index, NX_ASSEMBLE_2 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_FILL_3( _ptr, _index, ... ) \
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NX_FILL ( _ptr, _index, NX_ASSEMBLE_3 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_FILL_4( _ptr, _index, ... ) \
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NX_FILL ( _ptr, _index, NX_ASSEMBLE_4 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_FILL_5( _ptr, _index, ... ) \
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NX_FILL ( _ptr, _index, NX_ASSEMBLE_5 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_FILL_6( _ptr, _index, ... ) \
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NX_FILL ( _ptr, _index, NX_ASSEMBLE_6 ( _ptr, _index, __VA_ARGS__ ) )
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#define NX_FILL_7( _ptr, _index, ... ) \
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NX_FILL ( _ptr, _index, NX_ASSEMBLE_7 ( _ptr, _index, __VA_ARGS__ ) )
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/** Extract value of named field */
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#define NX_GET64( _ptr, _field ) \
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( { \
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unsigned int __index = NX_QWORD_OFFSET ( _ptr, _field ); \
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uint64_t *__ptr = &(_ptr)->u.qwords[__index]; \
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uint64_t __value = le64_to_cpu ( *__ptr ); \
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__value >>= \
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NX_QWORD_BIT_OFFSET ( _ptr, __index, _field ); \
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__value &= NX_BIT_MASK ( _ptr, _field ); \
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__value; \
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} )
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/** Extract value of named field (for fields up to the size of a long) */
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#define NX_GET( _ptr, _field ) \
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( ( unsigned long ) NX_GET64 ( _ptr, _field ) )
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#endif /* _NX_BITOPS_H */
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@ -0,0 +1,499 @@
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/*
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* Data types and structure for HAL - NIC interface.
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*
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*/
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#ifndef _NXHAL_NIC_INTERFACE_H_
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#define _NXHAL_NIC_INTERFACE_H_
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/*****************************************************************************
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* Simple Types
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*****************************************************************************/
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typedef U32 nx_reg_addr_t;
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/*****************************************************************************
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* Root crb-based firmware commands
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*****************************************************************************/
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/* CRB Root Command
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A single set of crbs is used across all physical/virtual
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functions for capability queries, initialization, and
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context creation/destruction.
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There are 4 CRBS:
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Command/Response CRB
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Argument1 CRB
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Argument2 CRB
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Argument3 CRB
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Signature CRB
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The cmd/rsp crb is always intiated by the host via
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a command code and always responded by the card with
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a response code. The cmd and rsp codes are disjoint.
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The sequence of use is always CMD, RSP, CLEAR CMD.
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The arguments are for passing in command specific
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and response specific parameters/data.
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The signature is composed of a magic value, the
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pci function id, and a command sequence id:
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[7:0] = pci function
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[15:8] = version
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[31:16] = magic of 0xcafe
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The pci function allows the card to take correct
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action for the given particular commands.
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The firmware will attempt to detect
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an errant driver that has died while holding
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the root crb hardware lock. Such an error condition
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shows up as the cmd/rsp crb stuck in a non-clear state.
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Interface Sequence:
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Host always makes requests and firmware always responds.
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Note that data field is always set prior to command field.
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[READ] CMD/RSP CRB ARGUMENT FIELD
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Host grab lock
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Host -> CMD optional parameter
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FW <- (Good) RSP-OK DATA
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FW <- (Fail) RSP-FAIL optional failure code
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Host -> CLEAR
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Host release lock
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[WRITE] CMD/RSP CRB ARGUMENT FIELD
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Host grab lock
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Host -> CMD DATA
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FW <- (Good) RSP-OK optional write status
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FW <- (Write) RSP-FAIL optional failure code
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Host -> CLEAR
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Host release lock
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*/
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/*****************************************************************************
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* CMD/RSP
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*****************************************************************************/
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#define NX_CDRP_SIGNATURE_TO_PCIFN(sign) ((sign) & 0xff)
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#define NX_CDRP_SIGNATURE_TO_VERSION(sign) (((sign)>>8) & 0xff)
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#define NX_CDRP_SIGNATURE_TO_MAGIC(sign) (((sign)>>16) & 0xffff)
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#define NX_CDRP_SIGNATURE_VALID(sign) \
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( NX_CDRP_SIGNATURE_TO_MAGIC(sign) == 0xcafe && \
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NX_CDRP_SIGNATURE_TO_PCIFN(sign) < 8)
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#define NX_CDRP_SIGNATURE_MAKE(pcifn,version) \
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( ((pcifn) & 0xff) | \
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(((version) & 0xff) << 8) | \
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(0xcafe << 16) )
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#define NX_CDRP_CLEAR 0x00000000
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#define NX_CDRP_CMD_BIT 0x80000000
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/* All responses must have the NX_CDRP_CMD_BIT cleared
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* in the crb NX_CDRP_CRB_OFFSET. */
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#define NX_CDRP_FORM_RSP(rsp) (rsp)
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#define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
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#define NX_CDRP_RSP_OK 0x00000001
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#define NX_CDRP_RSP_FAIL 0x00000002
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#define NX_CDRP_RSP_TIMEOUT 0x00000003
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/* All commands must have the NX_CDRP_CMD_BIT set in
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* the crb NX_CDRP_CRB_OFFSET.
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* The macros below do not have it explicitly set to
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* allow their use in lookup tables */
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#define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
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#define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
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/* [CMD] Capability Vector [RSP] Capability Vector */
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#define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
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/* [CMD] - [RSP] Query Value */
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#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
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/* [CMD] - [RSP] Query Value */
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#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
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/* [CMD] - [RSP] Query Value */
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#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
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/* [CMD] - [RSP] Query Value */
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#define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
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/* [CMD] - [RSP] Query Value */
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#define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
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/* [CMD] Rx Config DMA Addr [RSP] rcode */
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#define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
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/* [CMD] Rx Context Handle, Reset Kind [RSP] rcode */
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#define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
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/* [CMD] Tx Config DMA Addr [RSP] rcode */
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#define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
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/* [CMD] Tx Context Handle, Reset Kind [RSP] rcode */
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#define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
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/* [CMD] Stat setup dma addr - [RSP] Handle, rcode */
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#define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
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/* [CMD] Handle - [RSP] rcode */
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#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
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/* [CMD] Handle - [RSP] rcode */
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#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
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#define NX_CDRP_CMD_MAX 0x00000011
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/*****************************************************************************
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* Capabilities
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*****************************************************************************/
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#define NX_CAP_BIT(class, bit) (1 << bit)
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/* Class 0 (i.e. ARGS 1)
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*/
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#define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
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#define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
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#define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
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#define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
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#define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
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#define NX_CAP0_LRO NX_CAP_BIT(0, 5)
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#define NX_CAP0_LSO NX_CAP_BIT(0, 6)
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/* Class 1 (i.e. ARGS 2)
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*/
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#define NX_CAP1_NIC NX_CAP_BIT(1, 0)
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#define NX_CAP1_PXE NX_CAP_BIT(1, 1)
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#define NX_CAP1_CHIMNEY NX_CAP_BIT(1, 2)
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#define NX_CAP1_LSA NX_CAP_BIT(1, 3)
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#define NX_CAP1_RDMA NX_CAP_BIT(1, 4)
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#define NX_CAP1_ISCSI NX_CAP_BIT(1, 5)
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#define NX_CAP1_FCOE NX_CAP_BIT(1, 6)
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/* Class 2 (i.e. ARGS 3)
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*/
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/*****************************************************************************
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* Rules
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*****************************************************************************/
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typedef U32 nx_rx_rule_type_t;
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#define NX_RX_RULETYPE_DEFAULT 0
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#define NX_RX_RULETYPE_MAC 1
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#define NX_RX_RULETYPE_MAC_VLAN 2
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#define NX_RX_RULETYPE_MAC_RSS 3
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#define NX_RX_RULETYPE_MAC_VLAN_RSS 4
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#define NX_RX_RULETYPE_MAX 5
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typedef U32 nx_rx_rule_cmd_t;
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#define NX_RX_RULECMD_ADD 0
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#define NX_RX_RULECMD_REMOVE 1
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#define NX_RX_RULECMD_MAX 2
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typedef struct nx_rx_rule_arg_s {
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union {
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struct {
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char mac[6];
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} m;
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struct {
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char mac[6];
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char vlan;
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} mv;
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struct {
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char mac[6];
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} mr;
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struct {
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char mac[6];
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char vlan;
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} mvr;
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};
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/* will be union of all the different args for rules */
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U64 data;
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} nx_rx_rule_arg_t;
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typedef struct nx_rx_rule_s {
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U32 id;
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||||
U32 active;
|
||||
nx_rx_rule_arg_t arg;
|
||||
nx_rx_rule_type_t type;
|
||||
} nx_rx_rule_t;
|
||||
|
||||
/* MSG - REQUIRES TX CONTEXT */
|
||||
|
||||
/* The rules can be added/deleted from both the
|
||||
* host and card sides so rq/rsp are similar.
|
||||
*/
|
||||
typedef struct nx_hostmsg_rx_rule_s {
|
||||
nx_rx_rule_cmd_t cmd;
|
||||
nx_rx_rule_t rule;
|
||||
} nx_hostmsg_rx_rule_t;
|
||||
|
||||
typedef struct nx_cardmsg_rx_rule_s {
|
||||
nx_rcode_t rcode;
|
||||
nx_rx_rule_cmd_t cmd;
|
||||
nx_rx_rule_t rule;
|
||||
} nx_cardmsg_rx_rule_t;
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Common to Rx/Tx contexts
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
* Context states
|
||||
*/
|
||||
|
||||
typedef U32 nx_host_ctx_state_t;
|
||||
|
||||
#define NX_HOST_CTX_STATE_FREED 0 /* Invalid state */
|
||||
#define NX_HOST_CTX_STATE_ALLOCATED 1 /* Not committed */
|
||||
/* The following states imply FW is aware of context */
|
||||
#define NX_HOST_CTX_STATE_ACTIVE 2
|
||||
#define NX_HOST_CTX_STATE_DISABLED 3
|
||||
#define NX_HOST_CTX_STATE_QUIESCED 4
|
||||
#define NX_HOST_CTX_STATE_MAX 5
|
||||
|
||||
/*
|
||||
* Interrupt mask crb use must be set identically on the Tx
|
||||
* and Rx context configs across a pci function
|
||||
*/
|
||||
|
||||
/* Rx and Tx have unique interrupt/crb */
|
||||
#define NX_HOST_INT_CRB_MODE_UNIQUE 0
|
||||
/* Rx and Tx share a common interrupt/crb */
|
||||
#define NX_HOST_INT_CRB_MODE_SHARED 1 /* <= LEGACY */
|
||||
/* Rx does not use a crb */
|
||||
#define NX_HOST_INT_CRB_MODE_NORX 2
|
||||
/* Tx does not use a crb */
|
||||
#define NX_HOST_INT_CRB_MODE_NOTX 3
|
||||
/* Neither Rx nor Tx use a crb */
|
||||
#define NX_HOST_INT_CRB_MODE_NORXTX 4
|
||||
|
||||
/*
|
||||
* Destroy Rx/Tx
|
||||
*/
|
||||
|
||||
#define NX_DESTROY_CTX_RESET 0
|
||||
#define NX_DESTROY_CTX_D3_RESET 1
|
||||
#define NX_DESTROY_CTX_MAX 2
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Tx
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
* Components of the host-request for Tx context creation.
|
||||
* CRB - DOES NOT REQUIRE Rx/TX CONTEXT
|
||||
*/
|
||||
|
||||
typedef struct nx_hostrq_cds_ring_s {
|
||||
U64 host_phys_addr; /* Ring base addr */
|
||||
U32 ring_size; /* Ring entries */
|
||||
U32 rsvd; /* Padding */
|
||||
} nx_hostrq_cds_ring_t;
|
||||
|
||||
typedef struct nx_hostrq_tx_ctx_s {
|
||||
U64 host_rsp_dma_addr; /* Response dma'd here */
|
||||
U64 cmd_cons_dma_addr; /* */
|
||||
U64 dummy_dma_addr; /* */
|
||||
U32 capabilities[4]; /* Flag bit vector */
|
||||
U32 host_int_crb_mode; /* Interrupt crb usage */
|
||||
U32 rsvd1; /* Padding */
|
||||
U16 rsvd2; /* Padding */
|
||||
U16 interrupt_ctl;
|
||||
U16 msi_index;
|
||||
U16 rsvd3; /* Padding */
|
||||
nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
|
||||
U8 reserved[128]; /* future expansion */
|
||||
} nx_hostrq_tx_ctx_t;
|
||||
|
||||
typedef struct nx_cardrsp_cds_ring_s {
|
||||
U32 host_producer_crb; /* Crb to use */
|
||||
U32 interrupt_crb; /* Crb to use */
|
||||
} nx_cardrsp_cds_ring_t;
|
||||
|
||||
typedef struct nx_cardrsp_tx_ctx_s {
|
||||
U32 host_ctx_state; /* Starting state */
|
||||
U16 context_id; /* Handle for context */
|
||||
U8 phys_port; /* Physical id of port */
|
||||
U8 virt_port; /* Virtual/Logical id of port */
|
||||
nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
|
||||
U8 reserved[128]; /* future expansion */
|
||||
} nx_cardrsp_tx_ctx_t;
|
||||
|
||||
#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) \
|
||||
( sizeof(HOSTRQ_TX))
|
||||
|
||||
#define SIZEOF_CARDRSP_TX(CARDRSP_TX) \
|
||||
( sizeof(CARDRSP_TX))
|
||||
|
||||
/*****************************************************************************
|
||||
* Rx
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
* RDS ring mapping to producer crbs
|
||||
*/
|
||||
|
||||
/* Each ring has a unique crb */
|
||||
#define NX_HOST_RDS_CRB_MODE_UNIQUE 0 /* <= LEGACY */
|
||||
|
||||
/* All configured RDS Rings share common crb:
|
||||
1 Ring - same as unique
|
||||
2 Rings - 16, 16
|
||||
3 Rings - 10, 10, 10 */
|
||||
#define NX_HOST_RDS_CRB_MODE_SHARED 1
|
||||
|
||||
/* Bit usage is specified per-ring using the
|
||||
ring's size. Sum of bit lengths must be <= 32.
|
||||
Packing is [Ring N] ... [Ring 1][Ring 0] */
|
||||
#define NX_HOST_RDS_CRB_MODE_CUSTOM 2
|
||||
#define NX_HOST_RDS_CRB_MODE_MAX 3
|
||||
|
||||
|
||||
/*
|
||||
* RDS Ting Types
|
||||
*/
|
||||
|
||||
#define NX_RDS_RING_TYPE_NORMAL 0
|
||||
#define NX_RDS_RING_TYPE_JUMBO 1
|
||||
#define NX_RDS_RING_TYPE_LRO 2
|
||||
#define NX_RDS_RING_TYPE_MAX 3
|
||||
|
||||
/*
|
||||
* Components of the host-request for Rx context creation.
|
||||
* CRB - DOES NOT REQUIRE Rx/TX CONTEXT
|
||||
*/
|
||||
|
||||
typedef struct nx_hostrq_sds_ring_s {
|
||||
U64 host_phys_addr; /* Ring base addr */
|
||||
U32 ring_size; /* Ring entries */
|
||||
U16 msi_index;
|
||||
U16 rsvd; /* Padding */
|
||||
} nx_hostrq_sds_ring_t;
|
||||
|
||||
typedef struct nx_hostrq_rds_ring_s {
|
||||
U64 host_phys_addr; /* Ring base addr */
|
||||
U64 buff_size; /* Packet buffer size */
|
||||
U32 ring_size; /* Ring entries */
|
||||
U32 ring_kind; /* Class of ring */
|
||||
} nx_hostrq_rds_ring_t;
|
||||
|
||||
typedef struct nx_hostrq_rx_ctx_s {
|
||||
U64 host_rsp_dma_addr; /* Response dma'd here */
|
||||
U32 capabilities[4]; /* Flag bit vector */
|
||||
U32 host_int_crb_mode; /* Interrupt crb usage */
|
||||
U32 host_rds_crb_mode; /* RDS crb usage */
|
||||
/* These ring offsets are relative to data[0] below */
|
||||
U32 rds_ring_offset; /* Offset to RDS config */
|
||||
U32 sds_ring_offset; /* Offset to SDS config */
|
||||
U16 num_rds_rings; /* Count of RDS rings */
|
||||
U16 num_sds_rings; /* Count of SDS rings */
|
||||
U16 rsvd1; /* Padding */
|
||||
U16 rsvd2; /* Padding */
|
||||
U8 reserved[128]; /* reserve space for future expansion*/
|
||||
/* MUST BE 64-bit aligned.
|
||||
The following is packed:
|
||||
- N hostrq_rds_rings
|
||||
- N hostrq_sds_rings */
|
||||
char data[0];
|
||||
} nx_hostrq_rx_ctx_t;
|
||||
|
||||
typedef struct nx_cardrsp_rds_ring_s {
|
||||
U32 host_producer_crb; /* Crb to use */
|
||||
U32 rsvd1; /* Padding */
|
||||
} nx_cardrsp_rds_ring_t;
|
||||
|
||||
typedef struct nx_cardrsp_sds_ring_s {
|
||||
U32 host_consumer_crb; /* Crb to use */
|
||||
U32 interrupt_crb; /* Crb to use */
|
||||
} nx_cardrsp_sds_ring_t;
|
||||
|
||||
typedef struct nx_cardrsp_rx_ctx_s {
|
||||
/* These ring offsets are relative to data[0] below */
|
||||
U32 rds_ring_offset; /* Offset to RDS config */
|
||||
U32 sds_ring_offset; /* Offset to SDS config */
|
||||
U32 host_ctx_state; /* Starting State */
|
||||
U32 num_fn_per_port; /* How many PCI fn share the port */
|
||||
U16 num_rds_rings; /* Count of RDS rings */
|
||||
U16 num_sds_rings; /* Count of SDS rings */
|
||||
U16 context_id; /* Handle for context */
|
||||
U8 phys_port; /* Physical id of port */
|
||||
U8 virt_port; /* Virtual/Logical id of port */
|
||||
U8 reserved[128]; /* save space for future expansion */
|
||||
/* MUST BE 64-bit aligned.
|
||||
The following is packed:
|
||||
- N cardrsp_rds_rings
|
||||
- N cardrs_sds_rings */
|
||||
char data[0];
|
||||
} nx_cardrsp_rx_ctx_t;
|
||||
|
||||
#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
|
||||
( sizeof(HOSTRQ_RX) + \
|
||||
(rds_rings)*(sizeof (nx_hostrq_rds_ring_t)) + \
|
||||
(sds_rings)*(sizeof (nx_hostrq_sds_ring_t)) )
|
||||
|
||||
#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
|
||||
( sizeof(CARDRSP_RX) + \
|
||||
(rds_rings)*(sizeof (nx_cardrsp_rds_ring_t)) + \
|
||||
(sds_rings)*(sizeof (nx_cardrsp_sds_ring_t)) )
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Statistics
|
||||
*****************************************************************************/
|
||||
|
||||
/*
|
||||
* The model of statistics update to use
|
||||
*/
|
||||
|
||||
#define NX_STATISTICS_MODE_INVALID 0
|
||||
|
||||
/* Permanent setup; Updates are only sent on explicit request
|
||||
(NX_CDRP_CMD_GET_STATISTICS) */
|
||||
#define NX_STATISTICS_MODE_PULL 1
|
||||
|
||||
/* Permanent setup; Updates are sent automatically and on
|
||||
explicit request (NX_CDRP_CMD_GET_STATISTICS) */
|
||||
#define NX_STATISTICS_MODE_PUSH 2
|
||||
|
||||
/* One time stat update. */
|
||||
#define NX_STATISTICS_MODE_SINGLE_SHOT 3
|
||||
|
||||
#define NX_STATISTICS_MODE_MAX 4
|
||||
|
||||
/*
|
||||
* What set of stats
|
||||
*/
|
||||
#define NX_STATISTICS_TYPE_INVALID 0
|
||||
#define NX_STATISTICS_TYPE_NIC_RX_CORE 1
|
||||
#define NX_STATISTICS_TYPE_NIC_TX_CORE 2
|
||||
#define NX_STATISTICS_TYPE_NIC_RX_ALL 3
|
||||
#define NX_STATISTICS_TYPE_NIC_TX_ALL 4
|
||||
#define NX_STATISTICS_TYPE_MAX 5
|
||||
|
||||
|
||||
/*
|
||||
* Request to setup statistics gathering.
|
||||
* CRB - DOES NOT REQUIRE Rx/TX CONTEXT
|
||||
*/
|
||||
|
||||
typedef struct nx_hostrq_stat_setup_s {
|
||||
U64 host_stat_buffer; /* Where to dma stats */
|
||||
U32 host_stat_size; /* Size of stat buffer */
|
||||
U16 context_id; /* Which context */
|
||||
U16 stat_type; /* What class of stats */
|
||||
U16 stat_mode; /* When to update */
|
||||
U16 stat_interval; /* Frequency of update */
|
||||
} nx_hostrq_stat_setup_t;
|
||||
|
||||
|
||||
|
||||
#endif /* _NXHAL_NIC_INTERFACE_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,252 @@
|
|||
#ifndef _PHANTOM_H
|
||||
#define _PHANTOM_H
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* NetXen Phantom NICs
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Drag in hardware definitions */
|
||||
#include "nx_bitops.h"
|
||||
#include "phantom_hw.h"
|
||||
struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
|
||||
struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
|
||||
union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
|
||||
|
||||
/* Drag in firmware interface definitions */
|
||||
typedef uint8_t U8;
|
||||
typedef uint16_t U16;
|
||||
typedef uint32_t U32;
|
||||
typedef uint64_t U64;
|
||||
typedef uint32_t nx_rcode_t;
|
||||
#define NXHAL_VERSION 1
|
||||
#include "nxhal_nic_interface.h"
|
||||
|
||||
/** SPI controller maximum block size */
|
||||
#define UNM_SPI_BLKSIZE 4
|
||||
|
||||
/** DMA buffer alignment */
|
||||
#define UNM_DMA_BUFFER_ALIGN 16
|
||||
|
||||
/** Mark structure as DMA-aligned */
|
||||
#define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
|
||||
|
||||
/** Dummy DMA buffer size */
|
||||
#define UNM_DUMMY_DMA_SIZE 1024
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Register definitions
|
||||
*
|
||||
*/
|
||||
|
||||
#define UNM_128M_CRB_WINDOW 0x6110210UL
|
||||
#define UNM_32M_CRB_WINDOW 0x0110210UL
|
||||
#define UNM_2M_CRB_WINDOW 0x0130060UL
|
||||
|
||||
/**
|
||||
* Phantom register blocks
|
||||
*
|
||||
* The upper address bits vary between cards. We define an abstract
|
||||
* address space in which the upper 8 bits of the 32-bit register
|
||||
* address encode the register block. This gets translated to a bus
|
||||
* address by the phantom_crb_access_xxx() methods.
|
||||
*/
|
||||
enum unm_reg_blocks {
|
||||
UNM_CRB_BLK_PCIE,
|
||||
UNM_CRB_BLK_CAM,
|
||||
UNM_CRB_BLK_ROMUSB,
|
||||
UNM_CRB_BLK_TEST,
|
||||
};
|
||||
#define UNM_CRB_BASE(blk) ( (blk) << 24 )
|
||||
#define UNM_CRB_BLK(reg) ( (reg) >> 24 )
|
||||
#define UNM_CRB_OFFSET(reg) ( (reg) & 0x00ffffff )
|
||||
|
||||
#define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
|
||||
#define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 )
|
||||
#define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 )
|
||||
|
||||
#define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
|
||||
|
||||
#define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 )
|
||||
#define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 )
|
||||
#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4
|
||||
#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5
|
||||
#define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
|
||||
#define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
|
||||
#define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
|
||||
#define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
|
||||
#define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL
|
||||
#define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5
|
||||
#define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 )
|
||||
#define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 )
|
||||
#define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc )
|
||||
#define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL
|
||||
|
||||
#define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 )
|
||||
#define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 )
|
||||
#define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c )
|
||||
#define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 )
|
||||
#define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 )
|
||||
#define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 )
|
||||
#define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c )
|
||||
#define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 )
|
||||
#define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 )
|
||||
#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01
|
||||
#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
|
||||
#define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc )
|
||||
#define UNM_NIC_REG_DUMMY_BUF_INIT 0
|
||||
#define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 )
|
||||
#define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
|
||||
( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
|
||||
#define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01
|
||||
#define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02
|
||||
#define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c )
|
||||
#define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01
|
||||
#define UNM_NIC_REG_SW_INT_MASK_0 ( UNM_NIC_REG + 0x001d8 )
|
||||
#define UNM_NIC_REG_SW_INT_MASK_1 ( UNM_NIC_REG + 0x001e0 )
|
||||
#define UNM_NIC_REG_SW_INT_MASK_2 ( UNM_NIC_REG + 0x001e4 )
|
||||
#define UNM_NIC_REG_SW_INT_MASK_3 ( UNM_NIC_REG + 0x001e8 )
|
||||
|
||||
#define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
|
||||
|
||||
#define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 )
|
||||
#define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 )
|
||||
#define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 )
|
||||
#define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
|
||||
#define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
|
||||
#define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
|
||||
|
||||
#define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
|
||||
#define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
|
||||
#define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 )
|
||||
#define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c )
|
||||
#define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 )
|
||||
#define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 )
|
||||
#define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 )
|
||||
|
||||
#define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
|
||||
|
||||
#define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 )
|
||||
#define UNM_TEST_CONTROL_START 0x01
|
||||
#define UNM_TEST_CONTROL_ENABLE 0x02
|
||||
#define UNM_TEST_CONTROL_BUSY 0x08
|
||||
#define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 )
|
||||
#define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 )
|
||||
#define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 )
|
||||
#define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac )
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Flash layout
|
||||
*
|
||||
*/
|
||||
|
||||
/* Board configuration */
|
||||
|
||||
#define UNM_BRDCFG_START 0x4000
|
||||
|
||||
struct unm_board_info {
|
||||
uint32_t header_version;
|
||||
uint32_t board_mfg;
|
||||
uint32_t board_type;
|
||||
uint32_t board_num;
|
||||
uint32_t chip_id;
|
||||
uint32_t chip_minor;
|
||||
uint32_t chip_major;
|
||||
uint32_t chip_pkg;
|
||||
uint32_t chip_lot;
|
||||
uint32_t port_mask;
|
||||
uint32_t peg_mask;
|
||||
uint32_t icache_ok;
|
||||
uint32_t dcache_ok;
|
||||
uint32_t casper_ok;
|
||||
uint32_t mac_addr_lo_0;
|
||||
uint32_t mac_addr_lo_1;
|
||||
uint32_t mac_addr_lo_2;
|
||||
uint32_t mac_addr_lo_3;
|
||||
uint32_t mn_sync_mode;
|
||||
uint32_t mn_sync_shift_cclk;
|
||||
uint32_t mn_sync_shift_mclk;
|
||||
uint32_t mn_wb_en;
|
||||
uint32_t mn_crystal_freq;
|
||||
uint32_t mn_speed;
|
||||
uint32_t mn_org;
|
||||
uint32_t mn_depth;
|
||||
uint32_t mn_ranks_0;
|
||||
uint32_t mn_ranks_1;
|
||||
uint32_t mn_rd_latency_0;
|
||||
uint32_t mn_rd_latency_1;
|
||||
uint32_t mn_rd_latency_2;
|
||||
uint32_t mn_rd_latency_3;
|
||||
uint32_t mn_rd_latency_4;
|
||||
uint32_t mn_rd_latency_5;
|
||||
uint32_t mn_rd_latency_6;
|
||||
uint32_t mn_rd_latency_7;
|
||||
uint32_t mn_rd_latency_8;
|
||||
uint32_t mn_dll_val[18];
|
||||
uint32_t mn_mode_reg;
|
||||
uint32_t mn_ext_mode_reg;
|
||||
uint32_t mn_timing_0;
|
||||
uint32_t mn_timing_1;
|
||||
uint32_t mn_timing_2;
|
||||
uint32_t sn_sync_mode;
|
||||
uint32_t sn_pt_mode;
|
||||
uint32_t sn_ecc_en;
|
||||
uint32_t sn_wb_en;
|
||||
uint32_t sn_crystal_freq;
|
||||
uint32_t sn_speed;
|
||||
uint32_t sn_org;
|
||||
uint32_t sn_depth;
|
||||
uint32_t sn_dll_tap;
|
||||
uint32_t sn_rd_latency;
|
||||
uint32_t mac_addr_hi_0;
|
||||
uint32_t mac_addr_hi_1;
|
||||
uint32_t mac_addr_hi_2;
|
||||
uint32_t mac_addr_hi_3;
|
||||
uint32_t magic;
|
||||
uint32_t mn_rdimm;
|
||||
uint32_t mn_dll_override;
|
||||
};
|
||||
|
||||
#define UNM_BDINFO_VERSION 1
|
||||
#define UNM_BRDTYPE_P3_HMEZ 0x0022
|
||||
#define UNM_BRDTYPE_P3_10G_CX4_LP 0x0023
|
||||
#define UNM_BRDTYPE_P3_4_GB 0x0024
|
||||
#define UNM_BRDTYPE_P3_IMEZ 0x0025
|
||||
#define UNM_BRDTYPE_P3_10G_SFP_PLUS 0x0026
|
||||
#define UNM_BRDTYPE_P3_10000_BASE_T 0x0027
|
||||
#define UNM_BRDTYPE_P3_XG_LOM 0x0028
|
||||
#define UNM_BRDTYPE_P3_10G_CX4 0x0031
|
||||
#define UNM_BRDTYPE_P3_10G_XFP 0x0032
|
||||
#define UNM_BDINFO_MAGIC 0x12345678
|
||||
|
||||
/* User defined region */
|
||||
|
||||
#define UNM_USER_START 0x3e8000
|
||||
|
||||
#define UNM_FLASH_NUM_PORTS 4
|
||||
#define UNM_FLASH_NUM_MAC_PER_PORT 32
|
||||
|
||||
struct unm_user_info {
|
||||
uint8_t flash_md5[16 * 64];
|
||||
uint32_t bootld_version;
|
||||
uint32_t bootld_size;
|
||||
uint32_t image_version;
|
||||
uint32_t image_size;
|
||||
uint32_t primary_status;
|
||||
uint32_t secondary_present;
|
||||
/* MAC address , 4 ports, 32 address per port */
|
||||
uint64_t mac_addr[UNM_FLASH_NUM_PORTS * UNM_FLASH_NUM_MAC_PER_PORT];
|
||||
uint32_t sub_sys_id;
|
||||
uint8_t serial_num[32];
|
||||
uint32_t bios_version;
|
||||
uint32_t pxe_enable;
|
||||
uint32_t vlan_tag[UNM_FLASH_NUM_PORTS];
|
||||
};
|
||||
|
||||
#endif /* _PHANTOM_H */
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
#ifndef _PHANTOM_HW_H
|
||||
#define _PHANTOM_HW_H
|
||||
|
||||
/*
|
||||
* Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Phantom hardware definitions
|
||||
*
|
||||
*/
|
||||
|
||||
/** A Phantom RX descriptor */
|
||||
struct phantom_rds_pb {
|
||||
pseudo_bit_t handle[16]; /**< Reference handle */
|
||||
pseudo_bit_t flags[16]; /**< Flags */
|
||||
pseudo_bit_t length[32]; /**< Buffer length */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t dma_addr[64]; /**< Buffer DMA address */
|
||||
|
||||
};
|
||||
|
||||
/** A Phantom RX status descriptor */
|
||||
struct phantom_sds_pb {
|
||||
pseudo_bit_t port[4]; /**< Port number */
|
||||
pseudo_bit_t status[4]; /**< Checksum status */
|
||||
pseudo_bit_t type[4]; /**< Type */
|
||||
pseudo_bit_t total_length[16]; /**< Total packet length */
|
||||
pseudo_bit_t handle[16]; /**< Reference handle */
|
||||
pseudo_bit_t protocol[4]; /**< Protocol */
|
||||
pseudo_bit_t pkt_offset[5]; /**< Offset to packet start */
|
||||
pseudo_bit_t desc_cnt[3]; /**< Descriptor count */
|
||||
pseudo_bit_t owner[2]; /**< Owner */
|
||||
pseudo_bit_t opcode[6]; /**< Opcode */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t hash_value[32]; /**< RSS hash value */
|
||||
pseudo_bit_t hash_type[8]; /**< RSS hash type */
|
||||
pseudo_bit_t lro[8]; /**< LRO data */
|
||||
};
|
||||
|
||||
/** Phantom RX status opcodes */
|
||||
enum phantom_sds_opcode {
|
||||
UNM_SYN_OFFLOAD = 0x03,
|
||||
UNM_RXPKT_DESC = 0x04,
|
||||
};
|
||||
|
||||
/** A Phantom TX descriptor */
|
||||
struct phantom_tx_cds_pb {
|
||||
pseudo_bit_t tcp_hdr_offset[8]; /**< TCP header offset (LSO) */
|
||||
pseudo_bit_t ip_hdr_offset[8]; /**< IP header offset (LSO) */
|
||||
pseudo_bit_t flags[7]; /**< Flags */
|
||||
pseudo_bit_t opcode[6]; /**< Opcode */
|
||||
pseudo_bit_t hw_rsvd_0[3]; /**< (Reserved) */
|
||||
pseudo_bit_t num_buffers[8]; /**< Total number of buffers */
|
||||
pseudo_bit_t length[24]; /**< Total length */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t buffer2_dma_addr[64]; /**< Buffer 2 DMA address */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t handle[16]; /**< Reference handle (n/a) */
|
||||
pseudo_bit_t port_mss[16]; /**< TCP MSS (LSO) */
|
||||
pseudo_bit_t port[4]; /**< Port */
|
||||
pseudo_bit_t context_id[4]; /**< Context ID */
|
||||
pseudo_bit_t total_hdr_length[8]; /**< MAC+IP+TCP header (LSO) */
|
||||
pseudo_bit_t conn_id[16]; /**< IPSec connection ID */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t buffer3_dma_addr[64]; /**< Buffer 3 DMA address */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t buffer1_dma_addr[64]; /**< Buffer 1 DMA address */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t buffer1_length[16]; /**< Buffer 1 length */
|
||||
pseudo_bit_t buffer2_length[16]; /**< Buffer 2 length */
|
||||
pseudo_bit_t buffer3_length[16]; /**< Buffer 3 length */
|
||||
pseudo_bit_t buffer4_length[16]; /**< Buffer 4 length */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t buffer4_dma_addr[64]; /**< Buffer 4 DMA address */
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
pseudo_bit_t hw_rsvd_1[64]; /**< (Reserved) */
|
||||
};
|
||||
|
||||
/** A Phantom MAC address request body */
|
||||
struct phantom_nic_request_body_mac_request_pb {
|
||||
pseudo_bit_t opcode[8]; /**< Opcode */
|
||||
pseudo_bit_t tag[8]; /**< Tag */
|
||||
pseudo_bit_t mac_addr_0[8]; /**< MAC address byte 0 */
|
||||
pseudo_bit_t mac_addr_1[8]; /**< MAC address byte 1 */
|
||||
pseudo_bit_t mac_addr_2[8]; /**< MAC address byte 2 */
|
||||
pseudo_bit_t mac_addr_3[8]; /**< MAC address byte 3 */
|
||||
pseudo_bit_t mac_addr_4[8]; /**< MAC address byte 4 */
|
||||
pseudo_bit_t mac_addr_5[8]; /**< MAC address byte 5 */
|
||||
};
|
||||
|
||||
/** Phantom MAC request opcodes */
|
||||
enum phantom_mac_request_opcode {
|
||||
UNM_MAC_ADD = 0x01, /**< Add MAC address */
|
||||
UNM_MAC_DEL = 0x02, /**< Delete MAC address */
|
||||
};
|
||||
|
||||
/** A Phantom NIC request command descriptor */
|
||||
struct phantom_nic_request_cds_pb {
|
||||
struct {
|
||||
pseudo_bit_t dst_minor[18];
|
||||
pseudo_bit_t dst_subq[1];
|
||||
pseudo_bit_t dst_major[4];
|
||||
pseudo_bit_t opcode[6];
|
||||
pseudo_bit_t hw_rsvd_0[3];
|
||||
pseudo_bit_t msginfo[24];
|
||||
pseudo_bit_t hw_rsvd_1[2];
|
||||
pseudo_bit_t qmsg_type[6];
|
||||
} common;
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
struct {
|
||||
pseudo_bit_t opcode[8];
|
||||
pseudo_bit_t comp_id [8];
|
||||
pseudo_bit_t context_id[16];
|
||||
pseudo_bit_t need_completion[1];
|
||||
pseudo_bit_t hw_rsvd_0[23];
|
||||
pseudo_bit_t sub_opcode[8];
|
||||
} header;
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
union {
|
||||
struct phantom_nic_request_body_mac_request_pb mac_request;
|
||||
pseudo_bit_t padding[384];
|
||||
} body;
|
||||
};
|
||||
|
||||
/** Phantom NIC request opcodes */
|
||||
enum phantom_nic_request_opcode {
|
||||
UNM_MAC_EVENT = 0x01, /**< Add/delete MAC address */
|
||||
};
|
||||
|
||||
/** A Phantom command descriptor */
|
||||
union phantom_cds_pb {
|
||||
struct phantom_tx_cds_pb tx;
|
||||
struct phantom_nic_request_cds_pb nic_request;
|
||||
};
|
||||
|
||||
/** Phantom command descriptor opcodes */
|
||||
enum phantom_cds_opcode {
|
||||
UNM_TX_ETHER_PKT = 0x01, /**< Transmit raw Ethernet */
|
||||
UNM_NIC_REQUEST = 0x14, /**< NIC request */
|
||||
};
|
||||
|
||||
#endif /* _PHANTOM_HW_H */
|
||||
|
|
@ -105,6 +105,7 @@
|
|||
#define ERRFILE_e1000 ( ERRFILE_DRIVER | 0x00480000 )
|
||||
#define ERRFILE_e1000_hw ( ERRFILE_DRIVER | 0x00490000 )
|
||||
#define ERRFILE_mtnic ( ERRFILE_DRIVER | 0x004a0000 )
|
||||
#define ERRFILE_phantom ( ERRFILE_DRIVER | 0x004b0000 )
|
||||
|
||||
#define ERRFILE_scsi ( ERRFILE_DRIVER | 0x00700000 )
|
||||
#define ERRFILE_arbel ( ERRFILE_DRIVER | 0x00710000 )
|
||||
|
|
|
|||
Reference in New Issue