david/ipxe
Archived
1
0

[intel] Avoid completely filling the TX descriptor ring

It is unclear from the datasheets whether or not the TX ring can be
completely filled (i.e. whether writing the tail value as equal to the
current head value will cause the ring to be treated as completely
full or completely empty).  It is very plausible that this edge case
could differ in behaviour between real hardware and the many
implementations of an emulated Intel NIC found in various virtual
machines.  Err on the side of caution and always leave at least one
ring entry empty.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown 2014-04-22 13:12:54 +01:00
parent 93acb5d8d0
commit 27884298a3
2 changed files with 4 additions and 1 deletions

View File

@ -593,7 +593,7 @@ int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
physaddr_t address; physaddr_t address;
/* Get next transmit descriptor */ /* Get next transmit descriptor */
if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_NUM_TX_DESC ) { if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel ); DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
return -ENOBUFS; return -ENOBUFS;
} }

View File

@ -156,6 +156,9 @@ enum intel_descriptor_status {
*/ */
#define INTEL_NUM_TX_DESC 16 #define INTEL_NUM_TX_DESC 16
/** Transmit descriptor ring maximum fill level */
#define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
/** Receive/Transmit Descriptor Base Address Low (offset) */ /** Receive/Transmit Descriptor Base Address Low (offset) */
#define INTEL_xDBAL 0x00 #define INTEL_xDBAL 0x00