[e1000] Add 82576 support
Add the 82576 to the e1000 driver. - Examining the Linux 2.6.30-rc4 igb driver, which supports this card and; - Information available in the Intel® 82576 Gigabit Ethernet Controller Datasheet v2.1, which is available from Intel's web site. I only have a dual-ported card with Copper PHY, so any code paths relating to Fibre haven't been tested. Also, I have only tested using auto-negotiation of speed and duplex, and no flow control. Other code paths relating to those settings also have not been exercised. Signed-off-by: Simon Horman <horms@verge.net.au> Sponsored-by: Thomas Miletich <thomas.miletich@gmail.com> Modified-by: Thomas Miletich <thomas.miletich@gmail.com> Modified-by: Marty Connor <mdc@etherboot.org> Signed-off-by: Marty Connor <mdc@etherboot.org>
This commit is contained in:
Simon Horman
Marty Connor
parent
db3e054fe5
commit
04cb1cde5c
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@ -73,6 +73,7 @@ e1000_get_hw_control ( struct e1000_adapter *adapter )
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break;
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case e1000_82571:
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case e1000_82572:
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case e1000_82576:
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case e1000_80003es2lan:
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case e1000_ich8lan:
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ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
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@ -253,6 +254,7 @@ e1000_configure_tx ( struct e1000_adapter *adapter )
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{
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struct e1000_hw *hw = &adapter->hw;
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uint32_t tctl;
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uint32_t txdctl;
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DBG ( "e1000_configure_tx\n" );
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@ -271,6 +273,12 @@ e1000_configure_tx ( struct e1000_adapter *adapter )
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adapter->tx_tail = 0;
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adapter->tx_fill_ctr = 0;
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if (hw->mac_type == e1000_82576) {
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txdctl = E1000_READ_REG ( hw, TXDCTL );
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txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
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E1000_WRITE_REG ( hw, TXDCTL, txdctl );
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}
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/* Setup Transmit Descriptor Settings for eop descriptor */
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tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
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(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
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@ -359,13 +367,15 @@ static void
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e1000_configure_rx ( struct e1000_adapter *adapter )
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{
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struct e1000_hw *hw = &adapter->hw;
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uint32_t rctl;
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uint32_t rctl, rxdctl, mrqc, rxcsum;
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DBG ( "e1000_configure_rx\n" );
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/* disable receives while setting up the descriptors */
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rctl = E1000_READ_REG ( hw, RCTL );
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E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
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E1000_WRITE_FLUSH ( hw );
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mdelay(10);
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adapter->rx_curr = 0;
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@ -377,16 +387,57 @@ e1000_configure_rx ( struct e1000_adapter *adapter )
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E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );
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E1000_WRITE_REG ( hw, RDH, 0 );
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E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
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/* Enable Receives */
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rctl = ( E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
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E1000_RCTL_MPE
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);
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if (hw->mac_type == e1000_82576)
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E1000_WRITE_REG ( hw, RDT, 0 );
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else
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E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
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/* This doesn't seem to be necessary for correct operation,
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* but it seems as well to be implicit
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*/
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if (hw->mac_type == e1000_82576) {
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rxdctl = E1000_READ_REG ( hw, RXDCTL );
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rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
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rxdctl &= 0xFFF00000;
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rxdctl |= IGB_RX_PTHRESH;
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rxdctl |= IGB_RX_HTHRESH << 8;
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rxdctl |= IGB_RX_WTHRESH << 16;
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E1000_WRITE_REG ( hw, RXDCTL, rxdctl );
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E1000_WRITE_FLUSH ( hw );
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rxcsum = E1000_READ_REG(hw, RXCSUM);
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rxcsum &= ~( E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE );
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E1000_WRITE_REG ( hw, RXCSUM, 0 );
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/* The initial value for MRQC disables multiple receive
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* queues, however this setting is not recommended.
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* - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
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* Section 8.10.9 Multiple Queues Command Register - MRQC
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*/
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mrqc = E1000_MRQC_ENABLE_VMDQ;
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E1000_WRITE_REG ( hw, MRQC, mrqc );
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}
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/* Enable Receives */
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rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
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E1000_RCTL_MPE;
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E1000_WRITE_REG ( hw, RCTL, rctl );
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E1000_WRITE_FLUSH ( hw );
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/* On the 82576, RDT([0]) must not be "bumped" before
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* the enable bit of RXDCTL([0]) is set.
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* - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
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* Section 4.5.9 receive Initialization
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*
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* By observation I have found to occur when the enable bit of
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* RCTL is set. The datasheet recommends polling for this bit,
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* however as I see no evidence of this in the Linux igb driver
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* I have omitted that step.
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* - Simon Horman, May 2009
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*/
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if (hw->mac_type == e1000_82576)
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E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
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DBG ( "RDBAL: %#08x\n", E1000_READ_REG ( hw, RDBAL ) );
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DBG ( "RDLEN: %d\n", E1000_READ_REG ( hw, RDLEN ) );
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DBG ( "RCTL: %#08x\n", E1000_READ_REG ( hw, RCTL ) );
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@ -433,6 +484,9 @@ e1000_reset ( struct e1000_adapter *adapter )
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case e1000_82573:
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pba = E1000_PBA_20K;
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break;
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case e1000_82576:
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pba = E1000_PBA_64K;
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break;
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case e1000_ich8lan:
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pba = E1000_PBA_8K;
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case e1000_undefined:
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@ -446,6 +500,7 @@ e1000_reset ( struct e1000_adapter *adapter )
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/* Set the FC high water mark to 90% of the FIFO size.
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* Required to clear last 3 LSB */
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fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
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/* We can't use 90% on small FIFOs because the remainder
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* would be less than 1 full frame. In this case, we size
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* it to allow at least a full frame above the high water
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@ -453,9 +508,20 @@ e1000_reset ( struct e1000_adapter *adapter )
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if (pba < E1000_PBA_16K)
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fc_high_water_mark = (pba * 1024) - 1600;
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adapter->hw.fc_high_water = fc_high_water_mark;
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adapter->hw.fc_low_water = fc_high_water_mark - 8;
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if (adapter->hw.mac_type == e1000_80003es2lan)
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/* This actually applies to < e1000_82575, one revision less than
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* e1000_82576, but e1000_82575 isn't currently defined in the code */
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if (adapter->hw.mac_type < e1000_82576) {
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/* 8-byte granularity */
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adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF8;
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adapter->hw.fc_low_water = adapter->hw.fc_high_water - 8;
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} else {
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/* 16-byte granularity */
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adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF0;
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adapter->hw.fc_low_water = adapter->hw.fc_high_water - 16;
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}
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if (adapter->hw.mac_type == e1000_80003es2lan ||
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adapter->hw.mac_type == e1000_82576)
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adapter->hw.fc_pause_time = 0xFFFF;
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else
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adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
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@ -1102,6 +1168,7 @@ static struct pci_device_id e1000_nics[] = {
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PCI_ROM(0x8086, 0x10bc, "e1000-0x10bc", "e1000-0x10bc", 0),
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PCI_ROM(0x8086, 0x10c4, "e1000-0x10c4", "e1000-0x10c4", 0),
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PCI_ROM(0x8086, 0x10c5, "e1000-0x10c5", "e1000-0x10c5", 0),
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PCI_ROM(0x8086, 0x10c9, "e1000-0x10c9", "e1000-0x10c9", 0),
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PCI_ROM(0x8086, 0x10d9, "e1000-0x10d9", "e1000-0x10d9", 0),
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PCI_ROM(0x8086, 0x10da, "e1000-0x10da", "e1000-0x10da", 0),
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};
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@ -419,6 +419,9 @@ e1000_set_mac_type(struct e1000_hw *hw)
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case E1000_DEV_ID_ICH8_IGP_M:
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hw->mac_type = e1000_ich8lan;
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break;
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case E1000_DEV_ID_82576:
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hw->mac_type = e1000_82576;
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break;
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default:
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/* Should never have loaded on this device */
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return -E1000_ERR_MAC_TYPE;
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@ -426,6 +429,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
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switch (hw->mac_type) {
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case e1000_ich8lan:
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case e1000_82576:
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hw->swfwhw_semaphore_present = TRUE;
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hw->asf_firmware_present = TRUE;
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break;
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@ -504,6 +508,7 @@ e1000_set_media_type(struct e1000_hw *hw)
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break;
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case e1000_ich8lan:
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case e1000_82573:
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case e1000_82576:
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/* The STATUS_TBIMODE bit is reserved or reused for the this
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* device.
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*/
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@ -750,7 +755,8 @@ e1000_reset_hw(struct e1000_hw *hw)
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static void
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e1000_initialize_hardware_bits(struct e1000_hw *hw)
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{
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if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
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if ((hw->mac_type >= e1000_82571 && hw->mac_type < e1000_82576) &&
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(!hw->initialize_hw_bits_disable)) {
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/* Settings common to all PCI-express silicon */
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uint32_t reg_ctrl, reg_ctrl_ext;
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uint32_t reg_tarc0, reg_tarc1;
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@ -907,11 +913,27 @@ e1000_init_hw(struct e1000_hw *hw)
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/* Disabling VLAN filtering. */
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DEBUGOUT("Initializing the IEEE VLAN\n");
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/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
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if (hw->mac_type != e1000_ich8lan) {
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switch (hw->mac_type) {
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case e1000_ich8lan:
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/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
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break;
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case e1000_82576:
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/* There is no need to clear vfta on 82576 if VLANs are not used.
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* - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
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* Section 8.10.19 Table Array - VFTA
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*
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* Setting VET may also be unnecessary, however the documentation
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* isn't specific on this point. The value used here is as advised in
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* - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
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* Section 8.2.7 VLAN Ether Type - VET
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*/
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E1000_WRITE_REG(hw, VET, ETHERNET_IEEE_VLAN_TYPE);
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break;
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default:
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if (hw->mac_type < e1000_82545_rev_3)
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E1000_WRITE_REG(hw, VET, 0);
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e1000_clear_vfta(hw);
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break;
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}
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/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
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@ -1477,9 +1499,13 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
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return ret_val;
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}
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/* Wait 15ms for MAC to configure PHY from eeprom settings */
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msleep(15);
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if (hw->mac_type != e1000_ich8lan) {
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/*
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* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
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* timeout issues when LFS is enabled.
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*/
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msleep(100);
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if (hw->mac_type != e1000_ich8lan && hw->mac_type != e1000_82576) {
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/* Configure activity LED after PHY reset */
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led_ctrl = E1000_READ_REG(hw, LEDCTL);
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led_ctrl &= IGP_ACTIVITY_LED_MASK;
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@ -3493,7 +3519,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
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DEBUGFUNC("e1000_read_phy_reg");
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if ((hw->mac_type == e1000_80003es2lan) &&
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if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
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(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
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swfw = E1000_SWFW_PHY1_SM;
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} else {
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@ -3631,7 +3657,7 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
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DEBUGFUNC("e1000_write_phy_reg");
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if ((hw->mac_type == e1000_80003es2lan) &&
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if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
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(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
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swfw = E1000_SWFW_PHY1_SM;
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} else {
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@ -3751,7 +3777,7 @@ e1000_read_kmrn_reg(struct e1000_hw *hw,
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uint16_t swfw;
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DEBUGFUNC("e1000_read_kmrn_reg");
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if ((hw->mac_type == e1000_80003es2lan) &&
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if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
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(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
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swfw = E1000_SWFW_PHY1_SM;
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} else {
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@ -3784,7 +3810,7 @@ e1000_write_kmrn_reg(struct e1000_hw *hw,
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uint16_t swfw;
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DEBUGFUNC("e1000_write_kmrn_reg");
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if ((hw->mac_type == e1000_80003es2lan) &&
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if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
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(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
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swfw = E1000_SWFW_PHY1_SM;
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} else {
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@ -3826,7 +3852,8 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
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DEBUGOUT("Resetting Phy...\n");
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if (hw->mac_type > e1000_82543) {
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if ((hw->mac_type == e1000_80003es2lan) &&
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if ((hw->mac_type == e1000_80003es2lan ||
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hw->mac_type == e1000_82576) &&
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(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
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swfw = E1000_SWFW_PHY1_SM;
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} else {
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@ -4136,6 +4163,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
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if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
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if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
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break;
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case e1000_82576:
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match = TRUE;
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break;
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default:
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DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
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return -E1000_ERR_CONFIG;
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@ -4607,6 +4637,38 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
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hw->flash_bank_size /= 2 * sizeof(uint16_t);
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break;
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}
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case e1000_82576:
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{
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uint16_t size;
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eeprom->type = e1000_eeprom_spi;
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eeprom->opcode_bits = 8;
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eeprom->delay_usec = 1;
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if (eecd & E1000_EECD_ADDR_BITS) {
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eeprom->page_size = 32;
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eeprom->address_bits = 16;
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} else {
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eeprom->page_size = 8;
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eeprom->address_bits = 8;
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}
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eeprom->use_eerd = TRUE;
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eeprom->use_eewr = FALSE;
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size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
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E1000_EECD_SIZE_EX_SHIFT);
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/*
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* Added to a constant, "size" becomes the left-shift value
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* for setting word_size.
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*/
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size += EEPROM_WORD_SIZE_SHIFT;
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/* EEPROM access above 16k is unsupported */
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if (size > 14)
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size = 14;
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eeprom->word_size = 1 << size;
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break;
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}
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default:
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@ -5014,8 +5076,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
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* directly. In this case, we need to acquire the EEPROM so that
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* FW or other port software does not interrupt.
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*/
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if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
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hw->eeprom.use_eerd == FALSE) {
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if (hw->eeprom.use_eerd == FALSE && e1000_is_onboard_nvm_eeprom(hw)) {
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/* Prepare the EEPROM for bit-bang reading */
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if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
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return -E1000_ERR_EEPROM;
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@ -5198,6 +5259,8 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
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DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
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assert(hw->mac_type != e1000_82576);
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if (hw->mac_type == e1000_ich8lan)
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return FALSE;
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@ -5732,6 +5795,7 @@ e1000_read_mac_addr(struct e1000_hw * hw)
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case e1000_82546:
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case e1000_82546_rev_3:
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case e1000_82571:
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case e1000_82576:
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case e1000_80003es2lan:
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if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
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hw->perm_mac_addr[5] ^= 0x01;
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@ -5944,6 +6008,13 @@ e1000_rar_set(struct e1000_hw *hw,
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case e1000_80003es2lan:
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if (hw->leave_av_bit_off == TRUE)
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break;
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case e1000_82576:
|
||||
/* If MAC address zero, no need to set the AV bit */
|
||||
if (rar_low || rar_high)
|
||||
rar_high |= E1000_RAH_AV;
|
||||
// Only neded when Multiple Receive Queues are enabmed in MRQC
|
||||
rar_high |= E1000_RAH_POOL_1;
|
||||
break;
|
||||
default:
|
||||
/* Indicate to hardware the Address is Valid. */
|
||||
rar_high |= E1000_RAH_AV;
|
||||
|
|
@ -6609,6 +6680,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
|
|||
case e1000_82572:
|
||||
case e1000_82573:
|
||||
case e1000_80003es2lan:
|
||||
case e1000_82576:
|
||||
hw->bus_type = e1000_bus_type_pci_express;
|
||||
hw->bus_speed = e1000_bus_speed_2500;
|
||||
ret_val = e1000_read_pcie_cap_reg(hw,
|
||||
|
|
@ -8027,6 +8099,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
|
|||
case e1000_82573:
|
||||
case e1000_80003es2lan:
|
||||
case e1000_ich8lan:
|
||||
case e1000_82576:
|
||||
while (timeout) {
|
||||
if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
|
||||
break;
|
||||
|
|
@ -8072,6 +8145,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
|
|||
mdelay(10);
|
||||
break;
|
||||
case e1000_80003es2lan:
|
||||
case e1000_82576:
|
||||
/* Separate *_CFG_DONE_* bit for each port */
|
||||
if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
|
||||
cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
|
||||
|
|
@ -8282,6 +8356,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
|
|||
case e1000_82572:
|
||||
case e1000_82573:
|
||||
case e1000_80003es2lan:
|
||||
case e1000_82576:
|
||||
fwsm = E1000_READ_REG(hw, FWSM);
|
||||
if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
|
||||
return TRUE;
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ typedef enum {
|
|||
e1000_82573,
|
||||
e1000_80003es2lan,
|
||||
e1000_ich8lan,
|
||||
e1000_82576,
|
||||
e1000_num_macs
|
||||
} e1000_mac_type;
|
||||
|
||||
|
|
@ -502,6 +503,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
|
|||
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
|
||||
#define E1000_DEV_ID_ICH8_IGP_M 0x104D
|
||||
|
||||
#define E1000_DEV_ID_82576 0x10C9
|
||||
|
||||
#define NODE_ADDRESS_SIZE 6
|
||||
#define ETH_LENGTH_OF_ADDRESS 6
|
||||
|
|
@ -569,7 +571,8 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
|
|||
E1000_IMS_TXDW | \
|
||||
E1000_IMS_RXDMT0 | \
|
||||
E1000_IMS_RXSEQ | \
|
||||
E1000_IMS_LSC)
|
||||
E1000_IMS_LSC | \
|
||||
E1000_IMS_DOUTSYNC)
|
||||
|
||||
/* Additional interrupts need to be handled for e1000_ich8lan:
|
||||
DSW = The FW changed the status of the DISSW bit in FWSM
|
||||
|
|
@ -1748,12 +1751,16 @@ struct e1000_hw {
|
|||
/* Receive Address */
|
||||
#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
|
||||
|
||||
#define E1000_RAH_POOL_1 0x00040000
|
||||
|
||||
/* Interrupt Cause Read */
|
||||
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
|
||||
#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
|
||||
#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
|
||||
#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
|
||||
#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
|
||||
/* LAN connected device generates an interrupt */
|
||||
#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
|
||||
#define E1000_ICR_RXO 0x00000040 /* rx overrun */
|
||||
#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
|
||||
#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
|
||||
|
|
@ -1815,6 +1822,7 @@ struct e1000_hw {
|
|||
#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
|
||||
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
|
||||
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
|
||||
#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
|
||||
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
|
||||
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
|
||||
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
|
||||
|
|
@ -1975,6 +1983,10 @@ struct e1000_hw {
|
|||
#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
|
||||
#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
|
||||
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
|
||||
#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
|
||||
#define IGB_RX_PTHRESH 16
|
||||
#define IGB_RX_HTHRESH 8
|
||||
#define IGB_RX_WTHRESH 1
|
||||
|
||||
/* Transmit Descriptor Control */
|
||||
#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
|
||||
|
|
@ -1985,6 +1997,7 @@ struct e1000_hw {
|
|||
#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
|
||||
#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
|
||||
still to be processed. */
|
||||
#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
|
||||
/* Transmit Configuration Word */
|
||||
#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
|
||||
#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
|
||||
|
|
@ -2034,6 +2047,7 @@ struct e1000_hw {
|
|||
|
||||
/* Multiple Receive Queue Control */
|
||||
#define E1000_MRQC_ENABLE_MASK 0x00000003
|
||||
#define E1000_MRQC_ENABLE_VMDQ 0x00000003
|
||||
#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
|
||||
#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
|
||||
#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
|
||||
|
|
@ -2437,6 +2451,7 @@ struct e1000_host_command_info {
|
|||
#define E1000_PBA_38K 0x0026
|
||||
#define E1000_PBA_40K 0x0028
|
||||
#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
|
||||
#define E1000_PBA_64K 0x0040 /* 64KB */
|
||||
|
||||
#define E1000_PBS_16K E1000_PBA_16K
|
||||
|
||||
|
|
|
|||
Reference in New Issue